10b57cec5SDimitry Andric //===--- AMDGPUMacroFusion.cpp - AMDGPU Macro Fusion ----------------------===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric /// \file This file contains the AMDGPU implementation of the DAG scheduling 100b57cec5SDimitry Andric /// mutation to pair instructions back to back. 110b57cec5SDimitry Andric // 120b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric 140b57cec5SDimitry Andric #include "AMDGPUMacroFusion.h" 150b57cec5SDimitry Andric #include "AMDGPUSubtarget.h" 160b57cec5SDimitry Andric #include "SIInstrInfo.h" 170b57cec5SDimitry Andric #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 180b57cec5SDimitry Andric 190b57cec5SDimitry Andric #include "llvm/CodeGen/MacroFusion.h" 200b57cec5SDimitry Andric 210b57cec5SDimitry Andric using namespace llvm; 220b57cec5SDimitry Andric 230b57cec5SDimitry Andric namespace { 240b57cec5SDimitry Andric 250b57cec5SDimitry Andric /// Check if the instr pair, FirstMI and SecondMI, should be fused 260b57cec5SDimitry Andric /// together. Given SecondMI, when FirstMI is unspecified, then check if 270b57cec5SDimitry Andric /// SecondMI may be part of a fused pair at all. 280b57cec5SDimitry Andric static bool shouldScheduleAdjacent(const TargetInstrInfo &TII_, 290b57cec5SDimitry Andric const TargetSubtargetInfo &TSI, 300b57cec5SDimitry Andric const MachineInstr *FirstMI, 310b57cec5SDimitry Andric const MachineInstr &SecondMI) { 320b57cec5SDimitry Andric const SIInstrInfo &TII = static_cast<const SIInstrInfo&>(TII_); 330b57cec5SDimitry Andric 340b57cec5SDimitry Andric switch (SecondMI.getOpcode()) { 350b57cec5SDimitry Andric case AMDGPU::V_ADDC_U32_e64: 360b57cec5SDimitry Andric case AMDGPU::V_SUBB_U32_e64: 37*5ffd83dbSDimitry Andric case AMDGPU::V_SUBBREV_U32_e64: 380b57cec5SDimitry Andric case AMDGPU::V_CNDMASK_B32_e64: { 390b57cec5SDimitry Andric // Try to cluster defs of condition registers to their uses. This improves 400b57cec5SDimitry Andric // the chance VCC will be available which will allow shrinking to VOP2 410b57cec5SDimitry Andric // encodings. 420b57cec5SDimitry Andric if (!FirstMI) 430b57cec5SDimitry Andric return true; 440b57cec5SDimitry Andric 450b57cec5SDimitry Andric const MachineBasicBlock &MBB = *FirstMI->getParent(); 460b57cec5SDimitry Andric const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 470b57cec5SDimitry Andric const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo(); 480b57cec5SDimitry Andric const MachineOperand *Src2 = TII.getNamedOperand(SecondMI, 490b57cec5SDimitry Andric AMDGPU::OpName::src2); 500b57cec5SDimitry Andric return FirstMI->definesRegister(Src2->getReg(), TRI); 510b57cec5SDimitry Andric } 520b57cec5SDimitry Andric default: 530b57cec5SDimitry Andric return false; 540b57cec5SDimitry Andric } 550b57cec5SDimitry Andric 560b57cec5SDimitry Andric return false; 570b57cec5SDimitry Andric } 580b57cec5SDimitry Andric 590b57cec5SDimitry Andric } // end namespace 600b57cec5SDimitry Andric 610b57cec5SDimitry Andric 620b57cec5SDimitry Andric namespace llvm { 630b57cec5SDimitry Andric 640b57cec5SDimitry Andric std::unique_ptr<ScheduleDAGMutation> createAMDGPUMacroFusionDAGMutation () { 650b57cec5SDimitry Andric return createMacroFusionDAGMutation(shouldScheduleAdjacent); 660b57cec5SDimitry Andric } 670b57cec5SDimitry Andric 680b57cec5SDimitry Andric } // end namespace llvm 69