1*0b57cec5SDimitry Andric //===--- AMDGPUMacroFusion.cpp - AMDGPU Macro Fusion ----------------------===// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric // 9*0b57cec5SDimitry Andric /// \file This file contains the AMDGPU implementation of the DAG scheduling 10*0b57cec5SDimitry Andric /// mutation to pair instructions back to back. 11*0b57cec5SDimitry Andric // 12*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 13*0b57cec5SDimitry Andric 14*0b57cec5SDimitry Andric #include "AMDGPUMacroFusion.h" 15*0b57cec5SDimitry Andric #include "AMDGPUSubtarget.h" 16*0b57cec5SDimitry Andric #include "SIInstrInfo.h" 17*0b57cec5SDimitry Andric #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 18*0b57cec5SDimitry Andric 19*0b57cec5SDimitry Andric #include "llvm/CodeGen/MacroFusion.h" 20*0b57cec5SDimitry Andric 21*0b57cec5SDimitry Andric using namespace llvm; 22*0b57cec5SDimitry Andric 23*0b57cec5SDimitry Andric namespace { 24*0b57cec5SDimitry Andric 25*0b57cec5SDimitry Andric /// Check if the instr pair, FirstMI and SecondMI, should be fused 26*0b57cec5SDimitry Andric /// together. Given SecondMI, when FirstMI is unspecified, then check if 27*0b57cec5SDimitry Andric /// SecondMI may be part of a fused pair at all. 28*0b57cec5SDimitry Andric static bool shouldScheduleAdjacent(const TargetInstrInfo &TII_, 29*0b57cec5SDimitry Andric const TargetSubtargetInfo &TSI, 30*0b57cec5SDimitry Andric const MachineInstr *FirstMI, 31*0b57cec5SDimitry Andric const MachineInstr &SecondMI) { 32*0b57cec5SDimitry Andric const SIInstrInfo &TII = static_cast<const SIInstrInfo&>(TII_); 33*0b57cec5SDimitry Andric 34*0b57cec5SDimitry Andric switch (SecondMI.getOpcode()) { 35*0b57cec5SDimitry Andric case AMDGPU::V_ADDC_U32_e64: 36*0b57cec5SDimitry Andric case AMDGPU::V_SUBB_U32_e64: 37*0b57cec5SDimitry Andric case AMDGPU::V_CNDMASK_B32_e64: { 38*0b57cec5SDimitry Andric // Try to cluster defs of condition registers to their uses. This improves 39*0b57cec5SDimitry Andric // the chance VCC will be available which will allow shrinking to VOP2 40*0b57cec5SDimitry Andric // encodings. 41*0b57cec5SDimitry Andric if (!FirstMI) 42*0b57cec5SDimitry Andric return true; 43*0b57cec5SDimitry Andric 44*0b57cec5SDimitry Andric const MachineBasicBlock &MBB = *FirstMI->getParent(); 45*0b57cec5SDimitry Andric const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 46*0b57cec5SDimitry Andric const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo(); 47*0b57cec5SDimitry Andric const MachineOperand *Src2 = TII.getNamedOperand(SecondMI, 48*0b57cec5SDimitry Andric AMDGPU::OpName::src2); 49*0b57cec5SDimitry Andric return FirstMI->definesRegister(Src2->getReg(), TRI); 50*0b57cec5SDimitry Andric } 51*0b57cec5SDimitry Andric default: 52*0b57cec5SDimitry Andric return false; 53*0b57cec5SDimitry Andric } 54*0b57cec5SDimitry Andric 55*0b57cec5SDimitry Andric return false; 56*0b57cec5SDimitry Andric } 57*0b57cec5SDimitry Andric 58*0b57cec5SDimitry Andric } // end namespace 59*0b57cec5SDimitry Andric 60*0b57cec5SDimitry Andric 61*0b57cec5SDimitry Andric namespace llvm { 62*0b57cec5SDimitry Andric 63*0b57cec5SDimitry Andric std::unique_ptr<ScheduleDAGMutation> createAMDGPUMacroFusionDAGMutation () { 64*0b57cec5SDimitry Andric return createMacroFusionDAGMutation(shouldScheduleAdjacent); 65*0b57cec5SDimitry Andric } 66*0b57cec5SDimitry Andric 67*0b57cec5SDimitry Andric } // end namespace llvm 68