1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// Code to lower AMDGPU MachineInstrs to their corresponding MCInst. 11 // 12 //===----------------------------------------------------------------------===// 13 // 14 15 #include "AMDGPUMCInstLower.h" 16 #include "AMDGPUAsmPrinter.h" 17 #include "AMDGPUMachineFunction.h" 18 #include "AMDGPUTargetMachine.h" 19 #include "MCTargetDesc/AMDGPUInstPrinter.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "llvm/CodeGen/MachineBasicBlock.h" 22 #include "llvm/CodeGen/MachineInstr.h" 23 #include "llvm/IR/Constants.h" 24 #include "llvm/IR/Function.h" 25 #include "llvm/IR/GlobalVariable.h" 26 #include "llvm/MC/MCCodeEmitter.h" 27 #include "llvm/MC/MCContext.h" 28 #include "llvm/MC/MCExpr.h" 29 #include "llvm/MC/MCInst.h" 30 #include "llvm/MC/MCObjectStreamer.h" 31 #include "llvm/MC/MCStreamer.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/Format.h" 34 #include <algorithm> 35 36 using namespace llvm; 37 38 #include "AMDGPUGenMCPseudoLowering.inc" 39 40 AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, 41 const TargetSubtargetInfo &st, 42 const AsmPrinter &ap): 43 Ctx(ctx), ST(st), AP(ap) { } 44 45 static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags) { 46 switch (MOFlags) { 47 default: 48 return MCSymbolRefExpr::VK_None; 49 case SIInstrInfo::MO_GOTPCREL: 50 return MCSymbolRefExpr::VK_GOTPCREL; 51 case SIInstrInfo::MO_GOTPCREL32_LO: 52 return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_LO; 53 case SIInstrInfo::MO_GOTPCREL32_HI: 54 return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_HI; 55 case SIInstrInfo::MO_REL32_LO: 56 return MCSymbolRefExpr::VK_AMDGPU_REL32_LO; 57 case SIInstrInfo::MO_REL32_HI: 58 return MCSymbolRefExpr::VK_AMDGPU_REL32_HI; 59 case SIInstrInfo::MO_ABS32_LO: 60 return MCSymbolRefExpr::VK_AMDGPU_ABS32_LO; 61 case SIInstrInfo::MO_ABS32_HI: 62 return MCSymbolRefExpr::VK_AMDGPU_ABS32_HI; 63 } 64 } 65 66 bool AMDGPUMCInstLower::lowerOperand(const MachineOperand &MO, 67 MCOperand &MCOp) const { 68 switch (MO.getType()) { 69 default: 70 break; 71 case MachineOperand::MO_Immediate: 72 MCOp = MCOperand::createImm(MO.getImm()); 73 return true; 74 case MachineOperand::MO_Register: 75 MCOp = MCOperand::createReg(AMDGPU::getMCReg(MO.getReg(), ST)); 76 return true; 77 case MachineOperand::MO_MachineBasicBlock: 78 MCOp = MCOperand::createExpr( 79 MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx)); 80 return true; 81 case MachineOperand::MO_GlobalAddress: { 82 const GlobalValue *GV = MO.getGlobal(); 83 SmallString<128> SymbolName; 84 AP.getNameWithPrefix(SymbolName, GV); 85 MCSymbol *Sym = Ctx.getOrCreateSymbol(SymbolName); 86 const MCExpr *Expr = 87 MCSymbolRefExpr::create(Sym, getVariantKind(MO.getTargetFlags()),Ctx); 88 int64_t Offset = MO.getOffset(); 89 if (Offset != 0) { 90 Expr = MCBinaryExpr::createAdd(Expr, 91 MCConstantExpr::create(Offset, Ctx), Ctx); 92 } 93 MCOp = MCOperand::createExpr(Expr); 94 return true; 95 } 96 case MachineOperand::MO_ExternalSymbol: { 97 MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(MO.getSymbolName())); 98 Sym->setExternal(true); 99 const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx); 100 MCOp = MCOperand::createExpr(Expr); 101 return true; 102 } 103 case MachineOperand::MO_RegisterMask: 104 // Regmasks are like implicit defs. 105 return false; 106 case MachineOperand::MO_MCSymbol: 107 if (MO.getTargetFlags() == SIInstrInfo::MO_FAR_BRANCH_OFFSET) { 108 MCSymbol *Sym = MO.getMCSymbol(); 109 MCOp = MCOperand::createExpr(Sym->getVariableValue()); 110 return true; 111 } 112 break; 113 } 114 llvm_unreachable("unknown operand type"); 115 } 116 117 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { 118 unsigned Opcode = MI->getOpcode(); 119 const auto *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo()); 120 121 // FIXME: Should be able to handle this with emitPseudoExpansionLowering. We 122 // need to select it to the subtarget specific version, and there's no way to 123 // do that with a single pseudo source operation. 124 if (Opcode == AMDGPU::S_SETPC_B64_return) 125 Opcode = AMDGPU::S_SETPC_B64; 126 else if (Opcode == AMDGPU::SI_CALL) { 127 // SI_CALL is just S_SWAPPC_B64 with an additional operand to track the 128 // called function (which we need to remove here). 129 OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64)); 130 MCOperand Dest, Src; 131 lowerOperand(MI->getOperand(0), Dest); 132 lowerOperand(MI->getOperand(1), Src); 133 OutMI.addOperand(Dest); 134 OutMI.addOperand(Src); 135 return; 136 } else if (Opcode == AMDGPU::SI_TCRETURN) { 137 // TODO: How to use branch immediate and avoid register+add? 138 Opcode = AMDGPU::S_SETPC_B64; 139 } 140 141 int MCOpcode = TII->pseudoToMCOpcode(Opcode); 142 if (MCOpcode == -1) { 143 LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext(); 144 C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have " 145 "a target-specific version: " + Twine(MI->getOpcode())); 146 } 147 148 OutMI.setOpcode(MCOpcode); 149 150 for (const MachineOperand &MO : MI->explicit_operands()) { 151 MCOperand MCOp; 152 lowerOperand(MO, MCOp); 153 OutMI.addOperand(MCOp); 154 } 155 156 int FIIdx = AMDGPU::getNamedOperandIdx(MCOpcode, AMDGPU::OpName::fi); 157 if (FIIdx >= (int)OutMI.getNumOperands()) 158 OutMI.addOperand(MCOperand::createImm(0)); 159 } 160 161 bool AMDGPUAsmPrinter::lowerOperand(const MachineOperand &MO, 162 MCOperand &MCOp) const { 163 const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>(); 164 AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this); 165 return MCInstLowering.lowerOperand(MO, MCOp); 166 } 167 168 const MCExpr *AMDGPUAsmPrinter::lowerConstant(const Constant *CV) { 169 170 // Intercept LDS variables with known addresses 171 if (const GlobalVariable *GV = dyn_cast<GlobalVariable>(CV)) { 172 if (AMDGPUMachineFunction::isKnownAddressLDSGlobal(*GV)) { 173 unsigned offset = 174 AMDGPUMachineFunction::calculateKnownAddressOfLDSGlobal(*GV); 175 Constant *C = ConstantInt::get(CV->getContext(), APInt(32, offset)); 176 return AsmPrinter::lowerConstant(C); 177 } 178 } 179 180 if (const MCExpr *E = lowerAddrSpaceCast(TM, CV, OutContext)) 181 return E; 182 return AsmPrinter::lowerConstant(CV); 183 } 184 185 void AMDGPUAsmPrinter::emitInstruction(const MachineInstr *MI) { 186 // FIXME: Enable feature predicate checks once all the test pass. 187 // AMDGPU_MC::verifyInstructionPredicates(MI->getOpcode(), 188 // getSubtargetInfo().getFeatureBits()); 189 190 if (emitPseudoExpansionLowering(*OutStreamer, MI)) 191 return; 192 193 const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>(); 194 AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this); 195 196 StringRef Err; 197 if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) { 198 LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext(); 199 C.emitError("Illegal instruction detected: " + Err); 200 MI->print(errs()); 201 } 202 203 if (MI->isBundle()) { 204 const MachineBasicBlock *MBB = MI->getParent(); 205 MachineBasicBlock::const_instr_iterator I = ++MI->getIterator(); 206 while (I != MBB->instr_end() && I->isInsideBundle()) { 207 emitInstruction(&*I); 208 ++I; 209 } 210 } else { 211 // We don't want these pseudo instructions encoded. They are 212 // placeholder terminator instructions and should only be printed as 213 // comments. 214 if (MI->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) { 215 if (isVerbose()) 216 OutStreamer->emitRawComment(" return to shader part epilog"); 217 return; 218 } 219 220 if (MI->getOpcode() == AMDGPU::WAVE_BARRIER) { 221 if (isVerbose()) 222 OutStreamer->emitRawComment(" wave barrier"); 223 return; 224 } 225 226 if (MI->getOpcode() == AMDGPU::SCHED_BARRIER) { 227 if (isVerbose()) { 228 std::string HexString; 229 raw_string_ostream HexStream(HexString); 230 HexStream << format_hex(MI->getOperand(0).getImm(), 10, true); 231 OutStreamer->emitRawComment(" sched_barrier mask(" + HexString + ")"); 232 } 233 return; 234 } 235 236 if (MI->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER) { 237 if (isVerbose()) { 238 std::string HexString; 239 raw_string_ostream HexStream(HexString); 240 HexStream << format_hex(MI->getOperand(0).getImm(), 10, true); 241 OutStreamer->emitRawComment( 242 " sched_group_barrier mask(" + HexString + ") size(" + 243 Twine(MI->getOperand(1).getImm()) + ") SyncID(" + 244 Twine(MI->getOperand(2).getImm()) + ")"); 245 } 246 return; 247 } 248 249 if (MI->getOpcode() == AMDGPU::IGLP_OPT) { 250 if (isVerbose()) { 251 std::string HexString; 252 raw_string_ostream HexStream(HexString); 253 HexStream << format_hex(MI->getOperand(0).getImm(), 10, true); 254 OutStreamer->emitRawComment(" iglp_opt mask(" + HexString + ")"); 255 } 256 return; 257 } 258 259 if (MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) { 260 if (isVerbose()) 261 OutStreamer->emitRawComment(" divergent unreachable"); 262 return; 263 } 264 265 if (MI->isMetaInstruction()) { 266 if (isVerbose()) 267 OutStreamer->emitRawComment(" meta instruction"); 268 return; 269 } 270 271 MCInst TmpInst; 272 MCInstLowering.lower(MI, TmpInst); 273 EmitToStreamer(*OutStreamer, TmpInst); 274 275 #ifdef EXPENSIVE_CHECKS 276 // Check getInstSizeInBytes on explicitly specified CPUs (it cannot 277 // work correctly for the generic CPU). 278 // 279 // The isPseudo check really shouldn't be here, but unfortunately there are 280 // some negative lit tests that depend on being able to continue through 281 // here even when pseudo instructions haven't been lowered. 282 // 283 // We also overestimate branch sizes with the offset bug. 284 if (!MI->isPseudo() && STI.isCPUStringValid(STI.getCPU()) && 285 (!STI.hasOffset3fBug() || !MI->isBranch())) { 286 SmallVector<MCFixup, 4> Fixups; 287 SmallVector<char, 16> CodeBytes; 288 raw_svector_ostream CodeStream(CodeBytes); 289 290 std::unique_ptr<MCCodeEmitter> InstEmitter(createSIMCCodeEmitter( 291 *STI.getInstrInfo(), OutContext)); 292 InstEmitter->encodeInstruction(TmpInst, CodeStream, Fixups, STI); 293 294 assert(CodeBytes.size() == STI.getInstrInfo()->getInstSizeInBytes(*MI)); 295 } 296 #endif 297 298 if (DumpCodeInstEmitter) { 299 // Disassemble instruction/operands to text 300 DisasmLines.resize(DisasmLines.size() + 1); 301 std::string &DisasmLine = DisasmLines.back(); 302 raw_string_ostream DisasmStream(DisasmLine); 303 304 AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), *STI.getInstrInfo(), 305 *STI.getRegisterInfo()); 306 InstPrinter.printInst(&TmpInst, 0, StringRef(), STI, DisasmStream); 307 308 // Disassemble instruction/operands to hex representation. 309 SmallVector<MCFixup, 4> Fixups; 310 SmallVector<char, 16> CodeBytes; 311 raw_svector_ostream CodeStream(CodeBytes); 312 313 DumpCodeInstEmitter->encodeInstruction( 314 TmpInst, CodeStream, Fixups, MF->getSubtarget<MCSubtargetInfo>()); 315 HexLines.resize(HexLines.size() + 1); 316 std::string &HexLine = HexLines.back(); 317 raw_string_ostream HexStream(HexLine); 318 319 for (size_t i = 0; i < CodeBytes.size(); i += 4) { 320 unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i]; 321 HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord); 322 } 323 324 DisasmStream.flush(); 325 DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size()); 326 } 327 } 328 } 329