1 //===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the targeting of the Machinelegalizer class for 10 /// AMDGPU. 11 /// \todo This should be generated by TableGen. 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H 15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H 16 17 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 18 #include "AMDGPUArgumentUsageInfo.h" 19 #include "SIInstrInfo.h" 20 21 namespace llvm { 22 23 class GCNTargetMachine; 24 class GCNSubtarget; 25 class MachineIRBuilder; 26 27 namespace AMDGPU { 28 struct ImageDimIntrinsicInfo; 29 } 30 /// This class provides the information for the target register banks. 31 class AMDGPULegalizerInfo final : public LegalizerInfo { 32 const GCNSubtarget &ST; 33 34 public: 35 AMDGPULegalizerInfo(const GCNSubtarget &ST, 36 const GCNTargetMachine &TM); 37 38 bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override; 39 40 Register getSegmentAperture(unsigned AddrSpace, 41 MachineRegisterInfo &MRI, 42 MachineIRBuilder &B) const; 43 44 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI, 45 MachineIRBuilder &B) const; 46 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI, 47 MachineIRBuilder &B) const; 48 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI, 49 MachineIRBuilder &B) const; 50 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI, 51 MachineIRBuilder &B) const; 52 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, 53 MachineIRBuilder &B) const; 54 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI, 55 MachineIRBuilder &B, bool Signed) const; 56 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI, 57 MachineIRBuilder &B, bool Signed) const; 58 bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const; 59 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, 60 MachineIRBuilder &B) const; 61 bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, 62 MachineIRBuilder &B) const; 63 64 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI, 65 MachineIRBuilder &B) const; 66 67 bool buildPCRelGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B, 68 const GlobalValue *GV, int64_t Offset, 69 unsigned GAFlags = SIInstrInfo::MO_NONE) const; 70 71 bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI, 72 MachineIRBuilder &B) const; 73 bool legalizeLoad(LegalizerHelper &Helper, MachineInstr &MI) const; 74 75 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI, 76 MachineIRBuilder &B) const; 77 78 bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI, 79 MachineIRBuilder &B) const; 80 bool legalizeFlog(MachineInstr &MI, MachineIRBuilder &B, 81 double Log2BaseInverted) const; 82 bool legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const; 83 bool legalizeFPow(MachineInstr &MI, MachineIRBuilder &B) const; 84 bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI, 85 MachineIRBuilder &B) const; 86 87 bool legalizeBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI, 88 MachineIRBuilder &B) const; 89 90 void buildMultiply(LegalizerHelper &Helper, MutableArrayRef<Register> Accum, 91 ArrayRef<Register> Src0, ArrayRef<Register> Src1, 92 bool UsePartialMad64_32, 93 bool SeparateOddAlignedProducts) const; 94 bool legalizeMul(LegalizerHelper &Helper, MachineInstr &MI) const; 95 bool legalizeCTLZ_CTTZ(MachineInstr &MI, MachineRegisterInfo &MRI, 96 MachineIRBuilder &B) const; 97 98 bool loadInputValue(Register DstReg, MachineIRBuilder &B, 99 const ArgDescriptor *Arg, 100 const TargetRegisterClass *ArgRC, LLT ArgTy) const; 101 bool loadInputValue(Register DstReg, MachineIRBuilder &B, 102 AMDGPUFunctionArgInfo::PreloadedValue ArgType) const; 103 104 bool legalizePreloadedArgIntrin( 105 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, 106 AMDGPUFunctionArgInfo::PreloadedValue ArgType) const; 107 bool legalizeWorkitemIDIntrinsic( 108 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, 109 unsigned Dim, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const; 110 111 Register getKernargParameterPtr(MachineIRBuilder &B, int64_t Offset) const; 112 bool legalizeKernargMemParameter(MachineInstr &MI, MachineIRBuilder &B, 113 uint64_t Offset, 114 Align Alignment = Align(4)) const; 115 116 bool legalizeUnsignedDIV_REM(MachineInstr &MI, MachineRegisterInfo &MRI, 117 MachineIRBuilder &B) const; 118 119 void legalizeUnsignedDIV_REM32Impl(MachineIRBuilder &B, Register DstDivReg, 120 Register DstRemReg, Register Num, 121 Register Den) const; 122 123 void legalizeUnsignedDIV_REM64Impl(MachineIRBuilder &B, Register DstDivReg, 124 Register DstRemReg, Register Num, 125 Register Den) const; 126 127 bool legalizeSignedDIV_REM(MachineInstr &MI, MachineRegisterInfo &MRI, 128 MachineIRBuilder &B) const; 129 130 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, 131 MachineIRBuilder &B) const; 132 bool legalizeFDIV16(MachineInstr &MI, MachineRegisterInfo &MRI, 133 MachineIRBuilder &B) const; 134 bool legalizeFDIV32(MachineInstr &MI, MachineRegisterInfo &MRI, 135 MachineIRBuilder &B) const; 136 bool legalizeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI, 137 MachineIRBuilder &B) const; 138 bool legalizeFastUnsafeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, 139 MachineIRBuilder &B) const; 140 bool legalizeFastUnsafeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI, 141 MachineIRBuilder &B) const; 142 bool legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI, 143 MachineIRBuilder &B) const; 144 145 bool legalizeRsqClampIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, 146 MachineIRBuilder &B) const; 147 148 bool legalizeDSAtomicFPIntrinsic(LegalizerHelper &Helper, 149 MachineInstr &MI, Intrinsic::ID IID) const; 150 151 bool getImplicitArgPtr(Register DstReg, MachineRegisterInfo &MRI, 152 MachineIRBuilder &B) const; 153 154 bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI, 155 MachineIRBuilder &B) const; 156 157 bool getLDSKernelId(Register DstReg, MachineRegisterInfo &MRI, 158 MachineIRBuilder &B) const; 159 160 bool legalizeLDSKernelId(MachineInstr &MI, MachineRegisterInfo &MRI, 161 MachineIRBuilder &B) const; 162 163 bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI, 164 MachineIRBuilder &B, unsigned AddrSpace) const; 165 166 std::pair<Register, unsigned> splitBufferOffsets(MachineIRBuilder &B, 167 Register OrigOffset) const; 168 void updateBufferMMO(MachineMemOperand *MMO, Register VOffset, 169 Register SOffset, unsigned ImmOffset, Register VIndex, 170 MachineRegisterInfo &MRI) const; 171 172 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, 173 Register Reg, bool ImageStore = false) const; 174 bool legalizeRawBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI, 175 MachineIRBuilder &B, bool IsFormat) const; 176 bool legalizeRawBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI, 177 MachineIRBuilder &B, bool IsFormat) const; 178 Register fixStoreSourceType(MachineIRBuilder &B, Register VData, 179 bool IsFormat) const; 180 181 bool legalizeBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI, 182 MachineIRBuilder &B, bool IsTyped, 183 bool IsFormat) const; 184 bool legalizeBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI, 185 MachineIRBuilder &B, bool IsFormat, 186 bool IsTyped) const; 187 bool legalizeBufferAtomic(MachineInstr &MI, MachineIRBuilder &B, 188 Intrinsic::ID IID) const; 189 190 bool legalizeBVHIntrinsic(MachineInstr &MI, MachineIRBuilder &B) const; 191 192 bool legalizeFPTruncRound(MachineInstr &MI, MachineIRBuilder &B) const; 193 194 bool legalizeImageIntrinsic( 195 MachineInstr &MI, MachineIRBuilder &B, 196 GISelChangeObserver &Observer, 197 const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const; 198 199 bool legalizeSBufferLoad(LegalizerHelper &Helper, MachineInstr &MI) const; 200 201 bool legalizeAtomicIncDec(MachineInstr &MI, MachineIRBuilder &B, 202 bool IsInc) const; 203 204 bool legalizeTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, 205 MachineIRBuilder &B) const; 206 bool legalizeTrapEndpgm(MachineInstr &MI, MachineRegisterInfo &MRI, 207 MachineIRBuilder &B) const; 208 bool legalizeTrapHsaQueuePtr(MachineInstr &MI, MachineRegisterInfo &MRI, 209 MachineIRBuilder &B) const; 210 bool legalizeTrapHsa(MachineInstr &MI, MachineRegisterInfo &MRI, 211 MachineIRBuilder &B) const; 212 bool legalizeDebugTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, 213 MachineIRBuilder &B) const; 214 215 bool legalizeIntrinsic(LegalizerHelper &Helper, 216 MachineInstr &MI) const override; 217 }; 218 } // End llvm namespace. 219 #endif 220