1 //===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the targeting of the Machinelegalizer class for 10 /// AMDGPU. 11 /// \todo This should be generated by TableGen. 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H 15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H 16 17 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 18 #include "AMDGPUArgumentUsageInfo.h" 19 #include "SIInstrInfo.h" 20 21 namespace llvm { 22 23 class GCNTargetMachine; 24 class GCNSubtarget; 25 class MachineIRBuilder; 26 27 namespace AMDGPU { 28 struct ImageDimIntrinsicInfo; 29 } 30 /// This class provides the information for the target register banks. 31 class AMDGPULegalizerInfo final : public LegalizerInfo { 32 const GCNSubtarget &ST; 33 34 public: 35 AMDGPULegalizerInfo(const GCNSubtarget &ST, 36 const GCNTargetMachine &TM); 37 38 bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override; 39 40 Register getSegmentAperture(unsigned AddrSpace, 41 MachineRegisterInfo &MRI, 42 MachineIRBuilder &B) const; 43 44 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI, 45 MachineIRBuilder &B) const; 46 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI, 47 MachineIRBuilder &B) const; 48 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI, 49 MachineIRBuilder &B) const; 50 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI, 51 MachineIRBuilder &B) const; 52 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, 53 MachineIRBuilder &B) const; 54 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI, 55 MachineIRBuilder &B, bool Signed) const; 56 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI, 57 MachineIRBuilder &B, bool Signed) const; 58 bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const; 59 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, 60 MachineIRBuilder &B) const; 61 bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, 62 MachineIRBuilder &B) const; 63 bool legalizeShuffleVector(MachineInstr &MI, MachineRegisterInfo &MRI, 64 MachineIRBuilder &B) const; 65 66 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI, 67 MachineIRBuilder &B) const; 68 69 bool buildPCRelGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B, 70 const GlobalValue *GV, int64_t Offset, 71 unsigned GAFlags = SIInstrInfo::MO_NONE) const; 72 73 bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI, 74 MachineIRBuilder &B) const; 75 bool legalizeLoad(LegalizerHelper &Helper, MachineInstr &MI) const; 76 77 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI, 78 MachineIRBuilder &B) const; 79 80 bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI, 81 MachineIRBuilder &B) const; 82 bool legalizeFlog(MachineInstr &MI, MachineIRBuilder &B, 83 double Log2BaseInverted) const; 84 bool legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const; 85 bool legalizeFPow(MachineInstr &MI, MachineIRBuilder &B) const; 86 bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI, 87 MachineIRBuilder &B) const; 88 89 bool legalizeBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI, 90 MachineIRBuilder &B) const; 91 92 void buildMultiply(LegalizerHelper &Helper, MutableArrayRef<Register> Accum, 93 ArrayRef<Register> Src0, ArrayRef<Register> Src1, 94 bool UsePartialMad64_32, 95 bool SeparateOddAlignedProducts) const; 96 bool legalizeMul(LegalizerHelper &Helper, MachineInstr &MI) const; 97 bool legalizeCTLZ_CTTZ(MachineInstr &MI, MachineRegisterInfo &MRI, 98 MachineIRBuilder &B) const; 99 100 bool loadInputValue(Register DstReg, MachineIRBuilder &B, 101 const ArgDescriptor *Arg, 102 const TargetRegisterClass *ArgRC, LLT ArgTy) const; 103 bool loadInputValue(Register DstReg, MachineIRBuilder &B, 104 AMDGPUFunctionArgInfo::PreloadedValue ArgType) const; 105 106 bool legalizePreloadedArgIntrin( 107 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, 108 AMDGPUFunctionArgInfo::PreloadedValue ArgType) const; 109 bool legalizeWorkitemIDIntrinsic( 110 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, 111 unsigned Dim, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const; 112 113 Register getKernargParameterPtr(MachineIRBuilder &B, int64_t Offset) const; 114 bool legalizeKernargMemParameter(MachineInstr &MI, MachineIRBuilder &B, 115 uint64_t Offset, 116 Align Alignment = Align(4)) const; 117 118 bool legalizeUnsignedDIV_REM(MachineInstr &MI, MachineRegisterInfo &MRI, 119 MachineIRBuilder &B) const; 120 121 void legalizeUnsignedDIV_REM32Impl(MachineIRBuilder &B, Register DstDivReg, 122 Register DstRemReg, Register Num, 123 Register Den) const; 124 125 void legalizeUnsignedDIV_REM64Impl(MachineIRBuilder &B, Register DstDivReg, 126 Register DstRemReg, Register Num, 127 Register Den) const; 128 129 bool legalizeSignedDIV_REM(MachineInstr &MI, MachineRegisterInfo &MRI, 130 MachineIRBuilder &B) const; 131 132 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, 133 MachineIRBuilder &B) const; 134 bool legalizeFDIV16(MachineInstr &MI, MachineRegisterInfo &MRI, 135 MachineIRBuilder &B) const; 136 bool legalizeFDIV32(MachineInstr &MI, MachineRegisterInfo &MRI, 137 MachineIRBuilder &B) const; 138 bool legalizeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI, 139 MachineIRBuilder &B) const; 140 bool legalizeFastUnsafeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, 141 MachineIRBuilder &B) const; 142 bool legalizeFastUnsafeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI, 143 MachineIRBuilder &B) const; 144 bool legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI, 145 MachineIRBuilder &B) const; 146 147 bool legalizeRsqClampIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, 148 MachineIRBuilder &B) const; 149 150 bool legalizeDSAtomicFPIntrinsic(LegalizerHelper &Helper, 151 MachineInstr &MI, Intrinsic::ID IID) const; 152 153 bool getImplicitArgPtr(Register DstReg, MachineRegisterInfo &MRI, 154 MachineIRBuilder &B) const; 155 156 bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI, 157 MachineIRBuilder &B) const; 158 159 bool getLDSKernelId(Register DstReg, MachineRegisterInfo &MRI, 160 MachineIRBuilder &B) const; 161 162 bool legalizeLDSKernelId(MachineInstr &MI, MachineRegisterInfo &MRI, 163 MachineIRBuilder &B) const; 164 165 bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI, 166 MachineIRBuilder &B, unsigned AddrSpace) const; 167 168 std::pair<Register, unsigned> splitBufferOffsets(MachineIRBuilder &B, 169 Register OrigOffset) const; 170 void updateBufferMMO(MachineMemOperand *MMO, Register VOffset, 171 Register SOffset, unsigned ImmOffset, Register VIndex, 172 MachineRegisterInfo &MRI) const; 173 174 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, 175 Register Reg, bool ImageStore = false) const; 176 bool legalizeRawBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI, 177 MachineIRBuilder &B, bool IsFormat) const; 178 bool legalizeRawBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI, 179 MachineIRBuilder &B, bool IsFormat) const; 180 Register fixStoreSourceType(MachineIRBuilder &B, Register VData, 181 bool IsFormat) const; 182 183 bool legalizeBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI, 184 MachineIRBuilder &B, bool IsTyped, 185 bool IsFormat) const; 186 bool legalizeBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI, 187 MachineIRBuilder &B, bool IsFormat, 188 bool IsTyped) const; 189 bool legalizeBufferAtomic(MachineInstr &MI, MachineIRBuilder &B, 190 Intrinsic::ID IID) const; 191 192 bool legalizeBVHIntrinsic(MachineInstr &MI, MachineIRBuilder &B) const; 193 194 bool legalizeFPTruncRound(MachineInstr &MI, MachineIRBuilder &B) const; 195 196 bool legalizeImageIntrinsic( 197 MachineInstr &MI, MachineIRBuilder &B, 198 GISelChangeObserver &Observer, 199 const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const; 200 201 bool legalizeSBufferLoad(LegalizerHelper &Helper, MachineInstr &MI) const; 202 203 bool legalizeAtomicIncDec(MachineInstr &MI, MachineIRBuilder &B, 204 bool IsInc) const; 205 206 bool legalizeTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, 207 MachineIRBuilder &B) const; 208 bool legalizeTrapEndpgm(MachineInstr &MI, MachineRegisterInfo &MRI, 209 MachineIRBuilder &B) const; 210 bool legalizeTrapHsaQueuePtr(MachineInstr &MI, MachineRegisterInfo &MRI, 211 MachineIRBuilder &B) const; 212 bool legalizeTrapHsa(MachineInstr &MI, MachineRegisterInfo &MRI, 213 MachineIRBuilder &B) const; 214 bool legalizeDebugTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, 215 MachineIRBuilder &B) const; 216 217 bool legalizeIntrinsic(LegalizerHelper &Helper, 218 MachineInstr &MI) const override; 219 }; 220 } // End llvm namespace. 221 #endif 222