1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the targeting of the InstructionSelector class for 10 /// AMDGPU. 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H 14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H 15 16 #include "AMDGPU.h" 17 #include "AMDGPUArgumentUsageInfo.h" 18 #include "llvm/ADT/ArrayRef.h" 19 #include "llvm/ADT/SmallVector.h" 20 #include "llvm/CodeGen/Register.h" 21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 22 #include "llvm/IR/InstrTypes.h" 23 24 namespace { 25 #define GET_GLOBALISEL_PREDICATE_BITSET 26 #define AMDGPUSubtarget GCNSubtarget 27 #include "AMDGPUGenGlobalISel.inc" 28 #undef GET_GLOBALISEL_PREDICATE_BITSET 29 #undef AMDGPUSubtarget 30 } 31 32 namespace llvm { 33 34 class AMDGPUInstrInfo; 35 class AMDGPURegisterBankInfo; 36 class GCNSubtarget; 37 class MachineInstr; 38 class MachineIRBuilder; 39 class MachineOperand; 40 class MachineRegisterInfo; 41 class SIInstrInfo; 42 class SIMachineFunctionInfo; 43 class SIRegisterInfo; 44 45 class AMDGPUInstructionSelector : public InstructionSelector { 46 private: 47 MachineRegisterInfo *MRI; 48 49 public: 50 AMDGPUInstructionSelector(const GCNSubtarget &STI, 51 const AMDGPURegisterBankInfo &RBI, 52 const AMDGPUTargetMachine &TM); 53 54 bool select(MachineInstr &I) override; 55 static const char *getName(); 56 57 void setupMF(MachineFunction &MF, GISelKnownBits &KB, 58 CodeGenCoverage &CoverageInfo) override; 59 60 private: 61 struct GEPInfo { 62 const MachineInstr &GEP; 63 SmallVector<unsigned, 2> SgprParts; 64 SmallVector<unsigned, 2> VgprParts; 65 int64_t Imm; 66 GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { } 67 }; 68 69 bool isInstrUniform(const MachineInstr &MI) const; 70 bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const; 71 72 /// tblgen-erated 'select' implementation. 73 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const; 74 75 MachineOperand getSubOperand64(MachineOperand &MO, 76 const TargetRegisterClass &SubRC, 77 unsigned SubIdx) const; 78 bool selectCOPY(MachineInstr &I) const; 79 bool selectPHI(MachineInstr &I) const; 80 bool selectG_TRUNC(MachineInstr &I) const; 81 bool selectG_SZA_EXT(MachineInstr &I) const; 82 bool selectG_SITOFP_UITOFP(MachineInstr &I) const; 83 bool selectG_CONSTANT(MachineInstr &I) const; 84 bool selectG_AND_OR_XOR(MachineInstr &I) const; 85 bool selectG_ADD_SUB(MachineInstr &I) const; 86 bool selectG_UADDO_USUBO(MachineInstr &I) const; 87 bool selectG_EXTRACT(MachineInstr &I) const; 88 bool selectG_MERGE_VALUES(MachineInstr &I) const; 89 bool selectG_UNMERGE_VALUES(MachineInstr &I) const; 90 bool selectG_GEP(MachineInstr &I) const; 91 bool selectG_IMPLICIT_DEF(MachineInstr &I) const; 92 bool selectG_INSERT(MachineInstr &I) const; 93 bool selectG_INTRINSIC(MachineInstr &I) const; 94 95 std::tuple<Register, unsigned, unsigned> 96 splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const; 97 98 bool selectStoreIntrinsic(MachineInstr &MI, bool IsFormat) const; 99 100 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const; 101 int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const; 102 bool selectG_ICMP(MachineInstr &I) const; 103 bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const; 104 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI, 105 SmallVectorImpl<GEPInfo> &AddrInfo) const; 106 bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const; 107 108 void initM0(MachineInstr &I) const; 109 bool selectG_LOAD_ATOMICRMW(MachineInstr &I) const; 110 bool selectG_STORE(MachineInstr &I) const; 111 bool selectG_SELECT(MachineInstr &I) const; 112 bool selectG_BRCOND(MachineInstr &I) const; 113 bool selectG_FRAME_INDEX(MachineInstr &I) const; 114 bool selectG_PTR_MASK(MachineInstr &I) const; 115 116 std::pair<Register, unsigned> 117 selectVOP3ModsImpl(Register Src) const; 118 119 InstructionSelector::ComplexRendererFns 120 selectVCSRC(MachineOperand &Root) const; 121 122 InstructionSelector::ComplexRendererFns 123 selectVSRC0(MachineOperand &Root) const; 124 125 InstructionSelector::ComplexRendererFns 126 selectVOP3Mods0(MachineOperand &Root) const; 127 InstructionSelector::ComplexRendererFns 128 selectVOP3Mods0Clamp0OMod(MachineOperand &Root) const; 129 InstructionSelector::ComplexRendererFns 130 selectVOP3OMods(MachineOperand &Root) const; 131 InstructionSelector::ComplexRendererFns 132 selectVOP3Mods(MachineOperand &Root) const; 133 134 InstructionSelector::ComplexRendererFns 135 selectVOP3OpSelMods0(MachineOperand &Root) const; 136 InstructionSelector::ComplexRendererFns 137 selectVOP3OpSelMods(MachineOperand &Root) const; 138 139 InstructionSelector::ComplexRendererFns 140 selectSmrdImm(MachineOperand &Root) const; 141 InstructionSelector::ComplexRendererFns 142 selectSmrdImm32(MachineOperand &Root) const; 143 InstructionSelector::ComplexRendererFns 144 selectSmrdSgpr(MachineOperand &Root) const; 145 146 template <bool Signed> 147 InstructionSelector::ComplexRendererFns 148 selectFlatOffsetImpl(MachineOperand &Root) const; 149 InstructionSelector::ComplexRendererFns 150 selectFlatOffset(MachineOperand &Root) const; 151 152 InstructionSelector::ComplexRendererFns 153 selectFlatOffsetSigned(MachineOperand &Root) const; 154 155 InstructionSelector::ComplexRendererFns 156 selectMUBUFScratchOffen(MachineOperand &Root) const; 157 InstructionSelector::ComplexRendererFns 158 selectMUBUFScratchOffset(MachineOperand &Root) const; 159 160 bool isDSOffsetLegal(const MachineRegisterInfo &MRI, 161 const MachineOperand &Base, 162 int64_t Offset, unsigned OffsetBits) const; 163 164 InstructionSelector::ComplexRendererFns 165 selectDS1Addr1Offset(MachineOperand &Root) const; 166 167 void renderTruncImm32(MachineInstrBuilder &MIB, 168 const MachineInstr &MI) const; 169 170 const SIInstrInfo &TII; 171 const SIRegisterInfo &TRI; 172 const AMDGPURegisterBankInfo &RBI; 173 const AMDGPUTargetMachine &TM; 174 const GCNSubtarget &STI; 175 bool EnableLateStructurizeCFG; 176 #define GET_GLOBALISEL_PREDICATES_DECL 177 #define AMDGPUSubtarget GCNSubtarget 178 #include "AMDGPUGenGlobalISel.inc" 179 #undef GET_GLOBALISEL_PREDICATES_DECL 180 #undef AMDGPUSubtarget 181 182 #define GET_GLOBALISEL_TEMPORARIES_DECL 183 #include "AMDGPUGenGlobalISel.inc" 184 #undef GET_GLOBALISEL_TEMPORARIES_DECL 185 }; 186 187 } // End llvm namespace. 188 #endif 189