1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the targeting of the InstructionSelector class for 10 /// AMDGPU. 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H 14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H 15 16 #include "SIDefines.h" 17 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 18 #include "llvm/IR/InstrTypes.h" 19 20 namespace { 21 #define GET_GLOBALISEL_PREDICATE_BITSET 22 #define AMDGPUSubtarget GCNSubtarget 23 #include "AMDGPUGenGlobalISel.inc" 24 #undef GET_GLOBALISEL_PREDICATE_BITSET 25 #undef AMDGPUSubtarget 26 } 27 28 namespace llvm { 29 30 namespace AMDGPU { 31 struct ImageDimIntrinsicInfo; 32 } 33 34 class AMDGPURegisterBankInfo; 35 class AMDGPUTargetMachine; 36 class BlockFrequencyInfo; 37 class ProfileSummaryInfo; 38 class GCNSubtarget; 39 class MachineInstr; 40 class MachineIRBuilder; 41 class MachineOperand; 42 class MachineRegisterInfo; 43 class RegisterBank; 44 class SIInstrInfo; 45 class SIRegisterInfo; 46 class TargetRegisterClass; 47 48 class AMDGPUInstructionSelector final : public InstructionSelector { 49 private: 50 MachineRegisterInfo *MRI; 51 const GCNSubtarget *Subtarget; 52 53 public: 54 AMDGPUInstructionSelector(const GCNSubtarget &STI, 55 const AMDGPURegisterBankInfo &RBI, 56 const AMDGPUTargetMachine &TM); 57 58 bool select(MachineInstr &I) override; 59 static const char *getName(); 60 61 void setupMF(MachineFunction &MF, GISelKnownBits *KB, 62 CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI, 63 BlockFrequencyInfo *BFI) override; 64 65 private: 66 struct GEPInfo { 67 SmallVector<unsigned, 2> SgprParts; 68 SmallVector<unsigned, 2> VgprParts; 69 int64_t Imm = 0; 70 }; 71 72 bool isSGPR(Register Reg) const; 73 74 bool isInstrUniform(const MachineInstr &MI) const; 75 bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const; 76 77 const RegisterBank *getArtifactRegBank( 78 Register Reg, const MachineRegisterInfo &MRI, 79 const TargetRegisterInfo &TRI) const; 80 81 /// tblgen-erated 'select' implementation. 82 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const; 83 84 MachineOperand getSubOperand64(MachineOperand &MO, 85 const TargetRegisterClass &SubRC, 86 unsigned SubIdx) const; 87 88 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const; 89 bool selectCOPY(MachineInstr &I) const; 90 bool selectPHI(MachineInstr &I) const; 91 bool selectG_TRUNC(MachineInstr &I) const; 92 bool selectG_SZA_EXT(MachineInstr &I) const; 93 bool selectG_CONSTANT(MachineInstr &I) const; 94 bool selectG_FNEG(MachineInstr &I) const; 95 bool selectG_FABS(MachineInstr &I) const; 96 bool selectG_AND_OR_XOR(MachineInstr &I) const; 97 bool selectG_ADD_SUB(MachineInstr &I) const; 98 bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const; 99 bool selectG_AMDGPU_MAD_64_32(MachineInstr &I) const; 100 bool selectG_EXTRACT(MachineInstr &I) const; 101 bool selectG_FMA_FMAD(MachineInstr &I) const; 102 bool selectG_MERGE_VALUES(MachineInstr &I) const; 103 bool selectG_UNMERGE_VALUES(MachineInstr &I) const; 104 bool selectG_BUILD_VECTOR(MachineInstr &I) const; 105 bool selectG_PTR_ADD(MachineInstr &I) const; 106 bool selectG_IMPLICIT_DEF(MachineInstr &I) const; 107 bool selectG_INSERT(MachineInstr &I) const; 108 bool selectG_SBFX_UBFX(MachineInstr &I) const; 109 110 bool selectInterpP1F16(MachineInstr &MI) const; 111 bool selectWritelane(MachineInstr &MI) const; 112 bool selectDivScale(MachineInstr &MI) const; 113 bool selectIntrinsicCmp(MachineInstr &MI) const; 114 bool selectBallot(MachineInstr &I) const; 115 bool selectInverseBallot(MachineInstr &I) const; 116 bool selectRelocConstant(MachineInstr &I) const; 117 bool selectGroupStaticSize(MachineInstr &I) const; 118 bool selectReturnAddress(MachineInstr &I) const; 119 bool selectG_INTRINSIC(MachineInstr &I) const; 120 121 bool selectEndCfIntrinsic(MachineInstr &MI) const; 122 bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const; 123 bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const; 124 bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const; 125 bool selectSBarrier(MachineInstr &MI) const; 126 bool selectDSBvhStackIntrinsic(MachineInstr &MI) const; 127 128 bool selectImageIntrinsic(MachineInstr &MI, 129 const AMDGPU::ImageDimIntrinsicInfo *Intr) const; 130 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const; 131 int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const; 132 bool selectG_ICMP(MachineInstr &I) const; 133 bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const; 134 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI, 135 SmallVectorImpl<GEPInfo> &AddrInfo) const; 136 137 void initM0(MachineInstr &I) const; 138 bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const; 139 bool selectG_SELECT(MachineInstr &I) const; 140 bool selectG_BRCOND(MachineInstr &I) const; 141 bool selectG_GLOBAL_VALUE(MachineInstr &I) const; 142 bool selectG_PTRMASK(MachineInstr &I) const; 143 bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const; 144 bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const; 145 bool selectBufferLoadLds(MachineInstr &MI) const; 146 bool selectGlobalLoadLds(MachineInstr &MI) const; 147 bool selectBVHIntrinsic(MachineInstr &I) const; 148 bool selectSMFMACIntrin(MachineInstr &I) const; 149 bool selectWaveAddress(MachineInstr &I) const; 150 151 std::pair<Register, unsigned> selectVOP3ModsImpl(MachineOperand &Root, 152 bool IsCanonicalizing = true, 153 bool AllowAbs = true, 154 bool OpSel = false) const; 155 156 Register copyToVGPRIfSrcFolded(Register Src, unsigned Mods, 157 MachineOperand Root, MachineInstr *InsertPt, 158 bool ForceVGPR = false) const; 159 160 InstructionSelector::ComplexRendererFns 161 selectVCSRC(MachineOperand &Root) const; 162 163 InstructionSelector::ComplexRendererFns 164 selectVSRC0(MachineOperand &Root) const; 165 166 InstructionSelector::ComplexRendererFns 167 selectVOP3Mods0(MachineOperand &Root) const; 168 InstructionSelector::ComplexRendererFns 169 selectVOP3BMods0(MachineOperand &Root) const; 170 InstructionSelector::ComplexRendererFns 171 selectVOP3OMods(MachineOperand &Root) const; 172 InstructionSelector::ComplexRendererFns 173 selectVOP3Mods(MachineOperand &Root) const; 174 InstructionSelector::ComplexRendererFns 175 selectVOP3ModsNonCanonicalizing(MachineOperand &Root) const; 176 InstructionSelector::ComplexRendererFns 177 selectVOP3BMods(MachineOperand &Root) const; 178 179 ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const; 180 181 std::pair<Register, unsigned> 182 selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI, 183 bool IsDOT = false) const; 184 185 InstructionSelector::ComplexRendererFns 186 selectVOP3PMods(MachineOperand &Root) const; 187 188 InstructionSelector::ComplexRendererFns 189 selectVOP3PModsDOT(MachineOperand &Root) const; 190 191 InstructionSelector::ComplexRendererFns 192 selectDotIUVOP3PMods(MachineOperand &Root) const; 193 194 InstructionSelector::ComplexRendererFns 195 selectWMMAOpSelVOP3PMods(MachineOperand &Root) const; 196 197 InstructionSelector::ComplexRendererFns 198 selectVOP3OpSelMods(MachineOperand &Root) const; 199 200 InstructionSelector::ComplexRendererFns 201 selectVINTERPMods(MachineOperand &Root) const; 202 InstructionSelector::ComplexRendererFns 203 selectVINTERPModsHi(MachineOperand &Root) const; 204 205 bool selectSmrdOffset(MachineOperand &Root, Register &Base, Register *SOffset, 206 int64_t *Offset) const; 207 InstructionSelector::ComplexRendererFns 208 selectSmrdImm(MachineOperand &Root) const; 209 InstructionSelector::ComplexRendererFns 210 selectSmrdImm32(MachineOperand &Root) const; 211 InstructionSelector::ComplexRendererFns 212 selectSmrdSgpr(MachineOperand &Root) const; 213 InstructionSelector::ComplexRendererFns 214 selectSmrdSgprImm(MachineOperand &Root) const; 215 216 std::pair<Register, int> selectFlatOffsetImpl(MachineOperand &Root, 217 uint64_t FlatVariant) const; 218 219 InstructionSelector::ComplexRendererFns 220 selectFlatOffset(MachineOperand &Root) const; 221 InstructionSelector::ComplexRendererFns 222 selectGlobalOffset(MachineOperand &Root) const; 223 InstructionSelector::ComplexRendererFns 224 selectScratchOffset(MachineOperand &Root) const; 225 226 InstructionSelector::ComplexRendererFns 227 selectGlobalSAddr(MachineOperand &Root) const; 228 229 InstructionSelector::ComplexRendererFns 230 selectScratchSAddr(MachineOperand &Root) const; 231 bool checkFlatScratchSVSSwizzleBug(Register VAddr, Register SAddr, 232 uint64_t ImmOffset) const; 233 InstructionSelector::ComplexRendererFns 234 selectScratchSVAddr(MachineOperand &Root) const; 235 236 InstructionSelector::ComplexRendererFns 237 selectMUBUFScratchOffen(MachineOperand &Root) const; 238 InstructionSelector::ComplexRendererFns 239 selectMUBUFScratchOffset(MachineOperand &Root) const; 240 241 bool isDSOffsetLegal(Register Base, int64_t Offset) const; 242 bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1, 243 unsigned Size) const; 244 bool isFlatScratchBaseLegal( 245 Register Base, uint64_t FlatVariant = SIInstrFlags::FlatScratch) const; 246 247 std::pair<Register, unsigned> 248 selectDS1Addr1OffsetImpl(MachineOperand &Root) const; 249 InstructionSelector::ComplexRendererFns 250 selectDS1Addr1Offset(MachineOperand &Root) const; 251 252 InstructionSelector::ComplexRendererFns 253 selectDS64Bit4ByteAligned(MachineOperand &Root) const; 254 255 InstructionSelector::ComplexRendererFns 256 selectDS128Bit8ByteAligned(MachineOperand &Root) const; 257 258 std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root, 259 unsigned size) const; 260 InstructionSelector::ComplexRendererFns 261 selectDSReadWrite2(MachineOperand &Root, unsigned size) const; 262 263 std::pair<Register, int64_t> 264 getPtrBaseWithConstantOffset(Register Root, 265 const MachineRegisterInfo &MRI) const; 266 267 // Parse out a chain of up to two g_ptr_add instructions. 268 // g_ptr_add (n0, _) 269 // g_ptr_add (n0, (n1 = g_ptr_add n2, n3)) 270 struct MUBUFAddressData { 271 Register N0, N2, N3; 272 int64_t Offset = 0; 273 }; 274 275 bool shouldUseAddr64(MUBUFAddressData AddrData) const; 276 277 void splitIllegalMUBUFOffset(MachineIRBuilder &B, 278 Register &SOffset, int64_t &ImmOffset) const; 279 280 MUBUFAddressData parseMUBUFAddress(Register Src) const; 281 282 bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr, 283 Register &RSrcReg, Register &SOffset, 284 int64_t &Offset) const; 285 286 bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg, 287 Register &SOffset, int64_t &Offset) const; 288 289 InstructionSelector::ComplexRendererFns 290 selectMUBUFAddr64(MachineOperand &Root) const; 291 292 InstructionSelector::ComplexRendererFns 293 selectMUBUFOffset(MachineOperand &Root) const; 294 295 ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const; 296 ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const; 297 ComplexRendererFns selectSMRDBufferSgprImm(MachineOperand &Root) const; 298 299 std::pair<Register, unsigned> selectVOP3PMadMixModsImpl(MachineOperand &Root, 300 bool &Matched) const; 301 ComplexRendererFns selectVOP3PMadMixModsExt(MachineOperand &Root) const; 302 ComplexRendererFns selectVOP3PMadMixMods(MachineOperand &Root) const; 303 304 void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI, 305 int OpIdx = -1) const; 306 307 void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI, 308 int OpIdx) const; 309 310 void renderOpSelTImm(MachineInstrBuilder &MIB, const MachineInstr &MI, 311 int OpIdx) const; 312 313 void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI, 314 int OpIdx) const; 315 316 void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI, 317 int OpIdx) const; 318 319 void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI, 320 int OpIdx) const; 321 void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI, 322 int OpIdx) const; 323 void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI, 324 int OpIdx) const; 325 void renderSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI, 326 int OpIdx) const; 327 328 void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI, 329 int OpIdx) const; 330 331 bool isInlineImmediate16(int64_t Imm) const; 332 bool isInlineImmediate32(int64_t Imm) const; 333 bool isInlineImmediate64(int64_t Imm) const; 334 bool isInlineImmediate(const APFloat &Imm) const; 335 336 // Returns true if TargetOpcode::G_AND MachineInstr `MI`'s masking of the 337 // shift amount operand's `ShAmtBits` bits is unneeded. 338 bool isUnneededShiftMask(const MachineInstr &MI, unsigned ShAmtBits) const; 339 340 const SIInstrInfo &TII; 341 const SIRegisterInfo &TRI; 342 const AMDGPURegisterBankInfo &RBI; 343 const AMDGPUTargetMachine &TM; 344 const GCNSubtarget &STI; 345 bool EnableLateStructurizeCFG; 346 #define GET_GLOBALISEL_PREDICATES_DECL 347 #define AMDGPUSubtarget GCNSubtarget 348 #include "AMDGPUGenGlobalISel.inc" 349 #undef GET_GLOBALISEL_PREDICATES_DECL 350 #undef AMDGPUSubtarget 351 352 #define GET_GLOBALISEL_TEMPORARIES_DECL 353 #include "AMDGPUGenGlobalISel.inc" 354 #undef GET_GLOBALISEL_TEMPORARIES_DECL 355 }; 356 357 } // End llvm namespace. 358 #endif 359