1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the targeting of the InstructionSelector class for 10 /// AMDGPU. 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H 14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H 15 16 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 17 #include "llvm/IR/InstrTypes.h" 18 19 namespace { 20 #define GET_GLOBALISEL_PREDICATE_BITSET 21 #define AMDGPUSubtarget GCNSubtarget 22 #include "AMDGPUGenGlobalISel.inc" 23 #undef GET_GLOBALISEL_PREDICATE_BITSET 24 #undef AMDGPUSubtarget 25 } 26 27 namespace llvm { 28 29 namespace AMDGPU { 30 struct ImageDimIntrinsicInfo; 31 } 32 33 class AMDGPURegisterBankInfo; 34 class AMDGPUTargetMachine; 35 class BlockFrequencyInfo; 36 class ProfileSummaryInfo; 37 class GCNSubtarget; 38 class MachineInstr; 39 class MachineIRBuilder; 40 class MachineOperand; 41 class MachineRegisterInfo; 42 class RegisterBank; 43 class SIInstrInfo; 44 class SIRegisterInfo; 45 class TargetRegisterClass; 46 47 class AMDGPUInstructionSelector final : public InstructionSelector { 48 private: 49 MachineRegisterInfo *MRI; 50 const GCNSubtarget *Subtarget; 51 52 public: 53 AMDGPUInstructionSelector(const GCNSubtarget &STI, 54 const AMDGPURegisterBankInfo &RBI, 55 const AMDGPUTargetMachine &TM); 56 57 bool select(MachineInstr &I) override; 58 static const char *getName(); 59 60 void setupMF(MachineFunction &MF, GISelKnownBits *KB, 61 CodeGenCoverage &CoverageInfo, ProfileSummaryInfo *PSI, 62 BlockFrequencyInfo *BFI) override; 63 64 private: 65 struct GEPInfo { 66 const MachineInstr &GEP; 67 SmallVector<unsigned, 2> SgprParts; 68 SmallVector<unsigned, 2> VgprParts; 69 int64_t Imm; 70 GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { } 71 }; 72 73 bool isSGPR(Register Reg) const; 74 75 bool isInstrUniform(const MachineInstr &MI) const; 76 bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const; 77 78 const RegisterBank *getArtifactRegBank( 79 Register Reg, const MachineRegisterInfo &MRI, 80 const TargetRegisterInfo &TRI) const; 81 82 /// tblgen-erated 'select' implementation. 83 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const; 84 85 MachineOperand getSubOperand64(MachineOperand &MO, 86 const TargetRegisterClass &SubRC, 87 unsigned SubIdx) const; 88 89 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const; 90 bool selectCOPY(MachineInstr &I) const; 91 bool selectPHI(MachineInstr &I) const; 92 bool selectG_TRUNC(MachineInstr &I) const; 93 bool selectG_SZA_EXT(MachineInstr &I) const; 94 bool selectG_CONSTANT(MachineInstr &I) const; 95 bool selectG_FNEG(MachineInstr &I) const; 96 bool selectG_FABS(MachineInstr &I) const; 97 bool selectG_AND_OR_XOR(MachineInstr &I) const; 98 bool selectG_ADD_SUB(MachineInstr &I) const; 99 bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const; 100 bool selectG_EXTRACT(MachineInstr &I) const; 101 bool selectG_MERGE_VALUES(MachineInstr &I) const; 102 bool selectG_UNMERGE_VALUES(MachineInstr &I) const; 103 bool selectG_BUILD_VECTOR_TRUNC(MachineInstr &I) const; 104 bool selectG_PTR_ADD(MachineInstr &I) const; 105 bool selectG_IMPLICIT_DEF(MachineInstr &I) const; 106 bool selectG_INSERT(MachineInstr &I) const; 107 bool selectG_SBFX_UBFX(MachineInstr &I) const; 108 109 bool selectInterpP1F16(MachineInstr &MI) const; 110 bool selectWritelane(MachineInstr &MI) const; 111 bool selectDivScale(MachineInstr &MI) const; 112 bool selectIntrinsicIcmp(MachineInstr &MI) const; 113 bool selectBallot(MachineInstr &I) const; 114 bool selectRelocConstant(MachineInstr &I) const; 115 bool selectGroupStaticSize(MachineInstr &I) const; 116 bool selectReturnAddress(MachineInstr &I) const; 117 bool selectG_INTRINSIC(MachineInstr &I) const; 118 119 bool selectEndCfIntrinsic(MachineInstr &MI) const; 120 bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const; 121 bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const; 122 bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const; 123 bool selectSBarrier(MachineInstr &MI) const; 124 125 bool selectImageIntrinsic(MachineInstr &MI, 126 const AMDGPU::ImageDimIntrinsicInfo *Intr) const; 127 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const; 128 int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const; 129 bool selectG_ICMP(MachineInstr &I) const; 130 bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const; 131 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI, 132 SmallVectorImpl<GEPInfo> &AddrInfo) const; 133 134 void initM0(MachineInstr &I) const; 135 bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const; 136 bool selectG_AMDGPU_ATOMIC_CMPXCHG(MachineInstr &I) const; 137 bool selectG_SELECT(MachineInstr &I) const; 138 bool selectG_BRCOND(MachineInstr &I) const; 139 bool selectG_GLOBAL_VALUE(MachineInstr &I) const; 140 bool selectG_PTRMASK(MachineInstr &I) const; 141 bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const; 142 bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const; 143 bool selectG_SHUFFLE_VECTOR(MachineInstr &I) const; 144 bool selectAMDGPU_BUFFER_ATOMIC_FADD(MachineInstr &I) const; 145 bool selectGlobalAtomicFadd(MachineInstr &I, MachineOperand &AddrOp, 146 MachineOperand &DataOp) const; 147 bool selectBVHIntrinsic(MachineInstr &I) const; 148 bool selectWaveAddress(MachineInstr &I) const; 149 150 std::pair<Register, unsigned> selectVOP3ModsImpl(MachineOperand &Root, 151 bool AllowAbs = true) const; 152 153 InstructionSelector::ComplexRendererFns 154 selectVCSRC(MachineOperand &Root) const; 155 156 InstructionSelector::ComplexRendererFns 157 selectVSRC0(MachineOperand &Root) const; 158 159 InstructionSelector::ComplexRendererFns 160 selectVOP3Mods0(MachineOperand &Root) const; 161 InstructionSelector::ComplexRendererFns 162 selectVOP3BMods0(MachineOperand &Root) const; 163 InstructionSelector::ComplexRendererFns 164 selectVOP3OMods(MachineOperand &Root) const; 165 InstructionSelector::ComplexRendererFns 166 selectVOP3Mods(MachineOperand &Root) const; 167 InstructionSelector::ComplexRendererFns 168 selectVOP3BMods(MachineOperand &Root) const; 169 170 ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const; 171 172 InstructionSelector::ComplexRendererFns 173 selectVOP3Mods_nnan(MachineOperand &Root) const; 174 175 std::pair<Register, unsigned> 176 selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI) const; 177 178 InstructionSelector::ComplexRendererFns 179 selectVOP3PMods(MachineOperand &Root) const; 180 181 InstructionSelector::ComplexRendererFns 182 selectVOP3OpSelMods(MachineOperand &Root) const; 183 184 InstructionSelector::ComplexRendererFns 185 selectSmrdImm(MachineOperand &Root) const; 186 InstructionSelector::ComplexRendererFns 187 selectSmrdImm32(MachineOperand &Root) const; 188 InstructionSelector::ComplexRendererFns 189 selectSmrdSgpr(MachineOperand &Root) const; 190 191 std::pair<Register, int> selectFlatOffsetImpl(MachineOperand &Root, 192 uint64_t FlatVariant) const; 193 194 InstructionSelector::ComplexRendererFns 195 selectFlatOffset(MachineOperand &Root) const; 196 InstructionSelector::ComplexRendererFns 197 selectGlobalOffset(MachineOperand &Root) const; 198 InstructionSelector::ComplexRendererFns 199 selectScratchOffset(MachineOperand &Root) const; 200 201 InstructionSelector::ComplexRendererFns 202 selectGlobalSAddr(MachineOperand &Root) const; 203 204 InstructionSelector::ComplexRendererFns 205 selectScratchSAddr(MachineOperand &Root) const; 206 207 InstructionSelector::ComplexRendererFns 208 selectMUBUFScratchOffen(MachineOperand &Root) const; 209 InstructionSelector::ComplexRendererFns 210 selectMUBUFScratchOffset(MachineOperand &Root) const; 211 212 bool isDSOffsetLegal(Register Base, int64_t Offset) const; 213 bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1, 214 unsigned Size) const; 215 216 std::pair<Register, unsigned> 217 selectDS1Addr1OffsetImpl(MachineOperand &Root) const; 218 InstructionSelector::ComplexRendererFns 219 selectDS1Addr1Offset(MachineOperand &Root) const; 220 221 InstructionSelector::ComplexRendererFns 222 selectDS64Bit4ByteAligned(MachineOperand &Root) const; 223 224 InstructionSelector::ComplexRendererFns 225 selectDS128Bit8ByteAligned(MachineOperand &Root) const; 226 227 std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root, 228 unsigned size) const; 229 InstructionSelector::ComplexRendererFns 230 selectDSReadWrite2(MachineOperand &Root, unsigned size) const; 231 232 std::pair<Register, int64_t> 233 getPtrBaseWithConstantOffset(Register Root, 234 const MachineRegisterInfo &MRI) const; 235 236 // Parse out a chain of up to two g_ptr_add instructions. 237 // g_ptr_add (n0, _) 238 // g_ptr_add (n0, (n1 = g_ptr_add n2, n3)) 239 struct MUBUFAddressData { 240 Register N0, N2, N3; 241 int64_t Offset = 0; 242 }; 243 244 bool shouldUseAddr64(MUBUFAddressData AddrData) const; 245 246 void splitIllegalMUBUFOffset(MachineIRBuilder &B, 247 Register &SOffset, int64_t &ImmOffset) const; 248 249 MUBUFAddressData parseMUBUFAddress(Register Src) const; 250 251 bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr, 252 Register &RSrcReg, Register &SOffset, 253 int64_t &Offset) const; 254 255 bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg, 256 Register &SOffset, int64_t &Offset) const; 257 258 InstructionSelector::ComplexRendererFns 259 selectMUBUFAddr64(MachineOperand &Root) const; 260 261 InstructionSelector::ComplexRendererFns 262 selectMUBUFOffset(MachineOperand &Root) const; 263 264 InstructionSelector::ComplexRendererFns 265 selectMUBUFOffsetAtomic(MachineOperand &Root) const; 266 267 InstructionSelector::ComplexRendererFns 268 selectMUBUFAddr64Atomic(MachineOperand &Root) const; 269 270 ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const; 271 ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const; 272 273 void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI, 274 int OpIdx = -1) const; 275 276 void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI, 277 int OpIdx) const; 278 279 void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI, 280 int OpIdx) const; 281 282 void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI, 283 int OpIdx) const; 284 285 void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI, 286 int OpIdx) const; 287 void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI, 288 int OpIdx) const; 289 void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI, 290 int OpIdx) const; 291 void renderSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI, 292 int OpIdx) const; 293 294 void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI, 295 int OpIdx) const; 296 297 bool isInlineImmediate16(int64_t Imm) const; 298 bool isInlineImmediate32(int64_t Imm) const; 299 bool isInlineImmediate64(int64_t Imm) const; 300 bool isInlineImmediate(const APFloat &Imm) const; 301 302 // Returns true if TargetOpcode::G_AND MachineInstr `MI`'s masking of the 303 // shift amount operand's `ShAmtBits` bits is unneeded. 304 bool isUnneededShiftMask(const MachineInstr &MI, unsigned ShAmtBits) const; 305 306 const SIInstrInfo &TII; 307 const SIRegisterInfo &TRI; 308 const AMDGPURegisterBankInfo &RBI; 309 const AMDGPUTargetMachine &TM; 310 const GCNSubtarget &STI; 311 bool EnableLateStructurizeCFG; 312 #define GET_GLOBALISEL_PREDICATES_DECL 313 #define AMDGPUSubtarget GCNSubtarget 314 #include "AMDGPUGenGlobalISel.inc" 315 #undef GET_GLOBALISEL_PREDICATES_DECL 316 #undef AMDGPUSubtarget 317 318 #define GET_GLOBALISEL_TEMPORARIES_DECL 319 #include "AMDGPUGenGlobalISel.inc" 320 #undef GET_GLOBALISEL_TEMPORARIES_DECL 321 }; 322 323 } // End llvm namespace. 324 #endif 325