xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td (revision c66ec88fed842fbaad62c30d510644ceb7bd2d71)
1//===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains DAG node definitions for the AMDGPU target.
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// AMDGPU DAG Profiles
15//===----------------------------------------------------------------------===//
16
17def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
18  SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
19]>;
20
21def AMDGPULdExpOp : SDTypeProfile<1, 2,
22  [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
23>;
24
25def AMDGPUFPClassOp : SDTypeProfile<1, 2,
26  [SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>]
27>;
28
29def AMDGPUFPPackOp : SDTypeProfile<1, 2,
30  [SDTCisFP<1>, SDTCisSameAs<1, 2>]
31>;
32
33def AMDGPUIntPackOp : SDTypeProfile<1, 2,
34  [SDTCisInt<1>, SDTCisSameAs<1, 2>]
35>;
36
37def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
38  [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
39>;
40
41// float, float, float, vcc
42def AMDGPUFmasOp : SDTypeProfile<1, 4,
43  [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>]
44>;
45
46def AMDGPUKillSDT : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
47
48def AMDGPUIfOp : SDTypeProfile<1, 2,
49  [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, OtherVT>]
50>;
51
52def AMDGPUElseOp : SDTypeProfile<1, 2,
53  [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, OtherVT>]
54>;
55
56def AMDGPULoopOp : SDTypeProfile<0, 2,
57  [SDTCisVT<0, i1>, SDTCisVT<1, OtherVT>]
58>;
59
60def AMDGPUIfBreakOp : SDTypeProfile<1, 2,
61  [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, i1>]
62>;
63
64//===----------------------------------------------------------------------===//
65// AMDGPU DAG Nodes
66//
67
68def AMDGPUif : SDNode<"AMDGPUISD::IF", AMDGPUIfOp, [SDNPHasChain]>;
69def AMDGPUelse : SDNode<"AMDGPUISD::ELSE", AMDGPUElseOp, [SDNPHasChain]>;
70def AMDGPUloop : SDNode<"AMDGPUISD::LOOP", AMDGPULoopOp, [SDNPHasChain]>;
71
72def callseq_start : SDNode<"ISD::CALLSEQ_START",
73  SDCallSeqStart<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>,
74  [SDNPHasChain, SDNPOutGlue]
75>;
76
77def callseq_end : SDNode<"ISD::CALLSEQ_END",
78 SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>,
79  [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]
80>;
81
82def AMDGPUcall : SDNode<"AMDGPUISD::CALL",
83  SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
84  [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
85  SDNPVariadic]
86>;
87
88def AMDGPUtc_return: SDNode<"AMDGPUISD::TC_RETURN",
89  SDTypeProfile<0, 3, [SDTCisPtrTy<0>]>,
90  [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]
91>;
92
93def AMDGPUtrap : SDNode<"AMDGPUISD::TRAP",
94  SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>,
95    [SDNPHasChain, SDNPVariadic, SDNPSideEffect, SDNPInGlue]
96>;
97
98def AMDGPUconstdata_ptr : SDNode<
99  "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 1, [SDTCisVT<0, iPTR>,
100                                                     SDTCisVT<0, iPTR>]>
101>;
102
103// This argument to this node is a dword address.
104def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
105
106// Force dependencies for vector trunc stores
107def R600dummy_chain : SDNode<"AMDGPUISD::DUMMY_CHAIN", SDTNone, [SDNPHasChain]>;
108
109def AMDGPUcos_impl : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;
110def AMDGPUsin_impl : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;
111// out = a - floor(a)
112def AMDGPUfract_impl : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
113
114// out = 1.0 / a
115def AMDGPUrcp_impl : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
116
117// out = 1.0 / sqrt(a)
118def AMDGPUrsq_impl : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
119
120def AMDGPUrcp_legacy_impl : SDNode<"AMDGPUISD::RCP_LEGACY", SDTFPUnaryOp>;
121
122def AMDGPUrcp_iflag : SDNode<"AMDGPUISD::RCP_IFLAG", SDTFPUnaryOp>;
123
124// out = 1.0 / sqrt(a) result clamped to +/- max_float.
125def AMDGPUrsq_clamp_impl : SDNode<"AMDGPUISD::RSQ_CLAMP", SDTFPUnaryOp>;
126
127def AMDGPUldexp_impl : SDNode<"AMDGPUISD::LDEXP", AMDGPULdExpOp>;
128
129def AMDGPUpkrtz_f16_f32_impl : SDNode<"AMDGPUISD::CVT_PKRTZ_F16_F32", AMDGPUFPPackOp>;
130def AMDGPUpknorm_i16_f32_impl : SDNode<"AMDGPUISD::CVT_PKNORM_I16_F32", AMDGPUFPPackOp>;
131def AMDGPUpknorm_u16_f32_impl : SDNode<"AMDGPUISD::CVT_PKNORM_U16_F32", AMDGPUFPPackOp>;
132def AMDGPUpk_i16_i32_impl : SDNode<"AMDGPUISD::CVT_PK_I16_I32", AMDGPUIntPackOp>;
133def AMDGPUpk_u16_u32_impl : SDNode<"AMDGPUISD::CVT_PK_U16_U32", AMDGPUIntPackOp>;
134def AMDGPUfp_to_f16 : SDNode<"AMDGPUISD::FP_TO_FP16" , SDTFPToIntOp>;
135def AMDGPUfp16_zext : SDNode<"AMDGPUISD::FP16_ZEXT" , SDTFPToIntOp>;
136
137
138def AMDGPUfp_class_impl : SDNode<"AMDGPUISD::FP_CLASS", AMDGPUFPClassOp>;
139
140// out = max(a, b) a and b are floats, where a nan comparison fails.
141// This is not commutative because this gives the second operand:
142//   x < nan ? x : nan -> nan
143//   nan < x ? nan : x -> x
144def AMDGPUfmax_legacy : SDNode<"AMDGPUISD::FMAX_LEGACY", SDTFPBinOp,
145  []
146>;
147
148def AMDGPUfmul_legacy_impl : SDNode<"AMDGPUISD::FMUL_LEGACY", SDTFPBinOp,
149  [SDNPCommutative, SDNPAssociative]
150>;
151
152// out = min(a, b) a and b are floats, where a nan comparison fails.
153def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp,
154  []
155>;
156
157// FIXME: TableGen doesn't like commutative instructions with more
158// than 2 operands.
159// out = max(a, b, c) a, b and c are floats
160def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp,
161  [/*SDNPCommutative, SDNPAssociative*/]
162>;
163
164// out = max(a, b, c) a, b, and c are signed ints
165def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp,
166  [/*SDNPCommutative, SDNPAssociative*/]
167>;
168
169// out = max(a, b, c) a, b and c are unsigned ints
170def AMDGPUumax3 : SDNode<"AMDGPUISD::UMAX3", AMDGPUDTIntTernaryOp,
171  [/*SDNPCommutative, SDNPAssociative*/]
172>;
173
174// out = min(a, b, c) a, b and c are floats
175def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp,
176  [/*SDNPCommutative, SDNPAssociative*/]
177>;
178
179// out = min(a, b, c) a, b and c are signed ints
180def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp,
181  [/*SDNPCommutative, SDNPAssociative*/]
182>;
183
184// out = min(a, b) a and b are unsigned ints
185def AMDGPUumin3 : SDNode<"AMDGPUISD::UMIN3", AMDGPUDTIntTernaryOp,
186  [/*SDNPCommutative, SDNPAssociative*/]
187>;
188
189// out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
190def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>;
191
192// out = (src1 > src0) ? 1 : 0
193def AMDGPUborrow : SDNode<"AMDGPUISD::BORROW", SDTIntBinOp, []>;
194
195def AMDGPUSetCCOp : SDTypeProfile<1, 3, [        // setcc
196  SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
197]>;
198
199def AMDGPUsetcc : SDNode<"AMDGPUISD::SETCC", AMDGPUSetCCOp>;
200
201def AMDGPUfma : SDNode<"AMDGPUISD::FMA_W_CHAIN", SDTFPTernaryOp, [
202   SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
203
204def AMDGPUmul : SDNode<"AMDGPUISD::FMUL_W_CHAIN", SDTFPBinOp, [
205  SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
206
207def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
208  SDTIntToFPOp, []>;
209def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
210  SDTIntToFPOp, []>;
211def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",
212  SDTIntToFPOp, []>;
213def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",
214  SDTIntToFPOp, []>;
215
216
217// urecip - This operation is a helper for integer division, it returns the
218// result of 1 / a as a fractional unsigned integer.
219// out = (2^32 / a) + e
220// e is rounding error
221def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
222
223// Special case divide preop and flags.
224def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;
225
226//  Special case divide FMA with scale and flags (src0 = Quotient,
227//  src1 = Denominator, src2 = Numerator).
228def AMDGPUdiv_fmas_impl : SDNode<"AMDGPUISD::DIV_FMAS", AMDGPUFmasOp,
229                            [SDNPOptInGlue]>;
230
231// Single or double precision division fixup.
232// Special case divide fixup and flags(src0 = Quotient, src1 =
233// Denominator, src2 = Numerator).
234def AMDGPUdiv_fixup_impl : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;
235
236def AMDGPUfmad_ftz_impl : SDNode<"AMDGPUISD::FMAD_FTZ", SDTFPTernaryOp>;
237
238def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
239                          SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
240                          [SDNPHasChain, SDNPMayLoad]>;
241
242def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
243                           SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
244                           [SDNPHasChain, SDNPMayStore]>;
245
246// MSKOR instructions are atomic memory instructions used mainly for storing
247// 8-bit and 16-bit values.  The definition is:
248//
249// MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
250//
251// src0: vec4(src, 0, 0, mask)
252// src1: dst - rat offset (aka pointer) in dwords
253def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
254                        SDTypeProfile<0, 2, []>,
255                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
256
257def AMDGPUatomic_cmp_swap : SDNode<"AMDGPUISD::ATOMIC_CMP_SWAP",
258                            SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisVec<2>]>,
259                            [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
260                             SDNPMemOperand]>;
261
262def AMDGPUround : SDNode<"ISD::FROUND",
263                         SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
264
265def AMDGPUbfe_u32_impl : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
266def AMDGPUbfe_i32_impl : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
267def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
268def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
269
270def AMDGPUffbh_u32_impl : SDNode<"AMDGPUISD::FFBH_U32", SDTIntBitCountUnaryOp>;
271def AMDGPUffbh_i32_impl : SDNode<"AMDGPUISD::FFBH_I32", SDTIntBitCountUnaryOp>;
272
273def AMDGPUffbl_b32_impl : SDNode<"AMDGPUISD::FFBL_B32", SDTIntBitCountUnaryOp>;
274
275// Signed and unsigned 24-bit multiply. The highest 8-bits are ignore
276// when performing the multiply. The result is a 32-bit value.
277def AMDGPUmul_u24_impl : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
278  [SDNPCommutative, SDNPAssociative]
279>;
280def AMDGPUmul_i24_impl : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
281  [SDNPCommutative, SDNPAssociative]
282>;
283
284def AMDGPUmulhi_u24 : SDNode<"AMDGPUISD::MULHI_U24", SDTIntBinOp,
285  [SDNPCommutative, SDNPAssociative]
286>;
287def AMDGPUmulhi_i24 : SDNode<"AMDGPUISD::MULHI_I24", SDTIntBinOp,
288  [SDNPCommutative, SDNPAssociative]
289>;
290
291def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
292  []
293>;
294def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
295  []
296>;
297
298def AMDGPUsmed3 : SDNode<"AMDGPUISD::SMED3", AMDGPUDTIntTernaryOp,
299  []
300>;
301
302def AMDGPUumed3 : SDNode<"AMDGPUISD::UMED3", AMDGPUDTIntTernaryOp,
303  []
304>;
305
306def AMDGPUfmed3_impl : SDNode<"AMDGPUISD::FMED3", SDTFPTernaryOp, []>;
307
308def AMDGPUfdot2_impl : SDNode<"AMDGPUISD::FDOT2",
309                  SDTypeProfile<1, 4, [SDTCisSameAs<0, 3>, SDTCisSameAs<1, 2>,
310                                       SDTCisFP<0>, SDTCisVec<1>,
311                                       SDTCisInt<4>]>,
312                  []>;
313
314def AMDGPUperm : SDNode<"AMDGPUISD::PERM", AMDGPUDTIntTernaryOp, []>;
315
316// SI+ export
317def AMDGPUExportOp : SDTypeProfile<0, 8, [
318  SDTCisInt<0>,       // i8 tgt
319  SDTCisInt<1>,       // i8 en
320                      // i32 or f32 src0
321  SDTCisSameAs<3, 2>, // f32 src1
322  SDTCisSameAs<4, 2>, // f32 src2
323  SDTCisSameAs<5, 2>, // f32 src3
324  SDTCisInt<6>,       // i1 compr
325  // skip done
326  SDTCisInt<1>        // i1 vm
327
328]>;
329
330
331def R600ExportOp : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
332
333def R600_EXPORT: SDNode<"AMDGPUISD::R600_EXPORT", R600ExportOp,
334  [SDNPHasChain, SDNPSideEffect]>;
335
336//===----------------------------------------------------------------------===//
337// Flow Control Profile Types
338//===----------------------------------------------------------------------===//
339// Branch instruction where second and third are basic blocks
340def SDTIL_BRCond : SDTypeProfile<0, 2, [
341    SDTCisVT<0, OtherVT>
342    ]>;
343
344//===----------------------------------------------------------------------===//
345// Flow Control DAG Nodes
346//===----------------------------------------------------------------------===//
347def IL_brcond      : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
348
349//===----------------------------------------------------------------------===//
350// Call/Return DAG Nodes
351//===----------------------------------------------------------------------===//
352def AMDGPUendpgm : SDNode<"AMDGPUISD::ENDPGM", SDTNone,
353    [SDNPHasChain, SDNPOptInGlue]>;
354
355def AMDGPUreturn_to_epilog : SDNode<"AMDGPUISD::RETURN_TO_EPILOG", SDTNone,
356    [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
357
358def AMDGPUret_flag : SDNode<"AMDGPUISD::RET_FLAG", SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
359  [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]
360>;
361
362
363//===----------------------------------------------------------------------===//
364// Intrinsic/Custom node compatibility PatFrags
365//===----------------------------------------------------------------------===//
366
367def AMDGPUrcp : PatFrags<(ops node:$src), [(int_amdgcn_rcp node:$src),
368                                           (AMDGPUrcp_impl node:$src)]>;
369def AMDGPUrcp_legacy : PatFrags<(ops node:$src), [(int_amdgcn_rcp_legacy node:$src),
370                                                  (AMDGPUrcp_legacy_impl node:$src)]>;
371
372def AMDGPUrsq : PatFrags<(ops node:$src), [(int_amdgcn_rsq node:$src),
373                                           (AMDGPUrsq_impl node:$src)]>;
374
375def AMDGPUrsq_clamp : PatFrags<(ops node:$src), [(int_amdgcn_rsq_clamp node:$src),
376                                                 (AMDGPUrsq_clamp_impl node:$src)]>;
377
378def AMDGPUsin : PatFrags<(ops node:$src), [(int_amdgcn_sin node:$src),
379                                           (AMDGPUsin_impl node:$src)]>;
380def AMDGPUcos : PatFrags<(ops node:$src), [(int_amdgcn_cos node:$src),
381                                           (AMDGPUcos_impl node:$src)]>;
382def AMDGPUfract : PatFrags<(ops node:$src), [(int_amdgcn_fract node:$src),
383                                             (AMDGPUfract_impl node:$src)]>;
384
385def AMDGPUldexp : PatFrags<(ops node:$src0, node:$src1),
386  [(int_amdgcn_ldexp node:$src0, node:$src1),
387   (AMDGPUldexp_impl node:$src0, node:$src1)]>;
388
389def AMDGPUfp_class : PatFrags<(ops node:$src0, node:$src1),
390  [(int_amdgcn_class node:$src0, node:$src1),
391  (AMDGPUfp_class_impl node:$src0, node:$src1)]>;
392
393def AMDGPUfmed3 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
394  [(int_amdgcn_fmed3 node:$src0, node:$src1, node:$src2),
395   (AMDGPUfmed3_impl node:$src0, node:$src1, node:$src2)]>;
396
397def AMDGPUdiv_fixup : PatFrags<(ops node:$src0, node:$src1, node:$src2),
398  [(int_amdgcn_div_fixup node:$src0, node:$src1, node:$src2),
399   (AMDGPUdiv_fixup_impl node:$src0, node:$src1, node:$src2)]>;
400
401def AMDGPUffbh_i32 : PatFrags<(ops node:$src),
402  [(int_amdgcn_sffbh node:$src),
403   (AMDGPUffbh_i32_impl node:$src)]>;
404
405def AMDGPUffbh_u32 : PatFrags<(ops node:$src),
406  [(ctlz_zero_undef node:$src),
407   (AMDGPUffbh_u32_impl node:$src)]>;
408
409def AMDGPUffbl_b32 : PatFrags<(ops node:$src),
410  [(cttz_zero_undef node:$src),
411   (AMDGPUffbl_b32_impl node:$src)]>;
412
413def AMDGPUpkrtz_f16_f32 : PatFrags<(ops node:$src0, node:$src1),
414  [(int_amdgcn_cvt_pkrtz node:$src0, node:$src1),
415  (AMDGPUpkrtz_f16_f32_impl node:$src0, node:$src1)]>;
416
417def AMDGPUpknorm_i16_f32 : PatFrags<(ops node:$src0, node:$src1),
418  [(int_amdgcn_cvt_pknorm_i16 node:$src0, node:$src1),
419  (AMDGPUpknorm_i16_f32_impl node:$src0, node:$src1)]>;
420
421def AMDGPUpknorm_u16_f32 : PatFrags<(ops node:$src0, node:$src1),
422  [(int_amdgcn_cvt_pknorm_u16 node:$src0, node:$src1),
423  (AMDGPUpknorm_u16_f32_impl node:$src0, node:$src1)]>;
424
425def AMDGPUpk_i16_i32 : PatFrags<(ops node:$src0, node:$src1),
426  [(int_amdgcn_cvt_pk_i16 node:$src0, node:$src1),
427  (AMDGPUpk_i16_i32_impl node:$src0, node:$src1)]>;
428
429def AMDGPUpk_u16_u32 : PatFrags<(ops node:$src0, node:$src1),
430  [(int_amdgcn_cvt_pk_u16 node:$src0, node:$src1),
431  (AMDGPUpk_u16_u32_impl node:$src0, node:$src1)]>;
432
433def AMDGPUfmad_ftz : PatFrags<(ops node:$src0, node:$src1, node:$src2),
434  [(int_amdgcn_fmad_ftz node:$src0, node:$src1, node:$src2),
435   (AMDGPUfmad_ftz_impl node:$src0, node:$src1, node:$src2)]>;
436
437def AMDGPUmul_u24 : PatFrags<(ops node:$src0, node:$src1),
438  [(int_amdgcn_mul_u24 node:$src0, node:$src1),
439   (AMDGPUmul_u24_impl node:$src0, node:$src1)]>;
440
441def AMDGPUmul_i24 : PatFrags<(ops node:$src0, node:$src1),
442  [(int_amdgcn_mul_i24 node:$src0, node:$src1),
443   (AMDGPUmul_i24_impl node:$src0, node:$src1)]>;
444
445def AMDGPUbfe_i32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
446  [(int_amdgcn_sbfe node:$src0, node:$src1, node:$src2),
447   (AMDGPUbfe_i32_impl node:$src0, node:$src1, node:$src2)]>;
448
449def AMDGPUbfe_u32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
450  [(int_amdgcn_ubfe node:$src0, node:$src1, node:$src2),
451   (AMDGPUbfe_u32_impl node:$src0, node:$src1, node:$src2)]>;
452
453def AMDGPUfmul_legacy : PatFrags<(ops node:$src0, node:$src1),
454  [(int_amdgcn_fmul_legacy node:$src0, node:$src1),
455   (AMDGPUfmul_legacy_impl node:$src0, node:$src1)]>;
456
457def AMDGPUfdot2 : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$clamp),
458  [(int_amdgcn_fdot2 node:$src0, node:$src1, node:$src2, node:$clamp),
459   (AMDGPUfdot2_impl node:$src0, node:$src1, node:$src2, node:$clamp)]>;
460
461def AMDGPUdiv_fmas : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$vcc),
462  [(int_amdgcn_div_fmas node:$src0, node:$src1, node:$src2, node:$vcc),
463   (AMDGPUdiv_fmas_impl node:$src0, node:$src1, node:$src2, node:$vcc)]>;
464