10b57cec5SDimitry Andric //===-- AMDGPUInstrInfo.cpp - Base class for AMD GPU InstrInfo ------------===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric /// \file 100b57cec5SDimitry Andric /// \brief Implementation of the TargetInstrInfo class that is common to all 110b57cec5SDimitry Andric /// AMD GPUs. 120b57cec5SDimitry Andric // 130b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 140b57cec5SDimitry Andric 150b57cec5SDimitry Andric #include "AMDGPUInstrInfo.h" 16e8d8bef9SDimitry Andric #include "AMDGPU.h" 17*5f757f3fSDimitry Andric #include "llvm/CodeGen/MachineInstr.h" 18e8d8bef9SDimitry Andric #include "llvm/CodeGen/MachineMemOperand.h" 19e8d8bef9SDimitry Andric #include "llvm/IR/Constants.h" 20e8d8bef9SDimitry Andric #include "llvm/IR/Instruction.h" 21e8d8bef9SDimitry Andric #include "llvm/IR/Value.h" 220b57cec5SDimitry Andric 230b57cec5SDimitry Andric using namespace llvm; 240b57cec5SDimitry Andric 250b57cec5SDimitry Andric // Pin the vtable to this file. 260b57cec5SDimitry Andric //void AMDGPUInstrInfo::anchor() {} 270b57cec5SDimitry Andric 280b57cec5SDimitry Andric AMDGPUInstrInfo::AMDGPUInstrInfo(const GCNSubtarget &ST) { } 290b57cec5SDimitry Andric 30*5f757f3fSDimitry Andric Intrinsic::ID AMDGPU::getIntrinsicID(const MachineInstr &I) { 31*5f757f3fSDimitry Andric return I.getOperand(I.getNumExplicitDefs()).getIntrinsicID(); 32*5f757f3fSDimitry Andric } 330b57cec5SDimitry Andric 340b57cec5SDimitry Andric // TODO: Should largely merge with AMDGPUTTIImpl::isSourceOfDivergence. 350b57cec5SDimitry Andric bool AMDGPUInstrInfo::isUniformMMO(const MachineMemOperand *MMO) { 360b57cec5SDimitry Andric const Value *Ptr = MMO->getValue(); 370b57cec5SDimitry Andric // UndefValue means this is a load of a kernel input. These are uniform. 380b57cec5SDimitry Andric // Sometimes LDS instructions have constant pointers. 390b57cec5SDimitry Andric // If Ptr is null, then that means this mem operand contains a 400b57cec5SDimitry Andric // PseudoSourceValue like GOT. 410b57cec5SDimitry Andric if (!Ptr || isa<UndefValue>(Ptr) || 420b57cec5SDimitry Andric isa<Constant>(Ptr) || isa<GlobalValue>(Ptr)) 430b57cec5SDimitry Andric return true; 440b57cec5SDimitry Andric 450b57cec5SDimitry Andric if (MMO->getAddrSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) 460b57cec5SDimitry Andric return true; 470b57cec5SDimitry Andric 480b57cec5SDimitry Andric if (const Argument *Arg = dyn_cast<Argument>(Ptr)) 490b57cec5SDimitry Andric return AMDGPU::isArgPassedInSGPR(Arg); 500b57cec5SDimitry Andric 510b57cec5SDimitry Andric const Instruction *I = dyn_cast<Instruction>(Ptr); 520b57cec5SDimitry Andric return I && I->getMetadata("amdgpu.uniform"); 530b57cec5SDimitry Andric } 54