1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// Interface definition of the TargetLowering class that is common 11 /// to all AMD GPUs. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H 16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H 17 18 #include "llvm/CodeGen/CallingConvLower.h" 19 #include "llvm/CodeGen/TargetLowering.h" 20 21 namespace llvm { 22 23 class AMDGPUMachineFunction; 24 class AMDGPUSubtarget; 25 struct ArgDescriptor; 26 27 class AMDGPUTargetLowering : public TargetLowering { 28 private: 29 const AMDGPUSubtarget *Subtarget; 30 31 /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been 32 /// legalized from a smaller type VT. Need to match pre-legalized type because 33 /// the generic legalization inserts the add/sub between the select and 34 /// compare. 35 SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const; 36 37 public: 38 /// \returns The minimum number of bits needed to store the value of \Op as an 39 /// unsigned integer. Truncating to this size and then zero-extending to the 40 /// original size will not change the value. 41 static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG); 42 43 /// \returns The minimum number of bits needed to store the value of \Op as a 44 /// signed integer. Truncating to this size and then sign-extending to the 45 /// original size will not change the value. 46 static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG); 47 48 protected: 49 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 50 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; 51 /// Split a vector store into multiple scalar stores. 52 /// \returns The resulting chain. 53 54 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const; 55 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const; 56 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const; 57 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const; 58 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const; 59 60 SDValue LowerFROUNDEVEN(SDValue Op, SelectionDAG &DAG) const; 61 SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const; 62 SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const; 63 SDValue LowerFLOG(SDValue Op, SelectionDAG &DAG, 64 double Log2BaseInverted) const; 65 SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const; 66 67 SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const; 68 69 SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const; 70 SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const; 71 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 72 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 73 74 SDValue LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG, bool Signed) const; 75 SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const; 76 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const; 77 78 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; 79 80 protected: 81 bool shouldCombineMemoryType(EVT VT) const; 82 SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const; 83 SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const; 84 SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const; 85 SDValue performIntrinsicWOChainCombine(SDNode *N, DAGCombinerInfo &DCI) const; 86 87 SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL, 88 unsigned Opc, SDValue LHS, 89 uint32_t ValLo, uint32_t ValHi) const; 90 SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const; 91 SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const; 92 SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const; 93 SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const; 94 SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const; 95 SDValue performMulLoHiCombine(SDNode *N, DAGCombinerInfo &DCI) const; 96 SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const; 97 SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const; 98 SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS, 99 SDValue RHS, DAGCombinerInfo &DCI) const; 100 SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const; 101 102 bool isConstantCostlierToNegate(SDValue N) const; 103 SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const; 104 SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const; 105 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const; 106 107 static EVT getEquivalentMemType(LLVMContext &Context, EVT VT); 108 109 virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 110 SelectionDAG &DAG) const; 111 112 /// Return 64-bit value Op as two 32-bit integers. 113 std::pair<SDValue, SDValue> split64BitValue(SDValue Op, 114 SelectionDAG &DAG) const; 115 SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const; 116 SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const; 117 118 /// Split a vector type into two parts. The first part is a power of two 119 /// vector. The second part is whatever is left over, and is a scalar if it 120 /// would otherwise be a 1-vector. 121 std::pair<EVT, EVT> getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const; 122 123 /// Split a vector value into two parts of types LoVT and HiVT. HiVT could be 124 /// scalar. 125 std::pair<SDValue, SDValue> splitVector(const SDValue &N, const SDLoc &DL, 126 const EVT &LoVT, const EVT &HighVT, 127 SelectionDAG &DAG) const; 128 129 /// Split a vector load into 2 loads of half the vector. 130 SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const; 131 132 /// Widen a suitably aligned v3 load. For all other cases, split the input 133 /// vector load. 134 SDValue WidenOrSplitVectorLoad(SDValue Op, SelectionDAG &DAG) const; 135 136 /// Split a vector store into 2 stores of half the vector. 137 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const; 138 139 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 140 SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const; 141 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const; 142 SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const; 143 void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, 144 SmallVectorImpl<SDValue> &Results) const; 145 146 void analyzeFormalArgumentsCompute( 147 CCState &State, 148 const SmallVectorImpl<ISD::InputArg> &Ins) const; 149 150 public: 151 AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI); 152 153 bool mayIgnoreSignedZero(SDValue Op) const; 154 155 static inline SDValue stripBitcast(SDValue Val) { 156 return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val; 157 } 158 159 static bool allUsesHaveSourceMods(const SDNode *N, 160 unsigned CostThreshold = 4); 161 bool isFAbsFree(EVT VT) const override; 162 bool isFNegFree(EVT VT) const override; 163 bool isTruncateFree(EVT Src, EVT Dest) const override; 164 bool isTruncateFree(Type *Src, Type *Dest) const override; 165 166 bool isZExtFree(Type *Src, Type *Dest) const override; 167 bool isZExtFree(EVT Src, EVT Dest) const override; 168 bool isZExtFree(SDValue Val, EVT VT2) const override; 169 170 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, 171 bool LegalOperations, bool ForCodeSize, 172 NegatibleCost &Cost, 173 unsigned Depth) const override; 174 175 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override; 176 177 bool isDesirableToCommuteWithShift(const SDNode *N, 178 CombineLevel Level) const override; 179 180 EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, 181 ISD::NodeType ExtendKind) const override; 182 183 MVT getVectorIdxTy(const DataLayout &) const override; 184 bool isSelectSupported(SelectSupportKind) const override; 185 186 bool isFPImmLegal(const APFloat &Imm, EVT VT, 187 bool ForCodeSize) const override; 188 bool ShouldShrinkFPConstant(EVT VT) const override; 189 bool shouldReduceLoadWidth(SDNode *Load, 190 ISD::LoadExtType ExtType, 191 EVT ExtVT) const override; 192 193 bool isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG, 194 const MachineMemOperand &MMO) const final; 195 196 bool storeOfVectorConstantIsCheap(EVT MemVT, 197 unsigned NumElem, 198 unsigned AS) const override; 199 bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override; 200 bool isCheapToSpeculateCttz(Type *Ty) const override; 201 bool isCheapToSpeculateCtlz(Type *Ty) const override; 202 203 bool isSDNodeAlwaysUniform(const SDNode *N) const override; 204 static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg); 205 static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg); 206 207 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 208 const SmallVectorImpl<ISD::OutputArg> &Outs, 209 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 210 SelectionDAG &DAG) const override; 211 212 SDValue addTokenForArgument(SDValue Chain, 213 SelectionDAG &DAG, 214 MachineFrameInfo &MFI, 215 int ClobberedFI) const; 216 217 SDValue lowerUnhandledCall(CallLoweringInfo &CLI, 218 SmallVectorImpl<SDValue> &InVals, 219 StringRef Reason) const; 220 SDValue LowerCall(CallLoweringInfo &CLI, 221 SmallVectorImpl<SDValue> &InVals) const override; 222 223 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, 224 SelectionDAG &DAG) const; 225 226 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 227 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 228 void ReplaceNodeResults(SDNode * N, 229 SmallVectorImpl<SDValue> &Results, 230 SelectionDAG &DAG) const override; 231 232 SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS, 233 SDValue RHS, SDValue True, SDValue False, 234 SDValue CC, DAGCombinerInfo &DCI) const; 235 236 const char* getTargetNodeName(unsigned Opcode) const override; 237 238 // FIXME: Turn off MergeConsecutiveStores() before Instruction Selection for 239 // AMDGPU. Commit r319036, 240 // (https://github.com/llvm/llvm-project/commit/db77e57ea86d941a4262ef60261692f4cb6893e6) 241 // turned on MergeConsecutiveStores() before Instruction Selection for all 242 // targets. Enough AMDGPU compiles go into an infinite loop ( 243 // MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges; 244 // MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off for 245 // now. 246 bool mergeStoresAfterLegalization(EVT) const override { return false; } 247 248 bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override { 249 return true; 250 } 251 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 252 int &RefinementSteps, bool &UseOneConstNR, 253 bool Reciprocal) const override; 254 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 255 int &RefinementSteps) const override; 256 257 virtual SDNode *PostISelFolding(MachineSDNode *N, 258 SelectionDAG &DAG) const = 0; 259 260 /// Determine which of the bits specified in \p Mask are known to be 261 /// either zero or one and return them in the \p KnownZero and \p KnownOne 262 /// bitsets. 263 void computeKnownBitsForTargetNode(const SDValue Op, 264 KnownBits &Known, 265 const APInt &DemandedElts, 266 const SelectionDAG &DAG, 267 unsigned Depth = 0) const override; 268 269 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, 270 const SelectionDAG &DAG, 271 unsigned Depth = 0) const override; 272 273 unsigned computeNumSignBitsForTargetInstr(GISelKnownBits &Analysis, 274 Register R, 275 const APInt &DemandedElts, 276 const MachineRegisterInfo &MRI, 277 unsigned Depth = 0) const override; 278 279 bool isKnownNeverNaNForTargetNode(SDValue Op, 280 const SelectionDAG &DAG, 281 bool SNaN = false, 282 unsigned Depth = 0) const override; 283 284 /// Helper function that adds Reg to the LiveIn list of the DAG's 285 /// MachineFunction. 286 /// 287 /// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise 288 /// a copy from the register. 289 SDValue CreateLiveInRegister(SelectionDAG &DAG, 290 const TargetRegisterClass *RC, 291 Register Reg, EVT VT, 292 const SDLoc &SL, 293 bool RawReg = false) const; 294 SDValue CreateLiveInRegister(SelectionDAG &DAG, 295 const TargetRegisterClass *RC, 296 Register Reg, EVT VT) const { 297 return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode())); 298 } 299 300 // Returns the raw live in register rather than a copy from it. 301 SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG, 302 const TargetRegisterClass *RC, 303 Register Reg, EVT VT) const { 304 return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()), true); 305 } 306 307 /// Similar to CreateLiveInRegister, except value maybe loaded from a stack 308 /// slot rather than passed in a register. 309 SDValue loadStackInputValue(SelectionDAG &DAG, 310 EVT VT, 311 const SDLoc &SL, 312 int64_t Offset) const; 313 314 SDValue storeStackInputValue(SelectionDAG &DAG, 315 const SDLoc &SL, 316 SDValue Chain, 317 SDValue ArgVal, 318 int64_t Offset) const; 319 320 SDValue loadInputValue(SelectionDAG &DAG, 321 const TargetRegisterClass *RC, 322 EVT VT, const SDLoc &SL, 323 const ArgDescriptor &Arg) const; 324 325 enum ImplicitParameter { 326 FIRST_IMPLICIT, 327 PRIVATE_BASE, 328 SHARED_BASE, 329 QUEUE_PTR, 330 }; 331 332 /// Helper function that returns the byte offset of the given 333 /// type of implicit parameter. 334 uint32_t getImplicitParameterOffset(const MachineFunction &MF, 335 const ImplicitParameter Param) const; 336 337 MVT getFenceOperandTy(const DataLayout &DL) const override { 338 return MVT::i32; 339 } 340 341 AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override; 342 343 bool isConstantUnsignedBitfieldExtractLegal(unsigned Opc, LLT Ty1, 344 LLT Ty2) const override; 345 }; 346 347 namespace AMDGPUISD { 348 349 enum NodeType : unsigned { 350 // AMDIL ISD Opcodes 351 FIRST_NUMBER = ISD::BUILTIN_OP_END, 352 UMUL, // 32bit unsigned multiplication 353 BRANCH_COND, 354 // End AMDIL ISD Opcodes 355 356 // Function call. 357 CALL, 358 TC_RETURN, 359 TRAP, 360 361 // Masked control flow nodes. 362 IF, 363 ELSE, 364 LOOP, 365 366 // A uniform kernel return that terminates the wavefront. 367 ENDPGM, 368 369 // Return to a shader part's epilog code. 370 RETURN_TO_EPILOG, 371 372 // Return with values from a non-entry function. 373 RET_FLAG, 374 375 DWORDADDR, 376 FRACT, 377 378 /// CLAMP value between 0.0 and 1.0. NaN clamped to 0, following clamp output 379 /// modifier behavior with dx10_enable. 380 CLAMP, 381 382 // This is SETCC with the full mask result which is used for a compare with a 383 // result bit per item in the wavefront. 384 SETCC, 385 SETREG, 386 387 DENORM_MODE, 388 389 // FP ops with input and output chain. 390 FMA_W_CHAIN, 391 FMUL_W_CHAIN, 392 393 // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi. 394 // Denormals handled on some parts. 395 COS_HW, 396 SIN_HW, 397 FMAX_LEGACY, 398 FMIN_LEGACY, 399 400 FMAX3, 401 SMAX3, 402 UMAX3, 403 FMIN3, 404 SMIN3, 405 UMIN3, 406 FMED3, 407 SMED3, 408 UMED3, 409 FDOT2, 410 URECIP, 411 DIV_SCALE, 412 DIV_FMAS, 413 DIV_FIXUP, 414 // For emitting ISD::FMAD when f32 denormals are enabled because mac/mad is 415 // treated as an illegal operation. 416 FMAD_FTZ, 417 418 // RCP, RSQ - For f32, 1 ULP max error, no denormal handling. 419 // For f64, max error 2^29 ULP, handles denormals. 420 RCP, 421 RSQ, 422 RCP_LEGACY, 423 RCP_IFLAG, 424 FMUL_LEGACY, 425 RSQ_CLAMP, 426 LDEXP, 427 FP_CLASS, 428 DOT4, 429 CARRY, 430 BORROW, 431 BFE_U32, // Extract range of bits with zero extension to 32-bits. 432 BFE_I32, // Extract range of bits with sign extension to 32-bits. 433 BFI, // (src0 & src1) | (~src0 & src2) 434 BFM, // Insert a range of bits into a 32-bit word. 435 FFBH_U32, // ctlz with -1 if input is zero. 436 FFBH_I32, 437 FFBL_B32, // cttz with -1 if input is zero. 438 MUL_U24, 439 MUL_I24, 440 MULHI_U24, 441 MULHI_I24, 442 MAD_U24, 443 MAD_I24, 444 MAD_U64_U32, 445 MAD_I64_I32, 446 PERM, 447 TEXTURE_FETCH, 448 R600_EXPORT, 449 CONST_ADDRESS, 450 REGISTER_LOAD, 451 REGISTER_STORE, 452 SAMPLE, 453 SAMPLEB, 454 SAMPLED, 455 SAMPLEL, 456 457 // These cvt_f32_ubyte* nodes need to remain consecutive and in order. 458 CVT_F32_UBYTE0, 459 CVT_F32_UBYTE1, 460 CVT_F32_UBYTE2, 461 CVT_F32_UBYTE3, 462 463 // Convert two float 32 numbers into a single register holding two packed f16 464 // with round to zero. 465 CVT_PKRTZ_F16_F32, 466 CVT_PKNORM_I16_F32, 467 CVT_PKNORM_U16_F32, 468 CVT_PK_I16_I32, 469 CVT_PK_U16_U32, 470 471 // Same as the standard node, except the high bits of the resulting integer 472 // are known 0. 473 FP_TO_FP16, 474 475 /// This node is for VLIW targets and it is used to represent a vector 476 /// that is stored in consecutive registers with the same channel. 477 /// For example: 478 /// |X |Y|Z|W| 479 /// T0|v.x| | | | 480 /// T1|v.y| | | | 481 /// T2|v.z| | | | 482 /// T3|v.w| | | | 483 BUILD_VERTICAL_VECTOR, 484 /// Pointer to the start of the shader's constant data. 485 CONST_DATA_PTR, 486 PC_ADD_REL_OFFSET, 487 LDS, 488 FPTRUNC_ROUND_UPWARD, 489 FPTRUNC_ROUND_DOWNWARD, 490 491 DUMMY_CHAIN, 492 FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE, 493 LOAD_D16_HI, 494 LOAD_D16_LO, 495 LOAD_D16_HI_I8, 496 LOAD_D16_HI_U8, 497 LOAD_D16_LO_I8, 498 LOAD_D16_LO_U8, 499 500 STORE_MSKOR, 501 LOAD_CONSTANT, 502 TBUFFER_STORE_FORMAT, 503 TBUFFER_STORE_FORMAT_D16, 504 TBUFFER_LOAD_FORMAT, 505 TBUFFER_LOAD_FORMAT_D16, 506 DS_ORDERED_COUNT, 507 ATOMIC_CMP_SWAP, 508 ATOMIC_INC, 509 ATOMIC_DEC, 510 ATOMIC_LOAD_FMIN, 511 ATOMIC_LOAD_FMAX, 512 BUFFER_LOAD, 513 BUFFER_LOAD_UBYTE, 514 BUFFER_LOAD_USHORT, 515 BUFFER_LOAD_BYTE, 516 BUFFER_LOAD_SHORT, 517 BUFFER_LOAD_FORMAT, 518 BUFFER_LOAD_FORMAT_TFE, 519 BUFFER_LOAD_FORMAT_D16, 520 SBUFFER_LOAD, 521 BUFFER_STORE, 522 BUFFER_STORE_BYTE, 523 BUFFER_STORE_SHORT, 524 BUFFER_STORE_FORMAT, 525 BUFFER_STORE_FORMAT_D16, 526 BUFFER_ATOMIC_SWAP, 527 BUFFER_ATOMIC_ADD, 528 BUFFER_ATOMIC_SUB, 529 BUFFER_ATOMIC_SMIN, 530 BUFFER_ATOMIC_UMIN, 531 BUFFER_ATOMIC_SMAX, 532 BUFFER_ATOMIC_UMAX, 533 BUFFER_ATOMIC_AND, 534 BUFFER_ATOMIC_OR, 535 BUFFER_ATOMIC_XOR, 536 BUFFER_ATOMIC_INC, 537 BUFFER_ATOMIC_DEC, 538 BUFFER_ATOMIC_CMPSWAP, 539 BUFFER_ATOMIC_CSUB, 540 BUFFER_ATOMIC_FADD, 541 BUFFER_ATOMIC_FMIN, 542 BUFFER_ATOMIC_FMAX, 543 544 LAST_AMDGPU_ISD_NUMBER 545 }; 546 547 } // End namespace AMDGPUISD 548 549 } // End namespace llvm 550 551 #endif 552