1 //===- AMDGPUGlobalISelUtils -------------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H 10 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H 11 12 #include "llvm/ADT/ArrayRef.h" 13 #include "llvm/CodeGen/Register.h" 14 #include <utility> 15 16 namespace llvm { 17 18 class MachineRegisterInfo; 19 class GCNSubtarget; 20 class LLT; 21 22 namespace AMDGPU { 23 24 /// Returns base register and constant offset. 25 std::pair<Register, unsigned> 26 getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg); 27 28 bool isLegalVOP3PShuffleMask(ArrayRef<int> Mask); 29 bool hasAtomicFaddRtnForTy(const GCNSubtarget &Subtarget, const LLT &Ty); 30 } 31 } 32 33 #endif 34