1480093f4SDimitry Andric //===- AMDGPUGlobalISelUtils -------------------------------------*- C++ -*-==// 2480093f4SDimitry Andric // 3480093f4SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4480093f4SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5480093f4SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6480093f4SDimitry Andric // 7480093f4SDimitry Andric //===----------------------------------------------------------------------===// 8480093f4SDimitry Andric 9480093f4SDimitry Andric #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H 10480093f4SDimitry Andric #define LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H 11480093f4SDimitry Andric 12480093f4SDimitry Andric #include "llvm/CodeGen/Register.h" 13*e8d8bef9SDimitry Andric #include <utility> 14480093f4SDimitry Andric 15480093f4SDimitry Andric namespace llvm { 16480093f4SDimitry Andric 17480093f4SDimitry Andric class MachineRegisterInfo; 18480093f4SDimitry Andric 19480093f4SDimitry Andric namespace AMDGPU { 20480093f4SDimitry Andric 21*e8d8bef9SDimitry Andric /// Returns base register and constant offset. 22*e8d8bef9SDimitry Andric std::pair<Register, unsigned> 23480093f4SDimitry Andric getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg); 24480093f4SDimitry Andric 255ffd83dbSDimitry Andric bool isLegalVOP3PShuffleMask(ArrayRef<int> Mask); 265ffd83dbSDimitry Andric 27480093f4SDimitry Andric } 28480093f4SDimitry Andric } 29480093f4SDimitry Andric 30480093f4SDimitry Andric #endif 31