1480093f4SDimitry Andric //===- AMDGPUGlobalISelUtils -------------------------------------*- C++ -*-==// 2480093f4SDimitry Andric // 3480093f4SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4480093f4SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5480093f4SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6480093f4SDimitry Andric // 7480093f4SDimitry Andric //===----------------------------------------------------------------------===// 8480093f4SDimitry Andric 9480093f4SDimitry Andric #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H 10480093f4SDimitry Andric #define LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H 11480093f4SDimitry Andric 12fe6060f1SDimitry Andric #include "llvm/ADT/ArrayRef.h" 13480093f4SDimitry Andric #include "llvm/CodeGen/Register.h" 14e8d8bef9SDimitry Andric #include <utility> 15480093f4SDimitry Andric 16480093f4SDimitry Andric namespace llvm { 17480093f4SDimitry Andric 18480093f4SDimitry Andric class MachineRegisterInfo; 1981ad6265SDimitry Andric class GCNSubtarget; 20*bdd1243dSDimitry Andric class GISelKnownBits; 2181ad6265SDimitry Andric class LLT; 22480093f4SDimitry Andric 23480093f4SDimitry Andric namespace AMDGPU { 24480093f4SDimitry Andric 25e8d8bef9SDimitry Andric /// Returns base register and constant offset. 26e8d8bef9SDimitry Andric std::pair<Register, unsigned> 27*bdd1243dSDimitry Andric getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg, 28*bdd1243dSDimitry Andric GISelKnownBits *KnownBits = nullptr); 29480093f4SDimitry Andric 3081ad6265SDimitry Andric bool hasAtomicFaddRtnForTy(const GCNSubtarget &Subtarget, const LLT &Ty); 31480093f4SDimitry Andric } 32480093f4SDimitry Andric } 33480093f4SDimitry Andric 34480093f4SDimitry Andric #endif 35