1480093f4SDimitry Andric //===- AMDGPUGlobalISelUtils -------------------------------------*- C++ -*-==// 2480093f4SDimitry Andric // 3480093f4SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4480093f4SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5480093f4SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6480093f4SDimitry Andric // 7480093f4SDimitry Andric //===----------------------------------------------------------------------===// 8480093f4SDimitry Andric 9480093f4SDimitry Andric #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H 10480093f4SDimitry Andric #define LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H 11480093f4SDimitry Andric 12*5ffd83dbSDimitry Andric #include "AMDGPUInstrInfo.h" 13480093f4SDimitry Andric #include "llvm/CodeGen/Register.h" 14480093f4SDimitry Andric #include <tuple> 15480093f4SDimitry Andric 16480093f4SDimitry Andric namespace llvm { 17480093f4SDimitry Andric 18480093f4SDimitry Andric class MachineInstr; 19480093f4SDimitry Andric class MachineRegisterInfo; 20480093f4SDimitry Andric 21480093f4SDimitry Andric namespace AMDGPU { 22480093f4SDimitry Andric 23480093f4SDimitry Andric /// Returns Base register, constant offset, and offset def point. 24480093f4SDimitry Andric std::tuple<Register, unsigned, MachineInstr *> 25480093f4SDimitry Andric getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg); 26480093f4SDimitry Andric 27*5ffd83dbSDimitry Andric bool isLegalVOP3PShuffleMask(ArrayRef<int> Mask); 28*5ffd83dbSDimitry Andric 29*5ffd83dbSDimitry Andric /// Return number of address arguments, and the number of gradients for an image 30*5ffd83dbSDimitry Andric /// intrinsic. 31*5ffd83dbSDimitry Andric inline std::pair<int, int> 32*5ffd83dbSDimitry Andric getImageNumVAddr(const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr, 33*5ffd83dbSDimitry Andric const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode) { 34*5ffd83dbSDimitry Andric const AMDGPU::MIMGDimInfo *DimInfo 35*5ffd83dbSDimitry Andric = AMDGPU::getMIMGDimInfo(ImageDimIntr->Dim); 36*5ffd83dbSDimitry Andric 37*5ffd83dbSDimitry Andric int NumGradients = BaseOpcode->Gradients ? DimInfo->NumGradients : 0; 38*5ffd83dbSDimitry Andric int NumCoords = BaseOpcode->Coordinates ? DimInfo->NumCoords : 0; 39*5ffd83dbSDimitry Andric int NumLCM = BaseOpcode->LodOrClampOrMip ? 1 : 0; 40*5ffd83dbSDimitry Andric int NumVAddr = BaseOpcode->NumExtraArgs + NumGradients + NumCoords + NumLCM; 41*5ffd83dbSDimitry Andric return {NumVAddr, NumGradients}; 42*5ffd83dbSDimitry Andric } 43*5ffd83dbSDimitry Andric 44*5ffd83dbSDimitry Andric /// Return index of dmask in an gMIR image intrinsic 45*5ffd83dbSDimitry Andric inline int getDMaskIdx(const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode, 46*5ffd83dbSDimitry Andric int NumDefs) { 47*5ffd83dbSDimitry Andric assert(!BaseOpcode->Atomic); 48*5ffd83dbSDimitry Andric return NumDefs + 1 + (BaseOpcode->Store ? 1 : 0); 49*5ffd83dbSDimitry Andric } 50*5ffd83dbSDimitry Andric 51*5ffd83dbSDimitry Andric /// Return first address operand index in a gMIR image intrinsic. 52*5ffd83dbSDimitry Andric inline int getImageVAddrIdxBegin(const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode, 53*5ffd83dbSDimitry Andric int NumDefs) { 54*5ffd83dbSDimitry Andric if (BaseOpcode->Atomic) 55*5ffd83dbSDimitry Andric return NumDefs + 1 + (BaseOpcode->AtomicX2 ? 2 : 1); 56*5ffd83dbSDimitry Andric return getDMaskIdx(BaseOpcode, NumDefs) + 1; 57*5ffd83dbSDimitry Andric } 58*5ffd83dbSDimitry Andric 59480093f4SDimitry Andric } 60480093f4SDimitry Andric } 61480093f4SDimitry Andric 62480093f4SDimitry Andric #endif 63