1*480093f4SDimitry Andric //===- AMDGPUGlobalISelUtils -------------------------------------*- C++ -*-==// 2*480093f4SDimitry Andric // 3*480093f4SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*480093f4SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*480093f4SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*480093f4SDimitry Andric // 7*480093f4SDimitry Andric //===----------------------------------------------------------------------===// 8*480093f4SDimitry Andric 9*480093f4SDimitry Andric #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H 10*480093f4SDimitry Andric #define LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H 11*480093f4SDimitry Andric 12*480093f4SDimitry Andric #include "llvm/CodeGen/Register.h" 13*480093f4SDimitry Andric #include <tuple> 14*480093f4SDimitry Andric 15*480093f4SDimitry Andric namespace llvm { 16*480093f4SDimitry Andric 17*480093f4SDimitry Andric class MachineInstr; 18*480093f4SDimitry Andric class MachineRegisterInfo; 19*480093f4SDimitry Andric 20*480093f4SDimitry Andric namespace AMDGPU { 21*480093f4SDimitry Andric 22*480093f4SDimitry Andric /// Returns Base register, constant offset, and offset def point. 23*480093f4SDimitry Andric std::tuple<Register, unsigned, MachineInstr *> 24*480093f4SDimitry Andric getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg); 25*480093f4SDimitry Andric 26*480093f4SDimitry Andric } 27*480093f4SDimitry Andric } 28*480093f4SDimitry Andric 29*480093f4SDimitry Andric #endif 30