1//===- AMDGPUGenRegisterBankInfo.def -----------------------------*- C++ -*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// \file 9/// This file defines all the static objects used by AMDGPURegisterBankInfo. 10/// \todo This should be generated by TableGen. 11//===----------------------------------------------------------------------===// 12 13namespace llvm { 14namespace AMDGPU { 15 16enum PartialMappingIdx { 17 None = - 1, 18 PM_SGPR1 = 2, 19 PM_SGPR16 = 6, 20 PM_SGPR32 = 7, 21 PM_SGPR64 = 8, 22 PM_SGPR128 = 9, 23 PM_SGPR256 = 10, 24 PM_SGPR512 = 11, 25 PM_SGPR1024 = 12, 26 PM_VGPR1 = 13, 27 PM_VGPR16 = 17, 28 PM_VGPR32 = 18, 29 PM_VGPR64 = 19, 30 PM_VGPR128 = 20, 31 PM_VGPR256 = 21, 32 PM_VGPR512 = 22, 33 PM_VGPR1024 = 23, 34 PM_SGPR96 = 24, 35 PM_VGPR96 = 25 36}; 37 38const RegisterBankInfo::PartialMapping PartMappings[] { 39 // StartIdx, Length, RegBank 40 {0, 1, SCCRegBank}, 41 {0, 1, VCCRegBank}, 42 43 {0, 1, SGPRRegBank}, // SGPR begin 44 {0, 16, SGPRRegBank}, 45 {0, 32, SGPRRegBank}, 46 {0, 64, SGPRRegBank}, 47 {0, 128, SGPRRegBank}, 48 {0, 256, SGPRRegBank}, 49 {0, 512, SGPRRegBank}, 50 {0, 1024, SGPRRegBank}, 51 52 {0, 1, VGPRRegBank}, // VGPR begin 53 {0, 16, VGPRRegBank}, 54 {0, 32, VGPRRegBank}, 55 {0, 64, VGPRRegBank}, 56 {0, 128, VGPRRegBank}, 57 {0, 256, VGPRRegBank}, 58 {0, 512, VGPRRegBank}, 59 {0, 1024, VGPRRegBank}, 60 {0, 96, SGPRRegBank}, 61 {0, 96, VGPRRegBank} 62}; 63 64const RegisterBankInfo::ValueMapping ValMappings[] { 65 // SCC 66 {&PartMappings[0], 1}, 67 68 // VCC 69 {&PartMappings[1], 1}, 70 71 // SGPRs 72 {&PartMappings[2], 1}, // 1 73 {nullptr, 0}, // Illegal power of 2 sizes 74 {nullptr, 0}, 75 {nullptr, 0}, 76 {&PartMappings[3], 1}, // 16 77 {&PartMappings[4], 1}, // 32 78 {&PartMappings[5], 1}, // 64 79 {&PartMappings[6], 1}, // 128 80 {&PartMappings[7], 1}, // 256 81 {&PartMappings[8], 1}, // 512 82 {&PartMappings[9], 1}, // 1024 83 84 // VGPRs 85 {&PartMappings[10], 1}, // 1 86 {nullptr, 0}, 87 {nullptr, 0}, 88 {nullptr, 0}, 89 {&PartMappings[11], 1}, // 16 90 {&PartMappings[12], 1}, // 32 91 {&PartMappings[13], 1}, // 64 92 {&PartMappings[14], 1}, // 128 93 {&PartMappings[15], 1}, // 256 94 {&PartMappings[16], 1}, // 512 95 {&PartMappings[17], 1}, // 1024 96 {&PartMappings[18], 1}, 97 {&PartMappings[19], 1} 98}; 99 100const RegisterBankInfo::PartialMapping SGPROnly64BreakDown[] { 101 {0, 32, SGPRRegBank}, // 32-bit op 102 {0, 32, SGPRRegBank}, // 2x32-bit op 103 {32, 32, SGPRRegBank}, 104 {0, 64, SGPRRegBank}, // <2x32-bit> op 105 106 {0, 32, VGPRRegBank}, // 32-bit op 107 {0, 32, VGPRRegBank}, // 2x32-bit op 108 {32, 32, VGPRRegBank}, 109}; 110 111 112// For some instructions which can operate 64-bit only for the scalar version. 113const RegisterBankInfo::ValueMapping ValMappingsSGPR64OnlyVGPR32[] { 114 /*32-bit sgpr*/ {&SGPROnly64BreakDown[0], 1}, 115 /*2 x 32-bit sgpr*/ {&SGPROnly64BreakDown[1], 2}, 116 /*64-bit sgpr */ {&SGPROnly64BreakDown[3], 1}, 117 118 /*32-bit vgpr*/ {&SGPROnly64BreakDown[4], 1}, 119 /*2 x 32-bit vgpr*/ {&SGPROnly64BreakDown[5], 2} 120}; 121 122enum ValueMappingIdx { 123 SCCStartIdx = 0, 124 SGPRStartIdx = 2, 125 VGPRStartIdx = 13 126}; 127 128const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID, 129 unsigned Size) { 130 unsigned Idx; 131 switch (Size) { 132 case 1: 133 if (BankID == AMDGPU::SCCRegBankID) 134 return &ValMappings[0]; 135 if (BankID == AMDGPU::VCCRegBankID) 136 return &ValMappings[1]; 137 138 // 1-bit values not from a compare etc. 139 Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR1 : PM_VGPR1; 140 break; 141 case 96: 142 assert(BankID != AMDGPU::VCCRegBankID); 143 Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR96 : PM_VGPR96; 144 break; 145 default: 146 assert(BankID != AMDGPU::VCCRegBankID); 147 Idx = BankID == AMDGPU::VGPRRegBankID ? VGPRStartIdx : SGPRStartIdx; 148 Idx += Log2_32_Ceil(Size); 149 break; 150 } 151 152 assert(Log2_32_Ceil(Size) == Log2_32_Ceil(ValMappings[Idx].BreakDown->Length)); 153 assert(BankID == ValMappings[Idx].BreakDown->RegBank->getID()); 154 155 return &ValMappings[Idx]; 156} 157 158const RegisterBankInfo::ValueMapping *getValueMappingSGPR64Only(unsigned BankID, 159 unsigned Size) { 160 if (Size != 64) 161 return getValueMapping(BankID, Size); 162 163 if (BankID == AMDGPU::VGPRRegBankID) 164 return &ValMappingsSGPR64OnlyVGPR32[4]; 165 166 assert(BankID == AMDGPU::SGPRRegBankID); 167 return &ValMappingsSGPR64OnlyVGPR32[2]; 168} 169 170const RegisterBankInfo::PartialMapping LoadSGPROnlyBreakDown[] { 171 /* 256-bit load */ {0, 256, SGPRRegBank}, 172 /* 512-bit load */ {0, 512, SGPRRegBank}, 173 /* 8 32-bit loads */ {0, 32, VGPRRegBank}, {32, 32, VGPRRegBank}, 174 {64, 32, VGPRRegBank}, {96, 32, VGPRRegBank}, 175 {128, 32, VGPRRegBank}, {160, 32, VGPRRegBank}, 176 {192, 32, VGPRRegBank}, {224, 32, VGPRRegBank}, 177 /* 16 32-bit loads */ {0, 32, VGPRRegBank}, {32, 32, VGPRRegBank}, 178 {64, 32, VGPRRegBank}, {96, 32, VGPRRegBank}, 179 {128, 32, VGPRRegBank}, {160, 32, VGPRRegBank}, 180 {192, 32, VGPRRegBank}, {224, 32, VGPRRegBank}, 181 {256, 32, VGPRRegBank}, {288, 32, VGPRRegBank}, 182 {320, 32, VGPRRegBank}, {352, 32, VGPRRegBank}, 183 {384, 32, VGPRRegBank}, {416, 32, VGPRRegBank}, 184 {448, 32, VGPRRegBank}, {480, 32, VGPRRegBank}, 185 /* 4 64-bit loads */ {0, 64, VGPRRegBank}, {64, 64, VGPRRegBank}, 186 {128, 64, VGPRRegBank}, {192, 64, VGPRRegBank}, 187 /* 8 64-bit loads */ {0, 64, VGPRRegBank}, {64, 64, VGPRRegBank}, 188 {128, 64, VGPRRegBank}, {192, 64, VGPRRegBank}, 189 {256, 64, VGPRRegBank}, {320, 64, VGPRRegBank}, 190 {384, 64, VGPRRegBank}, {448, 64, VGPRRegBank}, 191 192 /* FIXME: The generic register bank select does not support complex 193 * break downs where the number of vector elements does not equal the 194 * number of breakdowns. 195 * FIXME: register bank select now tries to handle complex break downs, 196 * but it emits an illegal instruction: 197 * %1:vgpr(<8 x s32>) = G_CONCAT_VECTORS %2:vgpr(s128), %3:vgpr(s128) 198 */ 199 /* 2 128-bit loads */ {0, 128, VGPRRegBank}, {128, 128, VGPRRegBank}, 200 /* 4 128-bit loads */ {0, 128, VGPRRegBank}, {128, 128, VGPRRegBank}, 201 {256, 128, VGPRRegBank}, {384, 128, VGPRRegBank} 202}; 203 204const RegisterBankInfo::ValueMapping ValMappingsLoadSGPROnly[] { 205 /* 256-bit load */ {&LoadSGPROnlyBreakDown[0], 1}, 206 /* 512-bit load */ {&LoadSGPROnlyBreakDown[1], 1}, 207 /* <8 x i32> load */ {&LoadSGPROnlyBreakDown[2], 8}, 208 /* <16 x i32> load */ {&LoadSGPROnlyBreakDown[10], 16}, 209 /* <4 x i64> load */ {&LoadSGPROnlyBreakDown[26], 4}, 210 /* <8 x i64> load */ {&LoadSGPROnlyBreakDown[30], 8} 211}; 212 213const RegisterBankInfo::ValueMapping * 214getValueMappingLoadSGPROnly(unsigned BankID, LLT SizeTy) { 215 unsigned Size = SizeTy.getSizeInBits(); 216 if (Size < 256 || BankID == AMDGPU::SGPRRegBankID) 217 return getValueMapping(BankID, Size); 218 219 assert((Size == 256 || Size == 512) && BankID == AMDGPU::VGPRRegBankID); 220 221 // Default to using the non-split ValueMappings, we will use these if 222 // the register bank is SGPR or if we don't know how to handle the vector 223 // type. 224 unsigned Idx = Size == 256 ? 0 : 1; 225 226 // We need to split this load if it has a vgpr pointer. 227 if (BankID == AMDGPU::VGPRRegBankID) { 228 if (SizeTy == LLT::vector(8, 32)) 229 Idx = 2; 230 else if (SizeTy == LLT::vector(16, 32)) 231 Idx = 3; 232 else if (SizeTy == LLT::vector(4, 64)) 233 Idx = 4; 234 else if (SizeTy == LLT::vector(8, 64)) 235 Idx = 5; 236 } 237 238 return &ValMappingsLoadSGPROnly[Idx]; 239} 240 241 242} // End AMDGPU namespace. 243} // End llvm namespace. 244