1//===-- AMDGPUGIsel.td - AMDGPU GlobalISel Patterns---------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// This files contains patterns that should only be used by GlobalISel. For 9// example patterns for V_* instructions that have S_* equivalents. 10// SelectionDAG does not support selecting V_* instructions. 11//===----------------------------------------------------------------------===// 12 13include "AMDGPU.td" 14include "AMDGPUCombine.td" 15 16def sd_vsrc0 : ComplexPattern<i32, 1, "">; 17def gi_vsrc0 : 18 GIComplexOperandMatcher<s32, "selectVSRC0">, 19 GIComplexPatternEquiv<sd_vsrc0>; 20 21def sd_vcsrc : ComplexPattern<i32, 1, "">; 22def gi_vcsrc : 23 GIComplexOperandMatcher<s32, "selectVCSRC">, 24 GIComplexPatternEquiv<sd_vcsrc>; 25 26def gi_vop3mods0 : 27 GIComplexOperandMatcher<s32, "selectVOP3Mods0">, 28 GIComplexPatternEquiv<VOP3Mods0>; 29 30def gi_vop3mods : 31 GIComplexOperandMatcher<s32, "selectVOP3Mods">, 32 GIComplexPatternEquiv<VOP3Mods>; 33 34def gi_vop3_no_mods : 35 GIComplexOperandMatcher<s32, "selectVOP3NoMods">, 36 GIComplexPatternEquiv<VOP3NoMods>; 37 38def gi_vop3mods_nnan : 39 GIComplexOperandMatcher<s32, "selectVOP3Mods_nnan">, 40 GIComplexPatternEquiv<VOP3Mods_nnan>; 41 42def gi_vop3omods : 43 GIComplexOperandMatcher<s32, "selectVOP3OMods">, 44 GIComplexPatternEquiv<VOP3OMods>; 45 46def gi_vop3pmods : 47 GIComplexOperandMatcher<s32, "selectVOP3PMods">, 48 GIComplexPatternEquiv<VOP3PMods>; 49 50def gi_vop3pmodsdot : 51 GIComplexOperandMatcher<s32, "selectVOP3PModsDOT">, 52 GIComplexPatternEquiv<VOP3PModsDOT>; 53 54def gi_dotiuvop3pmods : 55 GIComplexOperandMatcher<s32, "selectDotIUVOP3PMods">, 56 GIComplexPatternEquiv<DotIUVOP3PMods>; 57 58def gi_wmmaopselvop3pmods : 59 GIComplexOperandMatcher<s32, "selectWMMAOpSelVOP3PMods">, 60 GIComplexPatternEquiv<WMMAOpSelVOP3PMods>; 61 62def gi_vop3opselmods : 63 GIComplexOperandMatcher<s32, "selectVOP3OpSelMods">, 64 GIComplexPatternEquiv<VOP3OpSelMods>; 65 66def gi_vinterpmods : 67 GIComplexOperandMatcher<s32, "selectVINTERPMods">, 68 GIComplexPatternEquiv<VINTERPMods>; 69 70def gi_vinterpmods_hi : 71 GIComplexOperandMatcher<s32, "selectVINTERPModsHi">, 72 GIComplexPatternEquiv<VINTERPModsHi>; 73 74// FIXME: Why do we have both VOP3OpSel and VOP3OpSelMods? 75def gi_vop3opsel : 76 GIComplexOperandMatcher<s32, "selectVOP3OpSelMods">, 77 GIComplexPatternEquiv<VOP3OpSel>; 78 79def gi_smrd_imm : 80 GIComplexOperandMatcher<s64, "selectSmrdImm">, 81 GIComplexPatternEquiv<SMRDImm>; 82 83def gi_smrd_imm32 : 84 GIComplexOperandMatcher<s64, "selectSmrdImm32">, 85 GIComplexPatternEquiv<SMRDImm32>; 86 87def gi_smrd_sgpr : 88 GIComplexOperandMatcher<s64, "selectSmrdSgpr">, 89 GIComplexPatternEquiv<SMRDSgpr>; 90 91def gi_smrd_sgpr_imm : 92 GIComplexOperandMatcher<s64, "selectSmrdSgprImm">, 93 GIComplexPatternEquiv<SMRDSgprImm>; 94 95def gi_flat_offset : 96 GIComplexOperandMatcher<s64, "selectFlatOffset">, 97 GIComplexPatternEquiv<FlatOffset>; 98def gi_global_offset : 99 GIComplexOperandMatcher<s64, "selectGlobalOffset">, 100 GIComplexPatternEquiv<GlobalOffset>; 101def gi_global_saddr : 102 GIComplexOperandMatcher<s64, "selectGlobalSAddr">, 103 GIComplexPatternEquiv<GlobalSAddr>; 104 105def gi_mubuf_scratch_offset : 106 GIComplexOperandMatcher<s32, "selectMUBUFScratchOffset">, 107 GIComplexPatternEquiv<MUBUFScratchOffset>; 108def gi_mubuf_scratch_offen : 109 GIComplexOperandMatcher<s32, "selectMUBUFScratchOffen">, 110 GIComplexPatternEquiv<MUBUFScratchOffen>; 111 112def gi_flat_scratch_offset : 113 GIComplexOperandMatcher<s32, "selectScratchOffset">, 114 GIComplexPatternEquiv<ScratchOffset>; 115 116def gi_flat_scratch_saddr : 117 GIComplexOperandMatcher<s32, "selectScratchSAddr">, 118 GIComplexPatternEquiv<ScratchSAddr>; 119 120def gi_flat_scratch_svaddr : 121 GIComplexOperandMatcher<s32, "selectScratchSVAddr">, 122 GIComplexPatternEquiv<ScratchSVAddr>; 123 124def gi_ds_1addr_1offset : 125 GIComplexOperandMatcher<s32, "selectDS1Addr1Offset">, 126 GIComplexPatternEquiv<DS1Addr1Offset>; 127 128def gi_ds_64bit_4byte_aligned : 129 GIComplexOperandMatcher<s64, "selectDS64Bit4ByteAligned">, 130 GIComplexPatternEquiv<DS64Bit4ByteAligned>; 131 132def gi_ds_128bit_8byte_aligned : 133 GIComplexOperandMatcher<s64, "selectDS128Bit8ByteAligned">, 134 GIComplexPatternEquiv<DS128Bit8ByteAligned>; 135 136def gi_mubuf_addr64 : 137 GIComplexOperandMatcher<s64, "selectMUBUFAddr64">, 138 GIComplexPatternEquiv<MUBUFAddr64>; 139 140def gi_mubuf_offset : 141 GIComplexOperandMatcher<s64, "selectMUBUFOffset">, 142 GIComplexPatternEquiv<MUBUFOffset>; 143 144def gi_smrd_buffer_imm : 145 GIComplexOperandMatcher<s64, "selectSMRDBufferImm">, 146 GIComplexPatternEquiv<SMRDBufferImm>; 147 148def gi_smrd_buffer_imm32 : 149 GIComplexOperandMatcher<s64, "selectSMRDBufferImm32">, 150 GIComplexPatternEquiv<SMRDBufferImm32>; 151 152// Separate load nodes are defined to glue m0 initialization in 153// SelectionDAG. The GISel selector can just insert m0 initialization 154// directly before selecting a glue-less load, so hide this 155// distinction. 156 157def : GINodeEquiv<G_LOAD, AMDGPUld_glue> { 158 let CheckMMOIsNonAtomic = 1; 159 let IfSignExtend = G_SEXTLOAD; 160 let IfZeroExtend = G_ZEXTLOAD; 161} 162 163def : GINodeEquiv<G_STORE, AMDGPUst_glue> { 164 let CheckMMOIsNonAtomic = 1; 165} 166 167def : GINodeEquiv<G_LOAD, AMDGPUatomic_ld_glue> { 168 bit CheckMMOIsAtomic = 1; 169} 170 171def : GINodeEquiv<G_STORE, AMDGPUatomic_st_glue> { 172 bit CheckMMOIsAtomic = 1; 173} 174 175 176def : GINodeEquiv<G_ATOMIC_CMPXCHG, atomic_cmp_swap_glue>; 177def : GINodeEquiv<G_ATOMICRMW_XCHG, atomic_swap_glue>; 178def : GINodeEquiv<G_ATOMICRMW_ADD, atomic_load_add_glue>; 179def : GINodeEquiv<G_ATOMICRMW_SUB, atomic_load_sub_glue>; 180def : GINodeEquiv<G_ATOMICRMW_AND, atomic_load_and_glue>; 181def : GINodeEquiv<G_ATOMICRMW_OR, atomic_load_or_glue>; 182def : GINodeEquiv<G_ATOMICRMW_XOR, atomic_load_xor_glue>; 183def : GINodeEquiv<G_ATOMICRMW_MIN, atomic_load_min_glue>; 184def : GINodeEquiv<G_ATOMICRMW_MAX, atomic_load_max_glue>; 185def : GINodeEquiv<G_ATOMICRMW_UMIN, atomic_load_umin_glue>; 186def : GINodeEquiv<G_ATOMICRMW_UMAX, atomic_load_umax_glue>; 187def : GINodeEquiv<G_ATOMICRMW_FADD, atomic_load_fadd_glue>; 188 189def : GINodeEquiv<G_AMDGPU_FFBH_U32, AMDGPUffbh_u32_impl>; 190def : GINodeEquiv<G_AMDGPU_FFBL_B32, AMDGPUffbl_b32_impl>; 191def : GINodeEquiv<G_AMDGPU_FMIN_LEGACY, AMDGPUfmin_legacy>; 192def : GINodeEquiv<G_AMDGPU_FMAX_LEGACY, AMDGPUfmax_legacy>; 193def : GINodeEquiv<G_AMDGPU_RCP_IFLAG, AMDGPUrcp_iflag>; 194 195def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE0, AMDGPUcvt_f32_ubyte0>; 196def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE1, AMDGPUcvt_f32_ubyte1>; 197def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE2, AMDGPUcvt_f32_ubyte2>; 198def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE3, AMDGPUcvt_f32_ubyte3>; 199 200def : GINodeEquiv<G_AMDGPU_CVT_PK_I16_I32, AMDGPUpk_i16_i32_impl>; 201def : GINodeEquiv<G_AMDGPU_SMED3, AMDGPUsmed3>; 202def : GINodeEquiv<G_AMDGPU_UMED3, AMDGPUumed3>; 203def : GINodeEquiv<G_AMDGPU_FMED3, AMDGPUfmed3_impl>; 204def : GINodeEquiv<G_AMDGPU_CLAMP, AMDGPUclamp>; 205 206def : GINodeEquiv<G_AMDGPU_ATOMIC_CMPXCHG, AMDGPUatomic_cmp_swap>; 207def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD, SIbuffer_load>; 208def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_USHORT, SIbuffer_load_ushort>; 209def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_UBYTE, SIbuffer_load_ubyte>; 210def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_SSHORT, SIbuffer_load_short>; 211def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_SBYTE, SIbuffer_load_byte>; 212def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_FORMAT, SIbuffer_load_format>; 213def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_FORMAT_D16, SIbuffer_load_format_d16>; 214def : GINodeEquiv<G_AMDGPU_TBUFFER_LOAD_FORMAT, SItbuffer_load>; 215def : GINodeEquiv<G_AMDGPU_TBUFFER_LOAD_FORMAT_D16, SItbuffer_load_d16>; 216def : GINodeEquiv<G_AMDGPU_BUFFER_STORE, SIbuffer_store>; 217def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_SHORT, SIbuffer_store_short>; 218def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_BYTE, SIbuffer_store_byte>; 219def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_FORMAT, SIbuffer_store_format>; 220def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_FORMAT_D16, SIbuffer_store_format_d16>; 221def : GINodeEquiv<G_AMDGPU_TBUFFER_STORE_FORMAT, SItbuffer_store>; 222def : GINodeEquiv<G_AMDGPU_TBUFFER_STORE_FORMAT_D16, SItbuffer_store_d16>; 223 224// FIXME: Check MMO is atomic 225def : GINodeEquiv<G_AMDGPU_ATOMIC_INC, SIatomic_inc>; 226def : GINodeEquiv<G_AMDGPU_ATOMIC_DEC, SIatomic_dec>; 227def : GINodeEquiv<G_AMDGPU_ATOMIC_INC, atomic_inc_glue>; 228def : GINodeEquiv<G_AMDGPU_ATOMIC_DEC, atomic_dec_glue>; 229def : GINodeEquiv<G_AMDGPU_ATOMIC_FMIN, SIatomic_fmin>; 230def : GINodeEquiv<G_AMDGPU_ATOMIC_FMAX, SIatomic_fmax>; 231def : GINodeEquiv<G_AMDGPU_ATOMIC_FMIN, atomic_load_fmin_glue>; 232def : GINodeEquiv<G_AMDGPU_ATOMIC_FMAX, atomic_load_fmax_glue>; 233 234 235def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SWAP, SIbuffer_atomic_swap>; 236def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_ADD, SIbuffer_atomic_add>; 237def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SUB, SIbuffer_atomic_sub>; 238def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SMIN, SIbuffer_atomic_smin>; 239def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_UMIN, SIbuffer_atomic_umin>; 240def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SMAX, SIbuffer_atomic_smax>; 241def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_UMAX, SIbuffer_atomic_umax>; 242def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_AND, SIbuffer_atomic_and>; 243def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_OR, SIbuffer_atomic_or>; 244def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_XOR, SIbuffer_atomic_xor>; 245def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_INC, SIbuffer_atomic_inc>; 246def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_DEC, SIbuffer_atomic_dec>; 247def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_FADD, SIbuffer_atomic_fadd>; 248def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_FMIN, SIbuffer_atomic_fmin>; 249def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_FMAX, SIbuffer_atomic_fmax>; 250def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_CMPSWAP, SIbuffer_atomic_cmpswap>; 251def : GINodeEquiv<G_AMDGPU_S_BUFFER_LOAD, SIsbuffer_load>; 252 253def : GINodeEquiv<G_FPTRUNC_ROUND_UPWARD, SIfptrunc_round_upward>; 254def : GINodeEquiv<G_FPTRUNC_ROUND_DOWNWARD, SIfptrunc_round_downward>; 255 256class GISelSop2Pat < 257 SDPatternOperator node, 258 Instruction inst, 259 ValueType dst_vt, 260 ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat < 261 262 (dst_vt (node (src0_vt SReg_32:$src0), (src1_vt SReg_32:$src1))), 263 (inst src0_vt:$src0, src1_vt:$src1) 264>; 265 266class GISelVop2Pat < 267 SDPatternOperator node, 268 Instruction inst, 269 ValueType dst_vt, 270 ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat < 271 272 (dst_vt (node (src0_vt (sd_vsrc0 src0_vt:$src0)), (src1_vt VGPR_32:$src1))), 273 (inst src0_vt:$src0, src1_vt:$src1) 274>; 275 276class GISelVop2CommutePat < 277 SDPatternOperator node, 278 Instruction inst, 279 ValueType dst_vt, 280 ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat < 281 282 (dst_vt (node (src1_vt VGPR_32:$src1), (src0_vt (sd_vsrc0 src0_vt:$src0)))), 283 (inst src0_vt:$src0, src1_vt:$src1) 284>; 285 286class GISelVop3Pat2 < 287 SDPatternOperator node, 288 Instruction inst, 289 ValueType dst_vt, 290 ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat < 291 292 (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))), 293 (inst src0_vt:$src0, src1_vt:$src1) 294>; 295 296class GISelVop3Pat2CommutePat < 297 SDPatternOperator node, 298 Instruction inst, 299 ValueType dst_vt, 300 ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat < 301 302 (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))), 303 (inst src0_vt:$src1, src1_vt:$src0) 304>; 305 306class GISelVop3Pat2ModsPat < 307 SDPatternOperator node, 308 Instruction inst, 309 ValueType dst_vt, 310 ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat < 311 312 (dst_vt (node (src0_vt (VOP3Mods0 src0_vt:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omods)), 313 (src1_vt (VOP3Mods src1_vt:$src1, i32:$src1_modifiers)))), 314 (inst i32:$src0_modifiers, src0_vt:$src0, 315 i32:$src1_modifiers, src1_vt:$src1, $clamp, $omods) 316>; 317 318multiclass GISelVop2IntrPat < 319 SDPatternOperator node, Instruction inst, 320 ValueType dst_vt, ValueType src_vt = dst_vt> { 321 322 def : GISelVop2Pat <node, inst, dst_vt, src_vt>; 323 324 // FIXME: Intrinsics aren't marked as commutable, so we need to add an explicit 325 // pattern to handle commuting. This is another reason why legalizing to a 326 // generic machine instruction may be better that matching the intrinsic 327 // directly. 328 def : GISelVop2CommutePat <node, inst, dst_vt, src_vt>; 329} 330 331// Since GlobalISel is more flexible then SelectionDAG, I think we can get 332// away with adding patterns for integer types and not legalizing all 333// loads and stores to vector types. This should help simplify the load/store 334// legalization. 335foreach Ty = [i64, p0, p1, p4] in { 336 defm : SMRD_Pattern <"S_LOAD_DWORDX2", Ty>; 337} 338 339def gi_as_i32timm : GICustomOperandRenderer<"renderTruncTImm">, 340 GISDNodeXFormEquiv<as_i32timm>; 341 342def gi_as_i16timm : GICustomOperandRenderer<"renderTruncTImm">, 343 GISDNodeXFormEquiv<as_i16timm>; 344 345def gi_as_i8timm : GICustomOperandRenderer<"renderTruncTImm">, 346 GISDNodeXFormEquiv<as_i8timm>; 347 348def gi_as_i1timm : GICustomOperandRenderer<"renderTruncTImm">, 349 GISDNodeXFormEquiv<as_i1timm>; 350 351def gi_NegateImm : GICustomOperandRenderer<"renderNegateImm">, 352 GISDNodeXFormEquiv<NegateImm>; 353 354def gi_bitcast_fpimm_to_i32 : GICustomOperandRenderer<"renderBitcastImm">, 355 GISDNodeXFormEquiv<bitcast_fpimm_to_i32>; 356 357def gi_IMMPopCount : GICustomOperandRenderer<"renderPopcntImm">, 358 GISDNodeXFormEquiv<IMMPopCount>; 359 360def gi_extract_cpol : GICustomOperandRenderer<"renderExtractCPol">, 361 GISDNodeXFormEquiv<extract_cpol>; 362 363def gi_extract_swz : GICustomOperandRenderer<"renderExtractSWZ">, 364 GISDNodeXFormEquiv<extract_swz>; 365 366def gi_set_glc : GICustomOperandRenderer<"renderSetGLC">, 367 GISDNodeXFormEquiv<set_glc>; 368 369def gi_frameindex_to_targetframeindex : GICustomOperandRenderer<"renderFrameIndex">, 370 GISDNodeXFormEquiv<frameindex_to_targetframeindex>; 371