1//===-- AMDGPUGIsel.td - AMDGPU GlobalISel Patterns---------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// This files contains patterns that should only be used by GlobalISel. For 9// example patterns for V_* instructions that have S_* equivalents. 10// SelectionDAG does not support selecting V_* instructions. 11//===----------------------------------------------------------------------===// 12 13include "AMDGPU.td" 14include "AMDGPUCombine.td" 15 16def sd_vsrc0 : ComplexPattern<i32, 1, "">; 17def gi_vsrc0 : 18 GIComplexOperandMatcher<s32, "selectVSRC0">, 19 GIComplexPatternEquiv<sd_vsrc0>; 20 21def sd_vcsrc : ComplexPattern<i32, 1, "">; 22def gi_vcsrc : 23 GIComplexOperandMatcher<s32, "selectVCSRC">, 24 GIComplexPatternEquiv<sd_vcsrc>; 25 26def gi_vop3mods0 : 27 GIComplexOperandMatcher<s32, "selectVOP3Mods0">, 28 GIComplexPatternEquiv<VOP3Mods0>; 29 30def gi_vop3mods : 31 GIComplexOperandMatcher<s32, "selectVOP3Mods">, 32 GIComplexPatternEquiv<VOP3Mods>; 33 34def gi_vop3_no_mods : 35 GIComplexOperandMatcher<s32, "selectVOP3NoMods">, 36 GIComplexPatternEquiv<VOP3NoMods>; 37 38def gi_vop3omods : 39 GIComplexOperandMatcher<s32, "selectVOP3OMods">, 40 GIComplexPatternEquiv<VOP3OMods>; 41 42def gi_vop3pmods : 43 GIComplexOperandMatcher<s32, "selectVOP3PMods">, 44 GIComplexPatternEquiv<VOP3PMods>; 45 46def gi_vop3pmodsdot : 47 GIComplexOperandMatcher<s32, "selectVOP3PModsDOT">, 48 GIComplexPatternEquiv<VOP3PModsDOT>; 49 50def gi_dotiuvop3pmods : 51 GIComplexOperandMatcher<s32, "selectDotIUVOP3PMods">, 52 GIComplexPatternEquiv<DotIUVOP3PMods>; 53 54def gi_wmmaopselvop3pmods : 55 GIComplexOperandMatcher<s32, "selectWMMAOpSelVOP3PMods">, 56 GIComplexPatternEquiv<WMMAOpSelVOP3PMods>; 57 58def gi_vop3opselmods : 59 GIComplexOperandMatcher<s32, "selectVOP3OpSelMods">, 60 GIComplexPatternEquiv<VOP3OpSelMods>; 61 62def gi_vinterpmods : 63 GIComplexOperandMatcher<s32, "selectVINTERPMods">, 64 GIComplexPatternEquiv<VINTERPMods>; 65 66def gi_vinterpmods_hi : 67 GIComplexOperandMatcher<s32, "selectVINTERPModsHi">, 68 GIComplexPatternEquiv<VINTERPModsHi>; 69 70// FIXME: Why do we have both VOP3OpSel and VOP3OpSelMods? 71def gi_vop3opsel : 72 GIComplexOperandMatcher<s32, "selectVOP3OpSelMods">, 73 GIComplexPatternEquiv<VOP3OpSel>; 74 75def gi_smrd_imm : 76 GIComplexOperandMatcher<s64, "selectSmrdImm">, 77 GIComplexPatternEquiv<SMRDImm>; 78 79def gi_smrd_imm32 : 80 GIComplexOperandMatcher<s64, "selectSmrdImm32">, 81 GIComplexPatternEquiv<SMRDImm32>; 82 83def gi_smrd_sgpr : 84 GIComplexOperandMatcher<s64, "selectSmrdSgpr">, 85 GIComplexPatternEquiv<SMRDSgpr>; 86 87def gi_smrd_sgpr_imm : 88 GIComplexOperandMatcher<s64, "selectSmrdSgprImm">, 89 GIComplexPatternEquiv<SMRDSgprImm>; 90 91def gi_flat_offset : 92 GIComplexOperandMatcher<s64, "selectFlatOffset">, 93 GIComplexPatternEquiv<FlatOffset>; 94def gi_global_offset : 95 GIComplexOperandMatcher<s64, "selectGlobalOffset">, 96 GIComplexPatternEquiv<GlobalOffset>; 97def gi_global_saddr : 98 GIComplexOperandMatcher<s64, "selectGlobalSAddr">, 99 GIComplexPatternEquiv<GlobalSAddr>; 100 101def gi_mubuf_scratch_offset : 102 GIComplexOperandMatcher<s32, "selectMUBUFScratchOffset">, 103 GIComplexPatternEquiv<MUBUFScratchOffset>; 104def gi_mubuf_scratch_offen : 105 GIComplexOperandMatcher<s32, "selectMUBUFScratchOffen">, 106 GIComplexPatternEquiv<MUBUFScratchOffen>; 107 108def gi_flat_scratch_offset : 109 GIComplexOperandMatcher<s32, "selectScratchOffset">, 110 GIComplexPatternEquiv<ScratchOffset>; 111 112def gi_flat_scratch_saddr : 113 GIComplexOperandMatcher<s32, "selectScratchSAddr">, 114 GIComplexPatternEquiv<ScratchSAddr>; 115 116def gi_flat_scratch_svaddr : 117 GIComplexOperandMatcher<s32, "selectScratchSVAddr">, 118 GIComplexPatternEquiv<ScratchSVAddr>; 119 120def gi_ds_1addr_1offset : 121 GIComplexOperandMatcher<s32, "selectDS1Addr1Offset">, 122 GIComplexPatternEquiv<DS1Addr1Offset>; 123 124def gi_ds_64bit_4byte_aligned : 125 GIComplexOperandMatcher<s64, "selectDS64Bit4ByteAligned">, 126 GIComplexPatternEquiv<DS64Bit4ByteAligned>; 127 128def gi_ds_128bit_8byte_aligned : 129 GIComplexOperandMatcher<s64, "selectDS128Bit8ByteAligned">, 130 GIComplexPatternEquiv<DS128Bit8ByteAligned>; 131 132def gi_mubuf_addr64 : 133 GIComplexOperandMatcher<s64, "selectMUBUFAddr64">, 134 GIComplexPatternEquiv<MUBUFAddr64>; 135 136def gi_mubuf_offset : 137 GIComplexOperandMatcher<s64, "selectMUBUFOffset">, 138 GIComplexPatternEquiv<MUBUFOffset>; 139 140def gi_smrd_buffer_imm : 141 GIComplexOperandMatcher<s64, "selectSMRDBufferImm">, 142 GIComplexPatternEquiv<SMRDBufferImm>; 143 144def gi_smrd_buffer_imm32 : 145 GIComplexOperandMatcher<s64, "selectSMRDBufferImm32">, 146 GIComplexPatternEquiv<SMRDBufferImm32>; 147 148def gi_smrd_buffer_sgpr_imm : 149 GIComplexOperandMatcher<s64, "selectSMRDBufferSgprImm">, 150 GIComplexPatternEquiv<SMRDBufferSgprImm>; 151 152def gi_vop3_mad_mix_mods : 153 GIComplexOperandMatcher<s64, "selectVOP3PMadMixMods">, 154 GIComplexPatternEquiv<VOP3PMadMixMods>; 155 156// Separate load nodes are defined to glue m0 initialization in 157// SelectionDAG. The GISel selector can just insert m0 initialization 158// directly before selecting a glue-less load, so hide this 159// distinction. 160 161def : GINodeEquiv<G_LOAD, AMDGPUld_glue> { 162 let CheckMMOIsNonAtomic = 1; 163 let IfSignExtend = G_SEXTLOAD; 164 let IfZeroExtend = G_ZEXTLOAD; 165} 166 167def : GINodeEquiv<G_STORE, AMDGPUst_glue> { 168 let CheckMMOIsNonAtomic = 1; 169} 170 171def : GINodeEquiv<G_LOAD, AMDGPUatomic_ld_glue> { 172 bit CheckMMOIsAtomic = 1; 173} 174 175def : GINodeEquiv<G_STORE, AMDGPUatomic_st_glue> { 176 bit CheckMMOIsAtomic = 1; 177} 178 179 180def : GINodeEquiv<G_ATOMIC_CMPXCHG, atomic_cmp_swap_glue>; 181def : GINodeEquiv<G_ATOMICRMW_XCHG, atomic_swap_glue>; 182def : GINodeEquiv<G_ATOMICRMW_ADD, atomic_load_add_glue>; 183def : GINodeEquiv<G_ATOMICRMW_SUB, atomic_load_sub_glue>; 184def : GINodeEquiv<G_ATOMICRMW_AND, atomic_load_and_glue>; 185def : GINodeEquiv<G_ATOMICRMW_OR, atomic_load_or_glue>; 186def : GINodeEquiv<G_ATOMICRMW_XOR, atomic_load_xor_glue>; 187def : GINodeEquiv<G_ATOMICRMW_MIN, atomic_load_min_glue>; 188def : GINodeEquiv<G_ATOMICRMW_MAX, atomic_load_max_glue>; 189def : GINodeEquiv<G_ATOMICRMW_UMIN, atomic_load_umin_glue>; 190def : GINodeEquiv<G_ATOMICRMW_UMAX, atomic_load_umax_glue>; 191def : GINodeEquiv<G_ATOMICRMW_FADD, atomic_load_fadd_glue>; 192 193def : GINodeEquiv<G_AMDGPU_FFBH_U32, AMDGPUffbh_u32_impl>; 194def : GINodeEquiv<G_AMDGPU_FFBL_B32, AMDGPUffbl_b32_impl>; 195def : GINodeEquiv<G_AMDGPU_FMIN_LEGACY, AMDGPUfmin_legacy>; 196def : GINodeEquiv<G_AMDGPU_FMAX_LEGACY, AMDGPUfmax_legacy>; 197def : GINodeEquiv<G_AMDGPU_RCP_IFLAG, AMDGPUrcp_iflag>; 198 199def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE0, AMDGPUcvt_f32_ubyte0>; 200def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE1, AMDGPUcvt_f32_ubyte1>; 201def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE2, AMDGPUcvt_f32_ubyte2>; 202def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE3, AMDGPUcvt_f32_ubyte3>; 203 204def : GINodeEquiv<G_AMDGPU_CVT_PK_I16_I32, AMDGPUpk_i16_i32_impl>; 205def : GINodeEquiv<G_AMDGPU_SMED3, AMDGPUsmed3>; 206def : GINodeEquiv<G_AMDGPU_UMED3, AMDGPUumed3>; 207def : GINodeEquiv<G_AMDGPU_FMED3, AMDGPUfmed3_impl>; 208def : GINodeEquiv<G_AMDGPU_CLAMP, AMDGPUclamp>; 209 210def : GINodeEquiv<G_AMDGPU_ATOMIC_CMPXCHG, AMDGPUatomic_cmp_swap>; 211def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD, SIbuffer_load>; 212def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_USHORT, SIbuffer_load_ushort>; 213def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_UBYTE, SIbuffer_load_ubyte>; 214def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_SSHORT, SIbuffer_load_short>; 215def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_SBYTE, SIbuffer_load_byte>; 216def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_FORMAT, SIbuffer_load_format>; 217def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_FORMAT_TFE, SIbuffer_load_format_tfe>; 218def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_FORMAT_D16, SIbuffer_load_format_d16>; 219def : GINodeEquiv<G_AMDGPU_TBUFFER_LOAD_FORMAT, SItbuffer_load>; 220def : GINodeEquiv<G_AMDGPU_TBUFFER_LOAD_FORMAT_D16, SItbuffer_load_d16>; 221def : GINodeEquiv<G_AMDGPU_BUFFER_STORE, SIbuffer_store>; 222def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_SHORT, SIbuffer_store_short>; 223def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_BYTE, SIbuffer_store_byte>; 224def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_FORMAT, SIbuffer_store_format>; 225def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_FORMAT_D16, SIbuffer_store_format_d16>; 226def : GINodeEquiv<G_AMDGPU_TBUFFER_STORE_FORMAT, SItbuffer_store>; 227def : GINodeEquiv<G_AMDGPU_TBUFFER_STORE_FORMAT_D16, SItbuffer_store_d16>; 228 229// FIXME: Check MMO is atomic 230def : GINodeEquiv<G_AMDGPU_ATOMIC_INC, SIatomic_inc>; 231def : GINodeEquiv<G_AMDGPU_ATOMIC_DEC, SIatomic_dec>; 232def : GINodeEquiv<G_AMDGPU_ATOMIC_INC, atomic_inc_glue>; 233def : GINodeEquiv<G_AMDGPU_ATOMIC_DEC, atomic_dec_glue>; 234def : GINodeEquiv<G_AMDGPU_ATOMIC_FMIN, SIatomic_fmin>; 235def : GINodeEquiv<G_AMDGPU_ATOMIC_FMAX, SIatomic_fmax>; 236def : GINodeEquiv<G_AMDGPU_ATOMIC_FMIN, atomic_load_fmin_glue>; 237def : GINodeEquiv<G_AMDGPU_ATOMIC_FMAX, atomic_load_fmax_glue>; 238 239 240def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SWAP, SIbuffer_atomic_swap>; 241def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_ADD, SIbuffer_atomic_add>; 242def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SUB, SIbuffer_atomic_sub>; 243def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SMIN, SIbuffer_atomic_smin>; 244def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_UMIN, SIbuffer_atomic_umin>; 245def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SMAX, SIbuffer_atomic_smax>; 246def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_UMAX, SIbuffer_atomic_umax>; 247def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_AND, SIbuffer_atomic_and>; 248def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_OR, SIbuffer_atomic_or>; 249def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_XOR, SIbuffer_atomic_xor>; 250def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_INC, SIbuffer_atomic_inc>; 251def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_DEC, SIbuffer_atomic_dec>; 252def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_FADD, SIbuffer_atomic_fadd>; 253def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_FMIN, SIbuffer_atomic_fmin>; 254def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_FMAX, SIbuffer_atomic_fmax>; 255def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_CMPSWAP, SIbuffer_atomic_cmpswap>; 256def : GINodeEquiv<G_AMDGPU_S_BUFFER_LOAD, SIsbuffer_load>; 257 258def : GINodeEquiv<G_FPTRUNC_ROUND_UPWARD, SIfptrunc_round_upward>; 259def : GINodeEquiv<G_FPTRUNC_ROUND_DOWNWARD, SIfptrunc_round_downward>; 260 261class GISelSop2Pat < 262 SDPatternOperator node, 263 Instruction inst, 264 ValueType dst_vt, 265 ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat < 266 267 (dst_vt (node (src0_vt SReg_32:$src0), (src1_vt SReg_32:$src1))), 268 (inst src0_vt:$src0, src1_vt:$src1) 269>; 270 271class GISelVop2Pat < 272 SDPatternOperator node, 273 Instruction inst, 274 ValueType dst_vt, 275 ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat < 276 277 (dst_vt (node (src0_vt (sd_vsrc0 src0_vt:$src0)), (src1_vt VGPR_32:$src1))), 278 (inst src0_vt:$src0, src1_vt:$src1) 279>; 280 281class GISelVop2CommutePat < 282 SDPatternOperator node, 283 Instruction inst, 284 ValueType dst_vt, 285 ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat < 286 287 (dst_vt (node (src1_vt VGPR_32:$src1), (src0_vt (sd_vsrc0 src0_vt:$src0)))), 288 (inst src0_vt:$src0, src1_vt:$src1) 289>; 290 291class GISelVop3Pat2 < 292 SDPatternOperator node, 293 Instruction inst, 294 ValueType dst_vt, 295 ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat < 296 297 (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))), 298 (inst src0_vt:$src0, src1_vt:$src1) 299>; 300 301class GISelVop3Pat2CommutePat < 302 SDPatternOperator node, 303 Instruction inst, 304 ValueType dst_vt, 305 ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat < 306 307 (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))), 308 (inst src0_vt:$src1, src1_vt:$src0) 309>; 310 311class GISelVop3Pat2ModsPat < 312 SDPatternOperator node, 313 Instruction inst, 314 ValueType dst_vt, 315 ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat < 316 317 (dst_vt (node (src0_vt (VOP3Mods0 src0_vt:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omods)), 318 (src1_vt (VOP3Mods src1_vt:$src1, i32:$src1_modifiers)))), 319 (inst i32:$src0_modifiers, src0_vt:$src0, 320 i32:$src1_modifiers, src1_vt:$src1, $clamp, $omods) 321>; 322 323multiclass GISelVop2IntrPat < 324 SDPatternOperator node, Instruction inst, 325 ValueType dst_vt, ValueType src_vt = dst_vt> { 326 327 def : GISelVop2Pat <node, inst, dst_vt, src_vt>; 328 329 // FIXME: Intrinsics aren't marked as commutable, so we need to add an explicit 330 // pattern to handle commuting. This is another reason why legalizing to a 331 // generic machine instruction may be better that matching the intrinsic 332 // directly. 333 def : GISelVop2CommutePat <node, inst, dst_vt, src_vt>; 334} 335 336// Since GlobalISel is more flexible then SelectionDAG, I think we can get 337// away with adding patterns for integer types and not legalizing all 338// loads and stores to vector types. This should help simplify the load/store 339// legalization. 340foreach Ty = [i64, p0, p1, p4] in { 341 defm : SMRD_Pattern <"S_LOAD_DWORDX2", Ty>; 342} 343 344def gi_as_i32timm : GICustomOperandRenderer<"renderTruncTImm">, 345 GISDNodeXFormEquiv<as_i32timm>; 346 347def gi_as_i16timm : GICustomOperandRenderer<"renderTruncTImm">, 348 GISDNodeXFormEquiv<as_i16timm>; 349 350def gi_as_i8timm : GICustomOperandRenderer<"renderTruncTImm">, 351 GISDNodeXFormEquiv<as_i8timm>; 352 353def gi_as_i1timm : GICustomOperandRenderer<"renderTruncTImm">, 354 GISDNodeXFormEquiv<as_i1timm>; 355 356def gi_NegateImm : GICustomOperandRenderer<"renderNegateImm">, 357 GISDNodeXFormEquiv<NegateImm>; 358 359def gi_bitcast_fpimm_to_i32 : GICustomOperandRenderer<"renderBitcastImm">, 360 GISDNodeXFormEquiv<bitcast_fpimm_to_i32>; 361 362def gi_IMMPopCount : GICustomOperandRenderer<"renderPopcntImm">, 363 GISDNodeXFormEquiv<IMMPopCount>; 364 365def gi_extract_cpol : GICustomOperandRenderer<"renderExtractCPol">, 366 GISDNodeXFormEquiv<extract_cpol>; 367 368def gi_extract_swz : GICustomOperandRenderer<"renderExtractSWZ">, 369 GISDNodeXFormEquiv<extract_swz>; 370 371def gi_set_glc : GICustomOperandRenderer<"renderSetGLC">, 372 GISDNodeXFormEquiv<set_glc>; 373 374def gi_frameindex_to_targetframeindex : GICustomOperandRenderer<"renderFrameIndex">, 375 GISDNodeXFormEquiv<frameindex_to_targetframeindex>; 376