1//=- AMDGPUCombine.td - Define AMDGPU Combine Rules ----------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9include "llvm/Target/GlobalISel/Combine.td" 10 11// TODO: This really belongs after legalization after scalarization. 12// TODO: GICombineRules should accept subtarget predicates 13 14def fmin_fmax_legacy_matchdata : GIDefMatchData<"AMDGPUPostLegalizerCombinerHelper::FMinFMaxLegacyInfo">; 15 16def fcmp_select_to_fmin_fmax_legacy : GICombineRule< 17 (defs root:$select, fmin_fmax_legacy_matchdata:$matchinfo), 18 (match (wip_match_opcode G_SELECT):$select, 19 [{ return PostLegalizerHelper.matchFMinFMaxLegacy(*${select}, ${matchinfo}); }]), 20 (apply [{ PostLegalizerHelper.applySelectFCmpToFMinToFMaxLegacy(*${select}, ${matchinfo}); }])>; 21 22 23def uchar_to_float : GICombineRule< 24 (defs root:$itofp), 25 (match (wip_match_opcode G_UITOFP, G_SITOFP):$itofp, 26 [{ return PostLegalizerHelper.matchUCharToFloat(*${itofp}); }]), 27 (apply [{ PostLegalizerHelper.applyUCharToFloat(*${itofp}); }])>; 28 29def cvt_f32_ubyteN_matchdata : GIDefMatchData<"AMDGPUPostLegalizerCombinerHelper::CvtF32UByteMatchInfo">; 30 31def cvt_f32_ubyteN : GICombineRule< 32 (defs root:$cvt_f32_ubyteN, cvt_f32_ubyteN_matchdata:$matchinfo), 33 (match (wip_match_opcode G_AMDGPU_CVT_F32_UBYTE0, 34 G_AMDGPU_CVT_F32_UBYTE1, 35 G_AMDGPU_CVT_F32_UBYTE2, 36 G_AMDGPU_CVT_F32_UBYTE3):$cvt_f32_ubyteN, 37 [{ return PostLegalizerHelper.matchCvtF32UByteN(*${cvt_f32_ubyteN}, ${matchinfo}); }]), 38 (apply [{ PostLegalizerHelper.applyCvtF32UByteN(*${cvt_f32_ubyteN}, ${matchinfo}); }])>; 39 40def clamp_i64_to_i16_matchdata : GIDefMatchData<"AMDGPUPreLegalizerCombinerHelper::ClampI64ToI16MatchInfo">; 41 42def clamp_i64_to_i16 : GICombineRule< 43 (defs root:$clamp_i64_to_i16, clamp_i64_to_i16_matchdata:$matchinfo), 44 (match (wip_match_opcode G_TRUNC):$clamp_i64_to_i16, 45 [{ return PreLegalizerHelper.matchClampI64ToI16(*${clamp_i64_to_i16}, MRI, *MF, ${matchinfo}); }]), 46 (apply [{ PreLegalizerHelper.applyClampI64ToI16(*${clamp_i64_to_i16}, ${matchinfo}); }])>; 47 48def med3_matchdata : GIDefMatchData<"AMDGPURegBankCombinerHelper::Med3MatchInfo">; 49 50def int_minmax_to_med3 : GICombineRule< 51 (defs root:$min_or_max, med3_matchdata:$matchinfo), 52 (match (wip_match_opcode G_SMAX, 53 G_SMIN, 54 G_UMAX, 55 G_UMIN):$min_or_max, 56 [{ return RegBankHelper.matchIntMinMaxToMed3(*${min_or_max}, ${matchinfo}); }]), 57 (apply [{ RegBankHelper.applyMed3(*${min_or_max}, ${matchinfo}); }])>; 58 59def remove_fcanonicalize_matchinfo : GIDefMatchData<"Register">; 60 61def remove_fcanonicalize : GICombineRule< 62 (defs root:$fcanonicalize, remove_fcanonicalize_matchinfo:$matchinfo), 63 (match (wip_match_opcode G_FCANONICALIZE):$fcanonicalize, 64 [{ return PostLegalizerHelper.matchRemoveFcanonicalize(*${fcanonicalize}, ${matchinfo}); }]), 65 (apply [{ Helper.replaceSingleDefInstWithReg(*${fcanonicalize}, ${matchinfo}); }])>; 66 67def foldable_fneg_matchdata : GIDefMatchData<"MachineInstr *">; 68 69def foldable_fneg : GICombineRule< 70 (defs root:$ffn, foldable_fneg_matchdata:$matchinfo), 71 (match (wip_match_opcode G_FNEG):$ffn, 72 [{ return Helper.matchFoldableFneg(*${ffn}, ${matchinfo}); }]), 73 (apply [{ Helper.applyFoldableFneg(*${ffn}, ${matchinfo}); }])>; 74 75// Combines which should only apply on SI/VI 76def gfx6gfx7_combines : GICombineGroup<[fcmp_select_to_fmin_fmax_legacy]>; 77 78def AMDGPUPreLegalizerCombinerHelper: GICombinerHelper< 79 "AMDGPUGenPreLegalizerCombinerHelper", 80 [all_combines, clamp_i64_to_i16, foldable_fneg]> { 81 let DisableRuleOption = "amdgpuprelegalizercombiner-disable-rule"; 82 let StateClass = "AMDGPUPreLegalizerCombinerHelperState"; 83 let AdditionalArguments = []; 84} 85 86def AMDGPUPostLegalizerCombinerHelper: GICombinerHelper< 87 "AMDGPUGenPostLegalizerCombinerHelper", 88 [all_combines, gfx6gfx7_combines, 89 uchar_to_float, cvt_f32_ubyteN, remove_fcanonicalize, foldable_fneg]> { 90 let DisableRuleOption = "amdgpupostlegalizercombiner-disable-rule"; 91 let StateClass = "AMDGPUPostLegalizerCombinerHelperState"; 92 let AdditionalArguments = []; 93} 94 95def AMDGPURegBankCombinerHelper : GICombinerHelper< 96 "AMDGPUGenRegBankCombinerHelper", [zext_trunc_fold, int_minmax_to_med3, ptr_add_immed_chain]> { 97 let DisableRuleOption = "amdgpuregbankcombiner-disable-rule"; 98 let StateClass = "AMDGPURegBankCombinerHelperState"; 99 let AdditionalArguments = []; 100} 101