xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td (revision 77013d11e6483b970af25e13c9b892075742f7e5) 
1//===---- AMDCallingConv.td - Calling Conventions for Radeon GPUs ---------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This describes the calling conventions for the AMD Radeon GPUs.
10//
11//===----------------------------------------------------------------------===//
12
13// Inversion of CCIfInReg
14class CCIfNotInReg<CCAction A> : CCIf<"!ArgFlags.isInReg()", A> {}
15class CCIfExtend<CCAction A>
16  : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
17
18// Calling convention for SI
19def CC_SI_Gfx : CallingConv<[
20  // 0-3 are reserved for the stack buffer descriptor
21  // 30-31 are reserved for the return address
22  // 32 is reserved for the stack pointer
23  CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
24    SGPR4, SGPR5, SGPR6, SGPR7,
25    SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
26    SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23,
27    SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29,
28  ]>>>,
29
30  CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
31    VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
32    VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
33    VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
34    VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31
35  ]>>>,
36
37  CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1], CCAssignToStack<4, 4>>,
38  CCIfType<[i64, f64, v2i32, v2f32], CCAssignToStack<8, 4>>,
39  CCIfType<[v3i32, v3f32], CCAssignToStack<12, 4>>,
40  CCIfType<[v4i32, v4f32, v2i64, v2f64], CCAssignToStack<16, 4>>,
41  CCIfType<[v5i32, v5f32], CCAssignToStack<20, 4>>,
42  CCIfType<[v8i32, v8f32], CCAssignToStack<32, 4>>,
43  CCIfType<[v16i32, v16f32], CCAssignToStack<64, 4>>
44]>;
45
46def RetCC_SI_Gfx : CallingConv<[
47  // 0-3 are reserved for the stack buffer descriptor
48  // 32 is reserved for the stack pointer
49  CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
50    SGPR4, SGPR5, SGPR6, SGPR7,
51    SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
52    SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23,
53    SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31,
54    SGPR33, SGPR34, SGPR35, SGPR36, SGPR37, SGPR38, SGPR39,
55    SGPR40, SGPR41, SGPR42, SGPR43
56  ]>>>,
57
58  CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
59    VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
60    VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
61    VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
62    VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31,
63    VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39,
64    VGPR40, VGPR41, VGPR42, VGPR43, VGPR44, VGPR45, VGPR46, VGPR47,
65    VGPR48, VGPR49, VGPR50, VGPR51, VGPR52, VGPR53, VGPR54, VGPR55,
66    VGPR56, VGPR57, VGPR58, VGPR59, VGPR60, VGPR61, VGPR62, VGPR63,
67    VGPR64, VGPR65, VGPR66, VGPR67, VGPR68, VGPR69, VGPR70, VGPR71,
68    VGPR72, VGPR73, VGPR74, VGPR75, VGPR76, VGPR77, VGPR78, VGPR79,
69    VGPR80, VGPR81, VGPR82, VGPR83, VGPR84, VGPR85, VGPR86, VGPR87,
70    VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95,
71    VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103,
72    VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111,
73    VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119,
74    VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127,
75    VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135
76  ]>>>,
77
78  CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1], CCAssignToStack<4, 4>>,
79  CCIfType<[i64, f64, v2i32, v2f32], CCAssignToStack<8, 4>>,
80  CCIfType<[v3i32, v3f32], CCAssignToStack<12, 4>>,
81  CCIfType<[v4i32, v4f32, v2i64, v2f64], CCAssignToStack<16, 4>>,
82  CCIfType<[v5i32, v5f32], CCAssignToStack<20, 4>>,
83  CCIfType<[v8i32, v8f32], CCAssignToStack<32, 4>>,
84  CCIfType<[v16i32, v16f32], CCAssignToStack<64, 4>>
85]>;
86
87def CC_SI_SHADER : CallingConv<[
88
89  CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
90    SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
91    SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
92    SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23,
93    SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31,
94    SGPR32, SGPR33, SGPR34, SGPR35, SGPR36, SGPR37, SGPR38, SGPR39,
95    SGPR40, SGPR41, SGPR42, SGPR43
96  ]>>>,
97
98  // 32*4 + 4 is the minimum for a fetch shader consumer with 32 inputs.
99  CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
100    VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
101    VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
102    VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
103    VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31,
104    VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39,
105    VGPR40, VGPR41, VGPR42, VGPR43, VGPR44, VGPR45, VGPR46, VGPR47,
106    VGPR48, VGPR49, VGPR50, VGPR51, VGPR52, VGPR53, VGPR54, VGPR55,
107    VGPR56, VGPR57, VGPR58, VGPR59, VGPR60, VGPR61, VGPR62, VGPR63,
108    VGPR64, VGPR65, VGPR66, VGPR67, VGPR68, VGPR69, VGPR70, VGPR71,
109    VGPR72, VGPR73, VGPR74, VGPR75, VGPR76, VGPR77, VGPR78, VGPR79,
110    VGPR80, VGPR81, VGPR82, VGPR83, VGPR84, VGPR85, VGPR86, VGPR87,
111    VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95,
112    VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103,
113    VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111,
114    VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119,
115    VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127,
116    VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135
117  ]>>>
118]>;
119
120def RetCC_SI_Shader : CallingConv<[
121  CCIfType<[i32, i16] , CCAssignToReg<[
122    SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
123    SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
124    SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23,
125    SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31,
126    SGPR32, SGPR33, SGPR34, SGPR35, SGPR36, SGPR37, SGPR38, SGPR39,
127    SGPR40, SGPR41, SGPR42, SGPR43
128  ]>>,
129
130  // 32*4 + 4 is the minimum for a fetch shader with 32 outputs.
131  CCIfType<[f32, f16, v2f16] , CCAssignToReg<[
132    VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
133    VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
134    VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
135    VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31,
136    VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39,
137    VGPR40, VGPR41, VGPR42, VGPR43, VGPR44, VGPR45, VGPR46, VGPR47,
138    VGPR48, VGPR49, VGPR50, VGPR51, VGPR52, VGPR53, VGPR54, VGPR55,
139    VGPR56, VGPR57, VGPR58, VGPR59, VGPR60, VGPR61, VGPR62, VGPR63,
140    VGPR64, VGPR65, VGPR66, VGPR67, VGPR68, VGPR69, VGPR70, VGPR71,
141    VGPR72, VGPR73, VGPR74, VGPR75, VGPR76, VGPR77, VGPR78, VGPR79,
142    VGPR80, VGPR81, VGPR82, VGPR83, VGPR84, VGPR85, VGPR86, VGPR87,
143    VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95,
144    VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103,
145    VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111,
146    VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119,
147    VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127,
148    VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135
149  ]>>
150]>;
151
152def CSR_AMDGPU_VGPRs_24_255 : CalleeSavedRegs<
153  (sequence "VGPR%u", 24, 255)
154>;
155
156def CSR_AMDGPU_VGPRs_32_255 : CalleeSavedRegs<
157  (sequence "VGPR%u", 32, 255)
158>;
159
160def CSR_AMDGPU_VGPRs : CalleeSavedRegs<
161  // The CSRs & scratch-registers are interleaved at a split boundary of 8.
162  (add (sequence "VGPR%u", 40, 47),
163    (sequence "VGPR%u", 56, 63),
164    (sequence "VGPR%u", 72, 79),
165    (sequence "VGPR%u", 88, 95),
166    (sequence "VGPR%u", 104, 111),
167    (sequence "VGPR%u", 120, 127),
168    (sequence "VGPR%u", 136, 143),
169    (sequence "VGPR%u", 152, 159),
170    (sequence "VGPR%u", 168, 175),
171    (sequence "VGPR%u", 184, 191),
172    (sequence "VGPR%u", 200, 207),
173    (sequence "VGPR%u", 216, 223),
174    (sequence "VGPR%u", 232, 239),
175    (sequence "VGPR%u", 248, 255))
176>;
177
178def CSR_AMDGPU_SGPRs_32_105 : CalleeSavedRegs<
179  (sequence "SGPR%u", 32, 105)
180>;
181
182// Just to get the regmask, not for calling convention purposes.
183def CSR_AMDGPU_AllVGPRs : CalleeSavedRegs<
184  (sequence "VGPR%u", 0, 255)
185>;
186
187// Just to get the regmask, not for calling convention purposes.
188def CSR_AMDGPU_AllAllocatableSRegs : CalleeSavedRegs<
189  (add (sequence "SGPR%u", 0, 105), VCC_LO, VCC_HI)
190>;
191
192def CSR_AMDGPU_HighRegs : CalleeSavedRegs<
193  (add CSR_AMDGPU_VGPRs, CSR_AMDGPU_SGPRs_32_105)
194>;
195
196def CSR_AMDGPU_NoRegs : CalleeSavedRegs<(add)>;
197
198// Calling convention for leaf functions
199def CC_AMDGPU_Func : CallingConv<[
200  CCIfByVal<CCPassByVal<4, 4>>,
201  CCIfType<[i1], CCPromoteToType<i32>>,
202  CCIfType<[i8, i16], CCIfExtend<CCPromoteToType<i32>>>,
203  CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1], CCAssignToReg<[
204    VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
205    VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
206    VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
207    VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31]>>,
208  CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1], CCAssignToStack<4, 4>>,
209  CCIfType<[i64, f64, v2i32, v2f32], CCAssignToStack<8, 4>>,
210  CCIfType<[v3i32, v3f32], CCAssignToStack<12, 4>>,
211  CCIfType<[v4i32, v4f32, v2i64, v2f64], CCAssignToStack<16, 4>>,
212  CCIfType<[v5i32, v5f32], CCAssignToStack<20, 4>>,
213  CCIfType<[v8i32, v8f32], CCAssignToStack<32, 4>>,
214  CCIfType<[v16i32, v16f32], CCAssignToStack<64, 4>>
215]>;
216
217// Calling convention for leaf functions
218def RetCC_AMDGPU_Func : CallingConv<[
219  CCIfType<[i1], CCPromoteToType<i32>>,
220  CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>,
221  CCIfType<[i32, f32, i16, f16, v2i16, v2f16], CCAssignToReg<[
222    VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
223    VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
224    VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
225    VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31]>>,
226]>;
227
228def CC_AMDGPU : CallingConv<[
229   CCIf<"static_cast<const GCNSubtarget&>"
230         "(State.getMachineFunction().getSubtarget()).getGeneration() >= "
231           "AMDGPUSubtarget::SOUTHERN_ISLANDS",
232        CCDelegateTo<CC_SI_SHADER>>,
233   CCIf<"static_cast<const GCNSubtarget&>"
234         "(State.getMachineFunction().getSubtarget()).getGeneration() >= "
235           "AMDGPUSubtarget::SOUTHERN_ISLANDS && State.getCallingConv() == CallingConv::C",
236        CCDelegateTo<CC_AMDGPU_Func>>
237]>;
238