1*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric 9*0b57cec5SDimitry Andric #include "AMDGPU.h" 10*0b57cec5SDimitry Andric #include "AMDGPUArgumentUsageInfo.h" 11*0b57cec5SDimitry Andric #include "SIRegisterInfo.h" 12*0b57cec5SDimitry Andric #include "llvm/Support/NativeFormatting.h" 13*0b57cec5SDimitry Andric #include "llvm/Support/raw_ostream.h" 14*0b57cec5SDimitry Andric 15*0b57cec5SDimitry Andric using namespace llvm; 16*0b57cec5SDimitry Andric 17*0b57cec5SDimitry Andric #define DEBUG_TYPE "amdgpu-argument-reg-usage-info" 18*0b57cec5SDimitry Andric 19*0b57cec5SDimitry Andric INITIALIZE_PASS(AMDGPUArgumentUsageInfo, DEBUG_TYPE, 20*0b57cec5SDimitry Andric "Argument Register Usage Information Storage", false, true) 21*0b57cec5SDimitry Andric 22*0b57cec5SDimitry Andric void ArgDescriptor::print(raw_ostream &OS, 23*0b57cec5SDimitry Andric const TargetRegisterInfo *TRI) const { 24*0b57cec5SDimitry Andric if (!isSet()) { 25*0b57cec5SDimitry Andric OS << "<not set>\n"; 26*0b57cec5SDimitry Andric return; 27*0b57cec5SDimitry Andric } 28*0b57cec5SDimitry Andric 29*0b57cec5SDimitry Andric if (isRegister()) 30*0b57cec5SDimitry Andric OS << "Reg " << printReg(getRegister(), TRI); 31*0b57cec5SDimitry Andric else 32*0b57cec5SDimitry Andric OS << "Stack offset " << getStackOffset(); 33*0b57cec5SDimitry Andric 34*0b57cec5SDimitry Andric if (isMasked()) { 35*0b57cec5SDimitry Andric OS << " & "; 36*0b57cec5SDimitry Andric llvm::write_hex(OS, Mask, llvm::HexPrintStyle::PrefixLower); 37*0b57cec5SDimitry Andric } 38*0b57cec5SDimitry Andric 39*0b57cec5SDimitry Andric OS << '\n'; 40*0b57cec5SDimitry Andric } 41*0b57cec5SDimitry Andric 42*0b57cec5SDimitry Andric char AMDGPUArgumentUsageInfo::ID = 0; 43*0b57cec5SDimitry Andric 44*0b57cec5SDimitry Andric const AMDGPUFunctionArgInfo AMDGPUArgumentUsageInfo::ExternFunctionInfo{}; 45*0b57cec5SDimitry Andric 46*0b57cec5SDimitry Andric bool AMDGPUArgumentUsageInfo::doInitialization(Module &M) { 47*0b57cec5SDimitry Andric return false; 48*0b57cec5SDimitry Andric } 49*0b57cec5SDimitry Andric 50*0b57cec5SDimitry Andric bool AMDGPUArgumentUsageInfo::doFinalization(Module &M) { 51*0b57cec5SDimitry Andric ArgInfoMap.clear(); 52*0b57cec5SDimitry Andric return false; 53*0b57cec5SDimitry Andric } 54*0b57cec5SDimitry Andric 55*0b57cec5SDimitry Andric void AMDGPUArgumentUsageInfo::print(raw_ostream &OS, const Module *M) const { 56*0b57cec5SDimitry Andric for (const auto &FI : ArgInfoMap) { 57*0b57cec5SDimitry Andric OS << "Arguments for " << FI.first->getName() << '\n' 58*0b57cec5SDimitry Andric << " PrivateSegmentBuffer: " << FI.second.PrivateSegmentBuffer 59*0b57cec5SDimitry Andric << " DispatchPtr: " << FI.second.DispatchPtr 60*0b57cec5SDimitry Andric << " QueuePtr: " << FI.second.QueuePtr 61*0b57cec5SDimitry Andric << " KernargSegmentPtr: " << FI.second.KernargSegmentPtr 62*0b57cec5SDimitry Andric << " DispatchID: " << FI.second.DispatchID 63*0b57cec5SDimitry Andric << " FlatScratchInit: " << FI.second.FlatScratchInit 64*0b57cec5SDimitry Andric << " PrivateSegmentSize: " << FI.second.PrivateSegmentSize 65*0b57cec5SDimitry Andric << " WorkGroupIDX: " << FI.second.WorkGroupIDX 66*0b57cec5SDimitry Andric << " WorkGroupIDY: " << FI.second.WorkGroupIDY 67*0b57cec5SDimitry Andric << " WorkGroupIDZ: " << FI.second.WorkGroupIDZ 68*0b57cec5SDimitry Andric << " WorkGroupInfo: " << FI.second.WorkGroupInfo 69*0b57cec5SDimitry Andric << " PrivateSegmentWaveByteOffset: " 70*0b57cec5SDimitry Andric << FI.second.PrivateSegmentWaveByteOffset 71*0b57cec5SDimitry Andric << " ImplicitBufferPtr: " << FI.second.ImplicitBufferPtr 72*0b57cec5SDimitry Andric << " ImplicitArgPtr: " << FI.second.ImplicitArgPtr 73*0b57cec5SDimitry Andric << " WorkItemIDX " << FI.second.WorkItemIDX 74*0b57cec5SDimitry Andric << " WorkItemIDY " << FI.second.WorkItemIDY 75*0b57cec5SDimitry Andric << " WorkItemIDZ " << FI.second.WorkItemIDZ 76*0b57cec5SDimitry Andric << '\n'; 77*0b57cec5SDimitry Andric } 78*0b57cec5SDimitry Andric } 79*0b57cec5SDimitry Andric 80*0b57cec5SDimitry Andric std::pair<const ArgDescriptor *, const TargetRegisterClass *> 81*0b57cec5SDimitry Andric AMDGPUFunctionArgInfo::getPreloadedValue( 82*0b57cec5SDimitry Andric AMDGPUFunctionArgInfo::PreloadedValue Value) const { 83*0b57cec5SDimitry Andric switch (Value) { 84*0b57cec5SDimitry Andric case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_BUFFER: { 85*0b57cec5SDimitry Andric return std::make_pair( 86*0b57cec5SDimitry Andric PrivateSegmentBuffer ? &PrivateSegmentBuffer : nullptr, 87*0b57cec5SDimitry Andric &AMDGPU::SGPR_128RegClass); 88*0b57cec5SDimitry Andric } 89*0b57cec5SDimitry Andric case AMDGPUFunctionArgInfo::IMPLICIT_BUFFER_PTR: 90*0b57cec5SDimitry Andric return std::make_pair(ImplicitBufferPtr ? &ImplicitBufferPtr : nullptr, 91*0b57cec5SDimitry Andric &AMDGPU::SGPR_64RegClass); 92*0b57cec5SDimitry Andric case AMDGPUFunctionArgInfo::WORKGROUP_ID_X: 93*0b57cec5SDimitry Andric return std::make_pair(WorkGroupIDX ? &WorkGroupIDX : nullptr, 94*0b57cec5SDimitry Andric &AMDGPU::SGPR_32RegClass); 95*0b57cec5SDimitry Andric 96*0b57cec5SDimitry Andric case AMDGPUFunctionArgInfo::WORKGROUP_ID_Y: 97*0b57cec5SDimitry Andric return std::make_pair(WorkGroupIDY ? &WorkGroupIDY : nullptr, 98*0b57cec5SDimitry Andric &AMDGPU::SGPR_32RegClass); 99*0b57cec5SDimitry Andric case AMDGPUFunctionArgInfo::WORKGROUP_ID_Z: 100*0b57cec5SDimitry Andric return std::make_pair(WorkGroupIDZ ? &WorkGroupIDZ : nullptr, 101*0b57cec5SDimitry Andric &AMDGPU::SGPR_32RegClass); 102*0b57cec5SDimitry Andric case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET: 103*0b57cec5SDimitry Andric return std::make_pair( 104*0b57cec5SDimitry Andric PrivateSegmentWaveByteOffset ? &PrivateSegmentWaveByteOffset : nullptr, 105*0b57cec5SDimitry Andric &AMDGPU::SGPR_32RegClass); 106*0b57cec5SDimitry Andric case AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR: 107*0b57cec5SDimitry Andric return std::make_pair(KernargSegmentPtr ? &KernargSegmentPtr : nullptr, 108*0b57cec5SDimitry Andric &AMDGPU::SGPR_64RegClass); 109*0b57cec5SDimitry Andric case AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR: 110*0b57cec5SDimitry Andric return std::make_pair(ImplicitArgPtr ? &ImplicitArgPtr : nullptr, 111*0b57cec5SDimitry Andric &AMDGPU::SGPR_64RegClass); 112*0b57cec5SDimitry Andric case AMDGPUFunctionArgInfo::DISPATCH_ID: 113*0b57cec5SDimitry Andric return std::make_pair(DispatchID ? &DispatchID : nullptr, 114*0b57cec5SDimitry Andric &AMDGPU::SGPR_64RegClass); 115*0b57cec5SDimitry Andric case AMDGPUFunctionArgInfo::FLAT_SCRATCH_INIT: 116*0b57cec5SDimitry Andric return std::make_pair(FlatScratchInit ? &FlatScratchInit : nullptr, 117*0b57cec5SDimitry Andric &AMDGPU::SGPR_64RegClass); 118*0b57cec5SDimitry Andric case AMDGPUFunctionArgInfo::DISPATCH_PTR: 119*0b57cec5SDimitry Andric return std::make_pair(DispatchPtr ? &DispatchPtr : nullptr, 120*0b57cec5SDimitry Andric &AMDGPU::SGPR_64RegClass); 121*0b57cec5SDimitry Andric case AMDGPUFunctionArgInfo::QUEUE_PTR: 122*0b57cec5SDimitry Andric return std::make_pair(QueuePtr ? &QueuePtr : nullptr, 123*0b57cec5SDimitry Andric &AMDGPU::SGPR_64RegClass); 124*0b57cec5SDimitry Andric case AMDGPUFunctionArgInfo::WORKITEM_ID_X: 125*0b57cec5SDimitry Andric return std::make_pair(WorkItemIDX ? &WorkItemIDX : nullptr, 126*0b57cec5SDimitry Andric &AMDGPU::VGPR_32RegClass); 127*0b57cec5SDimitry Andric case AMDGPUFunctionArgInfo::WORKITEM_ID_Y: 128*0b57cec5SDimitry Andric return std::make_pair(WorkItemIDY ? &WorkItemIDY : nullptr, 129*0b57cec5SDimitry Andric &AMDGPU::VGPR_32RegClass); 130*0b57cec5SDimitry Andric case AMDGPUFunctionArgInfo::WORKITEM_ID_Z: 131*0b57cec5SDimitry Andric return std::make_pair(WorkItemIDZ ? &WorkItemIDZ : nullptr, 132*0b57cec5SDimitry Andric &AMDGPU::VGPR_32RegClass); 133*0b57cec5SDimitry Andric } 134*0b57cec5SDimitry Andric llvm_unreachable("unexpected preloaded value type"); 135*0b57cec5SDimitry Andric } 136