xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPU.td (revision 3e8eb5c7f4909209c042403ddee340b2ee7003a5) 
1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===------------------------------------------------------------===//
8
9include "llvm/TableGen/SearchableTable.td"
10include "llvm/Target/Target.td"
11include "AMDGPUFeatures.td"
12
13def p0 : PtrValueType<i64, 0>;
14def p1 : PtrValueType<i64, 1>;
15def p2 : PtrValueType<i32, 2>;
16def p3 : PtrValueType<i32, 3>;
17def p4 : PtrValueType<i64, 4>;
18def p5 : PtrValueType<i32, 5>;
19def p6 : PtrValueType<i32, 6>;
20
21class BoolToList<bit Value> {
22  list<int> ret = !if(Value, [1]<int>, []<int>);
23}
24
25//===------------------------------------------------------------===//
26// Subtarget Features (device properties)
27//===------------------------------------------------------------===//
28
29def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
30  "FastFMAF32",
31  "true",
32  "Assuming f32 fma is at least as fast as mul + add"
33>;
34
35def FeatureFastDenormalF32 : SubtargetFeature<"fast-denormal-f32",
36  "FastDenormalF32",
37  "true",
38  "Enabling denormals does not cause f32 instructions to run at f64 rates"
39>;
40
41def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
42  "MIMG_R128",
43  "true",
44  "Support 128-bit texture resources"
45>;
46
47def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
48  "HalfRate64Ops",
49  "true",
50  "Most fp64 instructions are half rate instead of quarter"
51>;
52
53def FullRate64Ops : SubtargetFeature<"full-rate-64-ops",
54  "FullRate64Ops",
55  "true",
56  "Most fp64 instructions are full rate"
57>;
58
59def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
60  "FlatAddressSpace",
61  "true",
62  "Support flat address space"
63>;
64
65def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
66  "FlatInstOffsets",
67  "true",
68  "Flat instructions have immediate offset addressing mode"
69>;
70
71def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
72  "FlatGlobalInsts",
73  "true",
74  "Have global_* flat memory instructions"
75>;
76
77def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
78  "FlatScratchInsts",
79  "true",
80  "Have scratch_* flat memory instructions"
81>;
82
83def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
84  "ScalarFlatScratchInsts",
85  "true",
86  "Have s_scratch_* flat memory instructions"
87>;
88
89def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
90  "AddNoCarryInsts",
91  "true",
92  "Have VALU add/sub instructions without carry out"
93>;
94
95def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
96  "UnalignedBufferAccess",
97  "true",
98  "Hardware supports unaligned global loads and stores"
99>;
100
101def FeatureTrapHandler: SubtargetFeature<"trap-handler",
102  "TrapHandler",
103  "true",
104  "Trap handler support"
105>;
106
107def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
108  "UnalignedScratchAccess",
109  "true",
110  "Support unaligned scratch loads and stores"
111>;
112
113def FeatureUnalignedDSAccess : SubtargetFeature<"unaligned-ds-access",
114  "UnalignedDSAccess",
115  "true",
116  "Hardware supports unaligned local and region loads and stores"
117>;
118
119def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
120  "HasApertureRegs",
121  "true",
122  "Has Memory Aperture Base and Size Registers"
123>;
124
125def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
126  "HasMadMixInsts",
127  "true",
128  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
129>;
130
131def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
132  "HasFmaMixInsts",
133  "true",
134  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
135>;
136
137def FeatureSupportsXNACK : SubtargetFeature<"xnack-support",
138  "SupportsXNACK",
139  "true",
140  "Hardware supports XNACK"
141>;
142
143// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
144// XNACK. The current default kernel driver setting is:
145// - graphics ring: XNACK disabled
146// - compute ring: XNACK enabled
147//
148// If XNACK is enabled, the VMEM latency can be worse.
149// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
150def FeatureXNACK : SubtargetFeature<"xnack",
151  "EnableXNACK",
152  "true",
153  "Enable XNACK support"
154>;
155
156def FeatureTgSplit : SubtargetFeature<"tgsplit",
157  "EnableTgSplit",
158  "true",
159  "Enable threadgroup split execution"
160>;
161
162def FeatureCuMode : SubtargetFeature<"cumode",
163  "EnableCuMode",
164  "true",
165  "Enable CU wavefront execution mode"
166>;
167
168def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
169  "SGPRInitBug",
170  "true",
171  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
172>;
173
174def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
175  "LDSMisalignedBug",
176  "true",
177  "Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode"
178>;
179
180def FeatureMFMAInlineLiteralBug : SubtargetFeature<"mfma-inline-literal-bug",
181  "HasMFMAInlineLiteralBug",
182  "true",
183  "MFMA cannot use inline literal as SrcC"
184>;
185
186def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
187  "HasVcmpxPermlaneHazard",
188  "true",
189  "TODO: describe me"
190>;
191
192def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
193  "HasVMEMtoScalarWriteHazard",
194  "true",
195  "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
196>;
197
198def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
199  "HasSMEMtoVectorWriteHazard",
200  "true",
201  "s_load_dword followed by v_cmp page faults"
202>;
203
204def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
205  "HasInstFwdPrefetchBug",
206  "true",
207  "S_INST_PREFETCH instruction causes shader to hang"
208>;
209
210def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
211  "HasVcmpxExecWARHazard",
212  "true",
213  "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
214>;
215
216def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
217  "HasLdsBranchVmemWARHazard",
218  "true",
219  "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
220>;
221
222def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
223  "HasNSAtoVMEMBug",
224  "true",
225  "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
226>;
227
228def FeatureNSAClauseBug : SubtargetFeature<"nsa-clause-bug",
229  "HasNSAClauseBug",
230  "true",
231  "MIMG-NSA in a hard clause has unpredictable results on GFX10.1"
232>;
233
234def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
235  "HasFlatSegmentOffsetBug",
236  "true",
237  "GFX10 bug where inst_offset is ignored when flat instructions access global memory"
238>;
239
240def FeatureNegativeScratchOffsetBug : SubtargetFeature<"negative-scratch-offset-bug",
241  "NegativeScratchOffsetBug",
242  "true",
243  "Negative immediate offsets in scratch instructions with an SGPR offset page fault on GFX9"
244>;
245
246def FeatureNegativeUnalignedScratchOffsetBug : SubtargetFeature<"negative-unaligned-scratch-offset-bug",
247  "NegativeUnalignedScratchOffsetBug",
248  "true",
249  "Scratch instructions with a VGPR offset and a negative immediate offset that is not a multiple of 4 read wrong memory on GFX10"
250>;
251
252def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
253  "HasOffset3fBug",
254  "true",
255  "Branch offset of 3f hardware bug"
256>;
257
258def FeatureImageStoreD16Bug : SubtargetFeature<"image-store-d16-bug",
259  "HasImageStoreD16Bug",
260  "true",
261  "Image Store D16 hardware bug"
262>;
263
264def FeatureImageGather4D16Bug : SubtargetFeature<"image-gather4-d16-bug",
265  "HasImageGather4D16Bug",
266  "true",
267  "Image Gather4 D16 hardware bug"
268>;
269
270class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
271  "ldsbankcount"#Value,
272  "LDSBankCount",
273  !cast<string>(Value),
274  "The number of LDS banks per compute unit."
275>;
276
277def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
278def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
279
280def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
281  "GCN3Encoding",
282  "true",
283  "Encoding format for VI"
284>;
285
286def FeatureCIInsts : SubtargetFeature<"ci-insts",
287  "CIInsts",
288  "true",
289  "Additional instructions for CI+"
290>;
291
292def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
293  "GFX8Insts",
294  "true",
295  "Additional instructions for GFX8+"
296>;
297
298def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
299  "GFX9Insts",
300  "true",
301  "Additional instructions for GFX9+"
302>;
303
304def FeatureGFX90AInsts : SubtargetFeature<"gfx90a-insts",
305  "GFX90AInsts",
306  "true",
307  "Additional instructions for GFX90A+"
308>;
309
310def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
311  "GFX10Insts",
312  "true",
313  "Additional instructions for GFX10+"
314>;
315
316def FeatureGFX10_3Insts : SubtargetFeature<"gfx10-3-insts",
317  "GFX10_3Insts",
318  "true",
319  "Additional instructions for GFX10.3"
320>;
321
322def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
323  "GFX7GFX8GFX9Insts",
324  "true",
325  "Instructions shared in GFX7, GFX8, GFX9"
326>;
327
328def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
329  "HasSMemRealTime",
330  "true",
331  "Has s_memrealtime instruction"
332>;
333
334def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
335  "HasInv2PiInlineImm",
336  "true",
337  "Has 1 / (2 * pi) as inline immediate"
338>;
339
340def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
341  "Has16BitInsts",
342  "true",
343  "Has i16/f16 instructions"
344>;
345
346def FeatureVOP3P : SubtargetFeature<"vop3p",
347  "HasVOP3PInsts",
348  "true",
349  "Has VOP3P packed instructions"
350>;
351
352def FeatureMovrel : SubtargetFeature<"movrel",
353  "HasMovrel",
354  "true",
355  "Has v_movrel*_b32 instructions"
356>;
357
358def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
359  "HasVGPRIndexMode",
360  "true",
361  "Has VGPR mode register indexing"
362>;
363
364def FeatureScalarStores : SubtargetFeature<"scalar-stores",
365  "HasScalarStores",
366  "true",
367  "Has store scalar memory instructions"
368>;
369
370def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
371  "HasScalarAtomics",
372  "true",
373  "Has atomic scalar memory instructions"
374>;
375
376def FeatureSDWA : SubtargetFeature<"sdwa",
377  "HasSDWA",
378  "true",
379  "Support SDWA (Sub-DWORD Addressing) extension"
380>;
381
382def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
383  "HasSDWAOmod",
384  "true",
385  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
386>;
387
388def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
389  "HasSDWAScalar",
390  "true",
391  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
392>;
393
394def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
395  "HasSDWASdst",
396  "true",
397  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
398>;
399
400def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
401  "HasSDWAMac",
402  "true",
403  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
404>;
405
406def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
407  "HasSDWAOutModsVOPC",
408  "true",
409  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
410>;
411
412def FeatureDPP : SubtargetFeature<"dpp",
413  "HasDPP",
414  "true",
415  "Support DPP (Data Parallel Primitives) extension"
416>;
417
418// DPP8 allows arbitrary cross-lane swizzling within groups of 8 lanes.
419def FeatureDPP8 : SubtargetFeature<"dpp8",
420  "HasDPP8",
421  "true",
422  "Support DPP8 (Data Parallel Primitives) extension"
423>;
424
425def Feature64BitDPP : SubtargetFeature<"dpp-64bit",
426  "Has64BitDPP",
427  "true",
428  "Support DPP (Data Parallel Primitives) extension"
429>;
430
431def FeaturePackedFP32Ops : SubtargetFeature<"packed-fp32-ops",
432  "HasPackedFP32Ops",
433  "true",
434  "Support packed fp32 instructions"
435>;
436
437def FeatureR128A16 : SubtargetFeature<"r128-a16",
438  "HasR128A16",
439  "true",
440  "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128"
441>;
442
443def FeatureGFX10A16 : SubtargetFeature<"a16",
444  "HasGFX10A16",
445  "true",
446  "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands"
447>;
448
449def FeatureG16 : SubtargetFeature<"g16",
450  "HasG16",
451  "true",
452  "Support G16 for 16-bit gradient image operands"
453>;
454
455def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
456  "HasNSAEncoding",
457  "true",
458  "Support NSA encoding for image instructions"
459>;
460
461def FeatureExtendedImageInsts : SubtargetFeature<"extended-image-insts",
462  "HasExtendedImageInsts",
463  "true",
464  "Support mips != 0, lod != 0, gather4, and get_lod"
465>;
466
467def FeatureGFX10_AEncoding : SubtargetFeature<"gfx10_a-encoding",
468  "GFX10_AEncoding",
469  "true",
470  "Has BVH ray tracing instructions"
471>;
472
473def FeatureGFX10_BEncoding : SubtargetFeature<"gfx10_b-encoding",
474  "GFX10_BEncoding",
475  "true",
476  "Encoding format GFX10_B"
477>;
478
479def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
480  "HasIntClamp",
481  "true",
482  "Support clamp for integer destination"
483>;
484
485def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
486  "HasUnpackedD16VMem",
487  "true",
488  "Has unpacked d16 vmem instructions"
489>;
490
491def FeatureDLInsts : SubtargetFeature<"dl-insts",
492  "HasDLInsts",
493  "true",
494  "Has v_fmac_f32 and v_xnor_b32 instructions"
495>;
496
497def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
498  "HasDot1Insts",
499  "true",
500  "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
501>;
502
503def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
504  "HasDot2Insts",
505  "true",
506  "Has v_dot2_i32_i16, v_dot2_u32_u16 instructions"
507>;
508
509def FeatureDot3Insts : SubtargetFeature<"dot3-insts",
510  "HasDot3Insts",
511  "true",
512  "Has v_dot8c_i32_i4 instruction"
513>;
514
515def FeatureDot4Insts : SubtargetFeature<"dot4-insts",
516  "HasDot4Insts",
517  "true",
518  "Has v_dot2c_i32_i16 instruction"
519>;
520
521def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
522  "HasDot5Insts",
523  "true",
524  "Has v_dot2c_f32_f16 instruction"
525>;
526
527def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
528  "HasDot6Insts",
529  "true",
530  "Has v_dot4c_i32_i8 instruction"
531>;
532
533def FeatureDot7Insts : SubtargetFeature<"dot7-insts",
534  "HasDot7Insts",
535  "true",
536  "Has v_dot2_f32_f16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
537>;
538
539def FeatureMAIInsts : SubtargetFeature<"mai-insts",
540  "HasMAIInsts",
541  "true",
542  "Has mAI instructions"
543>;
544
545def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
546  "HasPkFmacF16Inst",
547  "true",
548  "Has v_pk_fmac_f16 instruction"
549>;
550
551def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts",
552  "HasAtomicFaddInsts",
553  "true",
554  "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, "
555  "global_atomic_pk_add_f16 instructions",
556  [FeatureFlatGlobalInsts]
557>;
558
559def FeatureSupportsSRAMECC : SubtargetFeature<"sramecc-support",
560  "SupportsSRAMECC",
561  "true",
562  "Hardware supports SRAMECC"
563>;
564
565def FeatureSRAMECC : SubtargetFeature<"sramecc",
566  "EnableSRAMECC",
567  "true",
568  "Enable SRAMECC"
569>;
570
571def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
572  "HasNoSdstCMPX",
573  "true",
574  "V_CMPX does not write VCC/SGPR in addition to EXEC"
575>;
576
577def FeatureVscnt : SubtargetFeature<"vscnt",
578  "HasVscnt",
579  "true",
580  "Has separate store vscnt counter"
581>;
582
583def FeatureGetWaveIdInst : SubtargetFeature<"get-wave-id-inst",
584  "HasGetWaveIdInst",
585  "true",
586  "Has s_get_waveid_in_workgroup instruction"
587>;
588
589def FeatureSMemTimeInst : SubtargetFeature<"s-memtime-inst",
590  "HasSMemTimeInst",
591  "true",
592  "Has s_memtime instruction"
593>;
594
595def FeatureShaderCyclesRegister : SubtargetFeature<"shader-cycles-register",
596  "HasShaderCyclesRegister",
597  "true",
598  "Has SHADER_CYCLES hardware register"
599>;
600
601def FeatureMadMacF32Insts : SubtargetFeature<"mad-mac-f32-insts",
602  "HasMadMacF32Insts",
603  "true",
604  "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions"
605>;
606
607def FeatureDsSrc2Insts : SubtargetFeature<"ds-src2-insts",
608  "HasDsSrc2Insts",
609  "true",
610  "Has ds_*_src2 instructions"
611>;
612
613def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
614  "HasVOP3Literal",
615  "true",
616  "Can use one literal in VOP3"
617>;
618
619def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
620  "HasNoDataDepHazard",
621  "true",
622  "Does not need SW waitstates"
623>;
624
625class SubtargetFeatureNSAMaxSize <int Value> : SubtargetFeature <
626  "nsa-max-size-"#Value,
627  "NSAMaxSize",
628  !cast<string>(Value),
629  "The maximum non-sequential address size in VGPRs."
630>;
631
632def FeatureNSAMaxSize5 : SubtargetFeatureNSAMaxSize<5>;
633def FeatureNSAMaxSize13 : SubtargetFeatureNSAMaxSize<13>;
634
635//===------------------------------------------------------------===//
636// Subtarget Features (options and debugging)
637//===------------------------------------------------------------===//
638
639class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
640  "max-private-element-size-"#size,
641  "MaxPrivateElementSize",
642  !cast<string>(size),
643  "Maximum private access size may be "#size
644>;
645
646def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
647def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
648def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
649
650def FeatureDumpCode : SubtargetFeature <"DumpCode",
651  "DumpCode",
652  "true",
653  "Dump MachineInstrs in the CodeEmitter"
654>;
655
656def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
657  "DumpCode",
658  "true",
659  "Dump MachineInstrs in the CodeEmitter"
660>;
661
662// XXX - This should probably be removed once enabled by default
663def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
664  "EnableLoadStoreOpt",
665  "true",
666  "Enable SI load/store optimizer pass"
667>;
668
669// Performance debugging feature. Allow using DS instruction immediate
670// offsets even if the base pointer can't be proven to be base. On SI,
671// base pointer values that won't give the same result as a 16-bit add
672// are not safe to fold, but this will override the conservative test
673// for the base pointer.
674def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
675  "unsafe-ds-offset-folding",
676  "EnableUnsafeDSOffsetFolding",
677  "true",
678  "Force using DS instruction immediate offsets on SI"
679>;
680
681def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
682  "EnableSIScheduler",
683  "true",
684  "Enable SI Machine Scheduler"
685>;
686
687def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
688  "EnableDS128",
689  "true",
690  "Use ds_{read|write}_b128"
691>;
692
693// Sparse texture support requires that all result registers are zeroed when
694// PRTStrictNull is set to true. This feature is turned on for all architectures
695// but is enabled as a feature in case there are situations where PRTStrictNull
696// is disabled by the driver.
697def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
698  "EnablePRTStrictNull",
699  "true",
700  "Enable zeroing of result registers for sparse texture fetches"
701>;
702
703// Unless +-flat-for-global is specified, turn on FlatForGlobal for
704// all OS-es on VI and newer hardware to avoid assertion failures due
705// to missing ADDR64 variants of MUBUF instructions.
706// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
707// instructions.
708
709def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
710  "FlatForGlobal",
711  "true",
712  "Force to generate flat instruction for global"
713>;
714
715def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
716  "auto-waitcnt-before-barrier",
717  "AutoWaitcntBeforeBarrier",
718  "true",
719  "Hardware automatically inserts waitcnt before barrier"
720>;
721
722def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
723  "HasTrigReducedRange",
724  "true",
725  "Requires use of fract on arguments to trig instructions"
726>;
727
728// Alignment enforcement is controlled by a configuration register:
729// SH_MEM_CONFIG.alignment_mode
730def FeatureUnalignedAccessMode : SubtargetFeature<"unaligned-access-mode",
731  "UnalignedAccessMode",
732  "true",
733  "Enable unaligned global, local and region loads and stores if the hardware"
734  " supports it"
735>;
736
737def FeaturePackedTID : SubtargetFeature<"packed-tid",
738  "HasPackedTID",
739  "true",
740  "Workitem IDs are packed into v0 at kernel launch"
741>;
742
743def FeatureArchitectedFlatScratch : SubtargetFeature<"architected-flat-scratch",
744  "HasArchitectedFlatScratch",
745  "true",
746  "Flat Scratch register is a readonly SPI initialized architected register"
747>;
748
749// Dummy feature used to disable assembler instructions.
750def FeatureDisable : SubtargetFeature<"",
751  "FeatureDisable","true",
752  "Dummy feature to disable assembler instructions"
753>;
754
755class GCNSubtargetFeatureGeneration <string Value,
756                                     string FeatureName,
757                                     list<SubtargetFeature> Implies> :
758        SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
759
760def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
761    "southern-islands",
762  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
763  FeatureWavefrontSize64, FeatureSMemTimeInst, FeatureMadMacF32Insts,
764  FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel,
765  FeatureTrigReducedRange, FeatureExtendedImageInsts
766  ]
767>;
768
769def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
770    "sea-islands",
771  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
772  FeatureWavefrontSize64, FeatureFlatAddressSpace,
773  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
774  FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
775  FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureUnalignedBufferAccess
776  ]
777>;
778
779def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
780  "volcanic-islands",
781  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
782   FeatureWavefrontSize64, FeatureFlatAddressSpace,
783   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
784   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
785   FeatureScalarStores, FeatureInv2PiInlineImm,
786   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
787   FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts,
788   FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
789   FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureFastDenormalF32,
790   FeatureUnalignedBufferAccess
791  ]
792>;
793
794def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
795  "gfx9",
796  [FeatureFP64, FeatureLocalMemorySize65536,
797   FeatureWavefrontSize64, FeatureFlatAddressSpace,
798   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
799   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
800   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
801   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
802   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
803   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
804   FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
805   FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16,
806   FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureSupportsXNACK,
807   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess,
808   FeatureNegativeScratchOffsetBug
809  ]
810>;
811
812def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
813  "gfx10",
814  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
815   FeatureFlatAddressSpace,
816   FeatureCIInsts, Feature16BitInsts,
817   FeatureSMemRealTime, FeatureInv2PiInlineImm,
818   FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
819   FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
820   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
821   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
822   FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
823   FeatureNoSdstCMPX, FeatureVscnt,
824   FeatureVOP3Literal, FeatureDPP8, FeatureExtendedImageInsts,
825   FeatureNoDataDepHazard, FeaturePkFmacF16Inst,
826   FeatureGFX10A16, FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureG16,
827   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess
828  ]
829>;
830
831class FeatureSet<list<SubtargetFeature> Features_> {
832  list<SubtargetFeature> Features = Features_;
833}
834
835def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
836   FeatureFastFMAF32,
837   HalfRate64Ops,
838   FeatureLDSBankCount32]>;
839
840def FeatureISAVersion6_0_1 : FeatureSet<
841  [FeatureSouthernIslands,
842   FeatureLDSBankCount32]>;
843
844def FeatureISAVersion6_0_2 : FeatureSet<
845  [FeatureSouthernIslands,
846   FeatureLDSBankCount32]>;
847
848def FeatureISAVersion7_0_0 : FeatureSet<
849  [FeatureSeaIslands,
850   FeatureLDSBankCount32]>;
851
852def FeatureISAVersion7_0_1 : FeatureSet<
853  [FeatureSeaIslands,
854   HalfRate64Ops,
855   FeatureLDSBankCount32,
856   FeatureFastFMAF32]>;
857
858def FeatureISAVersion7_0_2 : FeatureSet<
859  [FeatureSeaIslands,
860   FeatureLDSBankCount16,
861   FeatureFastFMAF32]>;
862
863def FeatureISAVersion7_0_3 : FeatureSet<
864  [FeatureSeaIslands,
865   FeatureLDSBankCount16]>;
866
867def FeatureISAVersion7_0_4 : FeatureSet<
868  [FeatureSeaIslands,
869   FeatureLDSBankCount32]>;
870
871def FeatureISAVersion7_0_5 : FeatureSet<
872  [FeatureSeaIslands,
873   FeatureLDSBankCount16]>;
874
875def FeatureISAVersion8_0_1 : FeatureSet<
876  [FeatureVolcanicIslands,
877   FeatureFastFMAF32,
878   HalfRate64Ops,
879   FeatureLDSBankCount32,
880   FeatureSupportsXNACK,
881   FeatureUnpackedD16VMem]>;
882
883def FeatureISAVersion8_0_2 : FeatureSet<
884  [FeatureVolcanicIslands,
885   FeatureLDSBankCount32,
886   FeatureSGPRInitBug,
887   FeatureUnpackedD16VMem]>;
888
889def FeatureISAVersion8_0_3 : FeatureSet<
890  [FeatureVolcanicIslands,
891   FeatureLDSBankCount32,
892   FeatureUnpackedD16VMem]>;
893
894def FeatureISAVersion8_0_5 : FeatureSet<
895  [FeatureVolcanicIslands,
896   FeatureLDSBankCount32,
897   FeatureSGPRInitBug,
898   FeatureUnpackedD16VMem]>;
899
900def FeatureISAVersion8_1_0 : FeatureSet<
901  [FeatureVolcanicIslands,
902   FeatureLDSBankCount16,
903   FeatureSupportsXNACK,
904   FeatureImageStoreD16Bug,
905   FeatureImageGather4D16Bug]>;
906
907def FeatureISAVersion9_0_0 : FeatureSet<
908  [FeatureGFX9,
909   FeatureMadMixInsts,
910   FeatureLDSBankCount32,
911   FeatureDsSrc2Insts,
912   FeatureExtendedImageInsts,
913   FeatureMadMacF32Insts,
914   FeatureImageGather4D16Bug]>;
915
916def FeatureISAVersion9_0_2 : FeatureSet<
917  [FeatureGFX9,
918   FeatureMadMixInsts,
919   FeatureLDSBankCount32,
920   FeatureDsSrc2Insts,
921   FeatureExtendedImageInsts,
922   FeatureMadMacF32Insts,
923   FeatureImageGather4D16Bug]>;
924
925def FeatureISAVersion9_0_4 : FeatureSet<
926  [FeatureGFX9,
927   FeatureLDSBankCount32,
928   FeatureDsSrc2Insts,
929   FeatureExtendedImageInsts,
930   FeatureMadMacF32Insts,
931   FeatureFmaMixInsts,
932   FeatureImageGather4D16Bug]>;
933
934def FeatureISAVersion9_0_6 : FeatureSet<
935  [FeatureGFX9,
936   HalfRate64Ops,
937   FeatureFmaMixInsts,
938   FeatureLDSBankCount32,
939   FeatureDsSrc2Insts,
940   FeatureExtendedImageInsts,
941   FeatureMadMacF32Insts,
942   FeatureDLInsts,
943   FeatureDot1Insts,
944   FeatureDot2Insts,
945   FeatureDot7Insts,
946   FeatureSupportsSRAMECC,
947   FeatureImageGather4D16Bug]>;
948
949def FeatureISAVersion9_0_8 : FeatureSet<
950  [FeatureGFX9,
951   HalfRate64Ops,
952   FeatureFmaMixInsts,
953   FeatureLDSBankCount32,
954   FeatureDsSrc2Insts,
955   FeatureExtendedImageInsts,
956   FeatureMadMacF32Insts,
957   FeatureDLInsts,
958   FeatureDot1Insts,
959   FeatureDot2Insts,
960   FeatureDot3Insts,
961   FeatureDot4Insts,
962   FeatureDot5Insts,
963   FeatureDot6Insts,
964   FeatureDot7Insts,
965   FeatureMAIInsts,
966   FeaturePkFmacF16Inst,
967   FeatureAtomicFaddInsts,
968   FeatureSupportsSRAMECC,
969   FeatureMFMAInlineLiteralBug,
970   FeatureImageGather4D16Bug]>;
971
972def FeatureISAVersion9_0_9 : FeatureSet<
973  [FeatureGFX9,
974   FeatureMadMixInsts,
975   FeatureLDSBankCount32,
976   FeatureDsSrc2Insts,
977   FeatureExtendedImageInsts,
978   FeatureMadMacF32Insts,
979   FeatureImageGather4D16Bug]>;
980
981def FeatureISAVersion9_0_A : FeatureSet<
982  [FeatureGFX9,
983   FeatureGFX90AInsts,
984   FeatureFmaMixInsts,
985   FeatureLDSBankCount32,
986   FeatureDLInsts,
987   FeatureDot1Insts,
988   FeatureDot2Insts,
989   FeatureDot3Insts,
990   FeatureDot4Insts,
991   FeatureDot5Insts,
992   FeatureDot6Insts,
993   FeatureDot7Insts,
994   Feature64BitDPP,
995   FeaturePackedFP32Ops,
996   FeatureMAIInsts,
997   FeaturePkFmacF16Inst,
998   FeatureAtomicFaddInsts,
999   FeatureMadMacF32Insts,
1000   FeatureSupportsSRAMECC,
1001   FeaturePackedTID,
1002   FullRate64Ops]>;
1003
1004def FeatureISAVersion9_0_C : FeatureSet<
1005  [FeatureGFX9,
1006   FeatureMadMixInsts,
1007   FeatureLDSBankCount32,
1008   FeatureDsSrc2Insts,
1009   FeatureExtendedImageInsts,
1010   FeatureMadMacF32Insts,
1011   FeatureImageGather4D16Bug]>;
1012
1013// TODO: Organize more features into groups.
1014def FeatureGroup {
1015  // Bugs present on gfx10.1.
1016  list<SubtargetFeature> GFX10_1_Bugs = [
1017    FeatureVcmpxPermlaneHazard,
1018    FeatureVMEMtoScalarWriteHazard,
1019    FeatureSMEMtoVectorWriteHazard,
1020    FeatureInstFwdPrefetchBug,
1021    FeatureVcmpxExecWARHazard,
1022    FeatureLdsBranchVmemWARHazard,
1023    FeatureNSAtoVMEMBug,
1024    FeatureNSAClauseBug,
1025    FeatureOffset3fBug,
1026    FeatureFlatSegmentOffsetBug,
1027    FeatureNegativeUnalignedScratchOffsetBug
1028   ];
1029}
1030
1031def FeatureISAVersion10_1_0 : FeatureSet<
1032  !listconcat(FeatureGroup.GFX10_1_Bugs,
1033    [FeatureGFX10,
1034     FeatureLDSBankCount32,
1035     FeatureDLInsts,
1036     FeatureNSAEncoding,
1037     FeatureNSAMaxSize5,
1038     FeatureWavefrontSize32,
1039     FeatureScalarStores,
1040     FeatureScalarAtomics,
1041     FeatureScalarFlatScratchInsts,
1042     FeatureGetWaveIdInst,
1043     FeatureMadMacF32Insts,
1044     FeatureDsSrc2Insts,
1045     FeatureLdsMisalignedBug,
1046     FeatureSupportsXNACK])>;
1047
1048def FeatureISAVersion10_1_1 : FeatureSet<
1049  !listconcat(FeatureGroup.GFX10_1_Bugs,
1050    [FeatureGFX10,
1051     FeatureLDSBankCount32,
1052     FeatureDLInsts,
1053     FeatureDot1Insts,
1054     FeatureDot2Insts,
1055     FeatureDot5Insts,
1056     FeatureDot6Insts,
1057     FeatureDot7Insts,
1058     FeatureNSAEncoding,
1059     FeatureNSAMaxSize5,
1060     FeatureWavefrontSize32,
1061     FeatureScalarStores,
1062     FeatureScalarAtomics,
1063     FeatureScalarFlatScratchInsts,
1064     FeatureGetWaveIdInst,
1065     FeatureMadMacF32Insts,
1066     FeatureDsSrc2Insts,
1067     FeatureLdsMisalignedBug,
1068     FeatureSupportsXNACK])>;
1069
1070def FeatureISAVersion10_1_2 : FeatureSet<
1071  !listconcat(FeatureGroup.GFX10_1_Bugs,
1072    [FeatureGFX10,
1073     FeatureLDSBankCount32,
1074     FeatureDLInsts,
1075     FeatureDot1Insts,
1076     FeatureDot2Insts,
1077     FeatureDot5Insts,
1078     FeatureDot6Insts,
1079     FeatureDot7Insts,
1080     FeatureNSAEncoding,
1081     FeatureNSAMaxSize5,
1082     FeatureWavefrontSize32,
1083     FeatureScalarStores,
1084     FeatureScalarAtomics,
1085     FeatureScalarFlatScratchInsts,
1086     FeatureGetWaveIdInst,
1087     FeatureMadMacF32Insts,
1088     FeatureDsSrc2Insts,
1089     FeatureLdsMisalignedBug,
1090     FeatureSupportsXNACK])>;
1091
1092def FeatureISAVersion10_1_3 : FeatureSet<
1093  !listconcat(FeatureGroup.GFX10_1_Bugs,
1094    [FeatureGFX10,
1095     FeatureGFX10_AEncoding,
1096     FeatureLDSBankCount32,
1097     FeatureDLInsts,
1098     FeatureNSAEncoding,
1099     FeatureNSAMaxSize5,
1100     FeatureWavefrontSize32,
1101     FeatureScalarStores,
1102     FeatureScalarAtomics,
1103     FeatureScalarFlatScratchInsts,
1104     FeatureGetWaveIdInst,
1105     FeatureMadMacF32Insts,
1106     FeatureDsSrc2Insts,
1107     FeatureLdsMisalignedBug,
1108     FeatureSupportsXNACK])>;
1109
1110def FeatureISAVersion10_3_0 : FeatureSet<
1111  [FeatureGFX10,
1112   FeatureGFX10_AEncoding,
1113   FeatureGFX10_BEncoding,
1114   FeatureGFX10_3Insts,
1115   FeatureLDSBankCount32,
1116   FeatureDLInsts,
1117   FeatureDot1Insts,
1118   FeatureDot2Insts,
1119   FeatureDot5Insts,
1120   FeatureDot6Insts,
1121   FeatureDot7Insts,
1122   FeatureNSAEncoding,
1123   FeatureNSAMaxSize13,
1124   FeatureWavefrontSize32,
1125   FeatureShaderCyclesRegister]>;
1126
1127//===----------------------------------------------------------------------===//
1128
1129def AMDGPUInstrInfo : InstrInfo {
1130  let guessInstructionProperties = 1;
1131  let noNamedPositionallyEncodedOperands = 1;
1132}
1133
1134def AMDGPUAsmParser : AsmParser {
1135  // Some of the R600 registers have the same name, so this crashes.
1136  // For example T0_XYZW and T0_XY both have the asm name T0.
1137  let ShouldEmitMatchRegisterName = 0;
1138}
1139
1140def AMDGPUAsmWriter : AsmWriter {
1141  int PassSubtarget = 1;
1142}
1143
1144def AMDGPUAsmVariants {
1145  string Default = "Default";
1146  int Default_ID = 0;
1147  string VOP3 = "VOP3";
1148  int VOP3_ID = 1;
1149  string SDWA = "SDWA";
1150  int SDWA_ID = 2;
1151  string SDWA9 = "SDWA9";
1152  int SDWA9_ID = 3;
1153  string DPP = "DPP";
1154  int DPP_ID = 4;
1155  string Disable = "Disable";
1156  int Disable_ID = 5;
1157}
1158
1159def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
1160  let Variant = AMDGPUAsmVariants.Default_ID;
1161  let Name = AMDGPUAsmVariants.Default;
1162}
1163
1164def VOP3AsmParserVariant : AsmParserVariant {
1165  let Variant = AMDGPUAsmVariants.VOP3_ID;
1166  let Name = AMDGPUAsmVariants.VOP3;
1167}
1168
1169def SDWAAsmParserVariant : AsmParserVariant {
1170  let Variant = AMDGPUAsmVariants.SDWA_ID;
1171  let Name = AMDGPUAsmVariants.SDWA;
1172}
1173
1174def SDWA9AsmParserVariant : AsmParserVariant {
1175  let Variant = AMDGPUAsmVariants.SDWA9_ID;
1176  let Name = AMDGPUAsmVariants.SDWA9;
1177}
1178
1179
1180def DPPAsmParserVariant : AsmParserVariant {
1181  let Variant = AMDGPUAsmVariants.DPP_ID;
1182  let Name = AMDGPUAsmVariants.DPP;
1183}
1184
1185def AMDGPU : Target {
1186  // Pull in Instruction Info:
1187  let InstructionSet = AMDGPUInstrInfo;
1188  let AssemblyParsers = [AMDGPUAsmParser];
1189  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
1190                                VOP3AsmParserVariant,
1191                                SDWAAsmParserVariant,
1192                                SDWA9AsmParserVariant,
1193                                DPPAsmParserVariant];
1194  let AssemblyWriters = [AMDGPUAsmWriter];
1195  let AllowRegisterRenaming = 1;
1196}
1197
1198// Dummy Instruction itineraries for pseudo instructions
1199def ALU_NULL : FuncUnit;
1200def NullALU : InstrItinClass;
1201
1202//===----------------------------------------------------------------------===//
1203// Predicate helper class
1204//===----------------------------------------------------------------------===//
1205
1206def isGFX6 :
1207  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
1208  AssemblerPredicate<(all_of FeatureSouthernIslands)>;
1209
1210def isGFX6GFX7 :
1211  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1212            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1213  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX10Insts))>;
1214
1215def isGFX6GFX7GFX10 :
1216  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1217            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1218            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1219  AssemblerPredicate<(all_of (not FeatureGCN3Encoding))>;
1220
1221def isGFX7Only :
1222  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1223  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX10Insts))>;
1224
1225def isGFX7GFX10 :
1226  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1227            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1228  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>;
1229
1230def isGFX7GFX8GFX9 :
1231  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1232            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1233            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1234  AssemblerPredicate<(all_of FeatureGFX7GFX8GFX9Insts)>;
1235
1236def isGFX6GFX7GFX8GFX9 :
1237  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1238            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1239            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1240            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1241  AssemblerPredicate<(all_of (not FeatureGFX10Insts))>;
1242
1243def isGFX6GFX7GFX8GFX9NotGFX90A :
1244  Predicate<"!Subtarget->hasGFX90AInsts() &&"
1245            "(Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1246            " Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1247            " Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1248            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1249  AssemblerPredicate<(all_of (not FeatureGFX10Insts), (not FeatureGFX90AInsts))>;
1250
1251def isGFX7Plus :
1252  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
1253  AssemblerPredicate<(all_of FeatureCIInsts)>;
1254
1255def isGFX8Plus :
1256  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1257  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1258
1259def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
1260                           "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1261  AssemblerPredicate <(all_of FeatureVolcanicIslands)>;
1262
1263def isGFX9Plus :
1264  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1265  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1266
1267def isGFX9Only : Predicate <
1268  "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1269  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts)>;
1270
1271def isGCN3ExcludingGFX90A :
1272  Predicate<"Subtarget->isGCN3Encoding() && !Subtarget->hasGFX90AInsts()">,
1273  AssemblerPredicate<(all_of FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1274
1275def isGFX90APlus :
1276  Predicate<"Subtarget->hasGFX90AInsts()">,
1277  AssemblerPredicate<(all_of FeatureGFX90AInsts)>;
1278
1279def isNotGFX90APlus :
1280  Predicate<"!Subtarget->hasGFX90AInsts()">,
1281  AssemblerPredicate<(all_of (not FeatureGFX90AInsts))>;
1282
1283def isGFX8GFX9NotGFX90A :
1284  Predicate<"!Subtarget->hasGFX90AInsts() &&"
1285            "(Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1286            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1287  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1288
1289def isGFX90AOnly :
1290  Predicate<"Subtarget->hasGFX90AInsts()">,
1291  AssemblerPredicate<(all_of FeatureGFX90AInsts)>;
1292
1293def isGFX908orGFX90A :
1294  Predicate<"Subtarget->hasMAIInsts()">,
1295  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1296
1297def isGFX8GFX9 :
1298  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1299            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1300  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>;
1301
1302def isGFX10Plus :
1303  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1304  AssemblerPredicate<(all_of FeatureGFX10Insts)>;
1305
1306def isGFX10Before1030 :
1307  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 &&"
1308            "!Subtarget->hasGFX10_3Insts()">,
1309  AssemblerPredicate<(all_of FeatureGFX10Insts,(not FeatureGFX10_3Insts))>;
1310
1311def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
1312  AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
1313
1314def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
1315  AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>;
1316def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
1317  AssemblerPredicate<(all_of FeatureFlatScratchInsts)>;
1318def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
1319  AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>;
1320def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
1321  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1322
1323def HasFlatScratchSTMode : Predicate<"Subtarget->hasFlatScratchSTMode()">,
1324  AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1325
1326def HasGFX10_AEncoding : Predicate<"Subtarget->hasGFX10_AEncoding()">,
1327  AssemblerPredicate<(all_of FeatureGFX10_AEncoding)>;
1328
1329def HasGFX10_BEncoding : Predicate<"Subtarget->hasGFX10_BEncoding()">,
1330  AssemblerPredicate<(all_of FeatureGFX10_BEncoding)>;
1331
1332def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
1333  AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>;
1334def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
1335  AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>;
1336
1337def D16PreservesUnusedBits :
1338  Predicate<"Subtarget->d16PreservesUnusedBits()">,
1339  AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>;
1340
1341def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
1342def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
1343
1344def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1345  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1346
1347def HasLDSFPAtomicAdd : Predicate<"Subtarget->hasLDSFPAtomicAdd()">,
1348  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1349
1350def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
1351  AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>;
1352
1353def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
1354
1355def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
1356  AssemblerPredicate<(all_of Feature16BitInsts)>;
1357def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
1358  AssemblerPredicate<(all_of FeatureVOP3P)>;
1359
1360def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">;
1361def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">;
1362
1363def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
1364  AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
1365
1366def HasSDWA9 :
1367  Predicate<"Subtarget->hasSDWA()">,
1368  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>;
1369
1370def HasSDWA10 :
1371  Predicate<"Subtarget->hasSDWA()">,
1372  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureSDWA)>;
1373
1374def HasDPP : Predicate<"Subtarget->hasDPP()">,
1375  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>;
1376
1377def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
1378  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>;
1379
1380def Has64BitDPP : Predicate<"Subtarget->has64BitDPP()">,
1381  AssemblerPredicate<(all_of Feature64BitDPP)>;
1382
1383def HasPackedFP32Ops : Predicate<"Subtarget->hasPackedFP32Ops()">,
1384  AssemblerPredicate<(all_of FeaturePackedFP32Ops)>;
1385
1386def HasFmaakFmamkF32Insts :
1387  Predicate<"Subtarget->hasFmaakFmamkF32Insts()">,
1388  AssemblerPredicate<(any_of FeatureGFX10Insts)>;
1389
1390def HasExtendedImageInsts : Predicate<"Subtarget->hasExtendedImageInsts()">,
1391  AssemblerPredicate<(all_of FeatureExtendedImageInsts)>;
1392
1393def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
1394  AssemblerPredicate<(all_of FeatureR128A16)>;
1395
1396def HasGFX10A16 : Predicate<"Subtarget->hasGFX10A16()">,
1397  AssemblerPredicate<(all_of FeatureGFX10A16)>;
1398
1399def HasG16 : Predicate<"Subtarget->hasG16()">,
1400  AssemblerPredicate<(all_of FeatureG16)>;
1401
1402def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
1403  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP)>;
1404
1405def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
1406  AssemblerPredicate<(all_of FeatureIntClamp)>;
1407
1408def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
1409  AssemblerPredicate<(all_of FeatureMadMixInsts)>;
1410
1411def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
1412  AssemblerPredicate<(all_of FeatureScalarStores)>;
1413
1414def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
1415  AssemblerPredicate<(all_of FeatureScalarAtomics)>;
1416
1417def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
1418  AssemblerPredicate<(all_of FeatureNoSdstCMPX)>;
1419
1420def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
1421  AssemblerPredicate<(all_of (not FeatureNoSdstCMPX))>;
1422
1423def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
1424def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
1425def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
1426                      AssemblerPredicate<(all_of FeatureVGPRIndexMode)>;
1427def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
1428                AssemblerPredicate<(all_of FeatureMovrel)>;
1429
1430def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
1431  AssemblerPredicate<(all_of FeatureFmaMixInsts)>;
1432
1433def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
1434  AssemblerPredicate<(all_of FeatureDLInsts)>;
1435
1436def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
1437  AssemblerPredicate<(all_of FeatureDot1Insts)>;
1438
1439def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
1440  AssemblerPredicate<(all_of FeatureDot2Insts)>;
1441
1442def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">,
1443  AssemblerPredicate<(all_of FeatureDot3Insts)>;
1444
1445def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">,
1446  AssemblerPredicate<(all_of FeatureDot4Insts)>;
1447
1448def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
1449  AssemblerPredicate<(all_of FeatureDot5Insts)>;
1450
1451def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
1452  AssemblerPredicate<(all_of FeatureDot6Insts)>;
1453
1454def HasDot7Insts : Predicate<"Subtarget->hasDot7Insts()">,
1455  AssemblerPredicate<(all_of FeatureDot7Insts)>;
1456
1457def HasGetWaveIdInst : Predicate<"Subtarget->hasGetWaveIdInst()">,
1458  AssemblerPredicate<(all_of FeatureGetWaveIdInst)>;
1459
1460def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
1461  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1462
1463def HasSMemRealTime : Predicate<"Subtarget->hasSMemRealTime()">,
1464  AssemblerPredicate<(all_of FeatureSMemRealTime)>;
1465
1466def HasSMemTimeInst : Predicate<"Subtarget->hasSMemTimeInst()">,
1467  AssemblerPredicate<(all_of FeatureSMemTimeInst)>;
1468
1469def HasShaderCyclesRegister : Predicate<"Subtarget->hasShaderCyclesRegister()">,
1470  AssemblerPredicate<(all_of FeatureShaderCyclesRegister)>;
1471
1472def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">,
1473  AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>;
1474
1475def HasMadMacF32Insts : Predicate<"Subtarget->hasMadMacF32Insts()">,
1476  AssemblerPredicate<(all_of FeatureMadMacF32Insts)>;
1477
1478def HasFmaLegacy32 : Predicate<"Subtarget->hasGFX10_3Insts()">,
1479  AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1480
1481def HasAtomicFaddInsts : Predicate<"Subtarget->hasAtomicFaddInsts()">,
1482  AssemblerPredicate<(all_of FeatureAtomicFaddInsts)>;
1483
1484def HasDsSrc2Insts : Predicate<"!Subtarget->hasDsSrc2Insts()">,
1485  AssemblerPredicate<(all_of FeatureDsSrc2Insts)>;
1486
1487def EnableLateCFGStructurize : Predicate<
1488  "EnableLateStructurizeCFG">;
1489
1490def EnableFlatScratch : Predicate<"Subtarget->enableFlatScratch()">;
1491
1492def DisableFlatScratch : Predicate<"!Subtarget->enableFlatScratch()">;
1493
1494def HasUnalignedAccessMode : Predicate<"Subtarget->hasUnalignedAccessMode()">,
1495  AssemblerPredicate<(all_of FeatureUnalignedAccessMode)>;
1496
1497// Include AMDGPU TD files
1498include "SISchedule.td"
1499include "GCNProcessors.td"
1500include "AMDGPUInstrInfo.td"
1501include "SIRegisterInfo.td"
1502include "AMDGPURegisterBanks.td"
1503include "AMDGPUInstructions.td"
1504include "SIInstrInfo.td"
1505include "AMDGPUCallingConv.td"
1506include "AMDGPUSearchableTables.td"
1507