xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPU.td (revision 1db9f3b21e39176dd5b67cf8ac378633b172463e) 
1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===------------------------------------------------------------===//
8
9include "llvm/TableGen/SearchableTable.td"
10include "llvm/Target/Target.td"
11include "AMDGPUFeatures.td"
12
13def p0 : PtrValueType<i64, 0>;
14def p1 : PtrValueType<i64, 1>;
15def p2 : PtrValueType<i32, 2>;
16def p3 : PtrValueType<i32, 3>;
17def p4 : PtrValueType<i64, 4>;
18def p5 : PtrValueType<i32, 5>;
19def p6 : PtrValueType<i32, 6>;
20
21//===------------------------------------------------------------===//
22// Subtarget Features (device properties)
23//===------------------------------------------------------------===//
24
25def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
26  "FastFMAF32",
27  "true",
28  "Assuming f32 fma is at least as fast as mul + add"
29>;
30
31def FeatureFastDenormalF32 : SubtargetFeature<"fast-denormal-f32",
32  "FastDenormalF32",
33  "true",
34  "Enabling denormals does not cause f32 instructions to run at f64 rates"
35>;
36
37def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
38  "MIMG_R128",
39  "true",
40  "Support 128-bit texture resources"
41>;
42
43def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
44  "HalfRate64Ops",
45  "true",
46  "Most fp64 instructions are half rate instead of quarter"
47>;
48
49def FullRate64Ops : SubtargetFeature<"full-rate-64-ops",
50  "FullRate64Ops",
51  "true",
52  "Most fp64 instructions are full rate"
53>;
54
55def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
56  "FlatAddressSpace",
57  "true",
58  "Support flat address space"
59>;
60
61def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
62  "FlatInstOffsets",
63  "true",
64  "Flat instructions have immediate offset addressing mode"
65>;
66
67def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
68  "FlatGlobalInsts",
69  "true",
70  "Have global_* flat memory instructions"
71>;
72
73def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
74  "FlatScratchInsts",
75  "true",
76  "Have scratch_* flat memory instructions"
77>;
78
79def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
80  "ScalarFlatScratchInsts",
81  "true",
82  "Have s_scratch_* flat memory instructions"
83>;
84
85def FeatureEnableFlatScratch : SubtargetFeature<"enable-flat-scratch",
86  "EnableFlatScratch",
87  "true",
88  "Use scratch_* flat memory instructions to access scratch"
89>;
90
91def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
92  "AddNoCarryInsts",
93  "true",
94  "Have VALU add/sub instructions without carry out"
95>;
96
97def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
98  "UnalignedBufferAccess",
99  "true",
100  "Hardware supports unaligned global loads and stores"
101>;
102
103def FeatureTrapHandler: SubtargetFeature<"trap-handler",
104  "TrapHandler",
105  "true",
106  "Trap handler support"
107>;
108
109def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
110  "UnalignedScratchAccess",
111  "true",
112  "Support unaligned scratch loads and stores"
113>;
114
115def FeatureUnalignedDSAccess : SubtargetFeature<"unaligned-ds-access",
116  "UnalignedDSAccess",
117  "true",
118  "Hardware supports unaligned local and region loads and stores"
119>;
120
121def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
122  "HasApertureRegs",
123  "true",
124  "Has Memory Aperture Base and Size Registers"
125>;
126
127def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
128  "HasMadMixInsts",
129  "true",
130  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
131>;
132
133def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
134  "HasFmaMixInsts",
135  "true",
136  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
137>;
138
139def FeatureSupportsXNACK : SubtargetFeature<"xnack-support",
140  "SupportsXNACK",
141  "true",
142  "Hardware supports XNACK"
143>;
144
145// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
146// XNACK. The current default kernel driver setting is:
147// - graphics ring: XNACK disabled
148// - compute ring: XNACK enabled
149//
150// If XNACK is enabled, the VMEM latency can be worse.
151// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
152def FeatureXNACK : SubtargetFeature<"xnack",
153  "EnableXNACK",
154  "true",
155  "Enable XNACK support"
156>;
157
158def FeatureTgSplit : SubtargetFeature<"tgsplit",
159  "EnableTgSplit",
160  "true",
161  "Enable threadgroup split execution"
162>;
163
164def FeatureCuMode : SubtargetFeature<"cumode",
165  "EnableCuMode",
166  "true",
167  "Enable CU wavefront execution mode"
168>;
169
170def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
171  "SGPRInitBug",
172  "true",
173  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
174>;
175
176def FeatureUserSGPRInit16Bug : SubtargetFeature<"user-sgpr-init16-bug",
177  "UserSGPRInit16Bug",
178  "true",
179  "Bug requiring at least 16 user+system SGPRs to be enabled"
180>;
181
182def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
183  "LDSMisalignedBug",
184  "true",
185  "Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode"
186>;
187
188def FeatureMFMAInlineLiteralBug : SubtargetFeature<"mfma-inline-literal-bug",
189  "HasMFMAInlineLiteralBug",
190  "true",
191  "MFMA cannot use inline literal as SrcC"
192>;
193
194def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
195  "HasVcmpxPermlaneHazard",
196  "true",
197  "TODO: describe me"
198>;
199
200def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
201  "HasVMEMtoScalarWriteHazard",
202  "true",
203  "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
204>;
205
206def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
207  "HasSMEMtoVectorWriteHazard",
208  "true",
209  "s_load_dword followed by v_cmp page faults"
210>;
211
212def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
213  "HasInstFwdPrefetchBug",
214  "true",
215  "S_INST_PREFETCH instruction causes shader to hang"
216>;
217
218def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
219  "HasVcmpxExecWARHazard",
220  "true",
221  "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
222>;
223
224def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
225  "HasLdsBranchVmemWARHazard",
226  "true",
227  "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
228>;
229
230def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
231  "HasNSAtoVMEMBug",
232  "true",
233  "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
234>;
235
236def FeatureNSAClauseBug : SubtargetFeature<"nsa-clause-bug",
237  "HasNSAClauseBug",
238  "true",
239  "MIMG-NSA in a hard clause has unpredictable results on GFX10.1"
240>;
241
242def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
243  "HasFlatSegmentOffsetBug",
244  "true",
245  "GFX10 bug where inst_offset is ignored when flat instructions access global memory"
246>;
247
248def FeatureNegativeScratchOffsetBug : SubtargetFeature<"negative-scratch-offset-bug",
249  "NegativeScratchOffsetBug",
250  "true",
251  "Negative immediate offsets in scratch instructions with an SGPR offset page fault on GFX9"
252>;
253
254def FeatureNegativeUnalignedScratchOffsetBug : SubtargetFeature<"negative-unaligned-scratch-offset-bug",
255  "NegativeUnalignedScratchOffsetBug",
256  "true",
257  "Scratch instructions with a VGPR offset and a negative immediate offset that is not a multiple of 4 read wrong memory on GFX10"
258>;
259
260def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
261  "HasOffset3fBug",
262  "true",
263  "Branch offset of 3f hardware bug"
264>;
265
266def FeatureImageStoreD16Bug : SubtargetFeature<"image-store-d16-bug",
267  "HasImageStoreD16Bug",
268  "true",
269  "Image Store D16 hardware bug"
270>;
271
272def FeatureImageGather4D16Bug : SubtargetFeature<"image-gather4-d16-bug",
273  "HasImageGather4D16Bug",
274  "true",
275  "Image Gather4 D16 hardware bug"
276>;
277
278def FeatureMADIntraFwdBug : SubtargetFeature<"mad-intra-fwd-bug",
279  "HasMADIntraFwdBug",
280  "true",
281  "MAD_U64/I64 intra instruction forwarding bug"
282>;
283
284def FeatureMSAALoadDstSelBug : SubtargetFeature<"msaa-load-dst-sel-bug",
285  "HasMSAALoadDstSelBug",
286  "true",
287  "MSAA loads not honoring dst_sel bug"
288>;
289
290class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
291  "ldsbankcount"#Value,
292  "LDSBankCount",
293  !cast<string>(Value),
294  "The number of LDS banks per compute unit."
295>;
296
297def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
298def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
299
300def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
301  "GCN3Encoding",
302  "true",
303  "Encoding format for VI"
304>;
305
306def FeatureCIInsts : SubtargetFeature<"ci-insts",
307  "CIInsts",
308  "true",
309  "Additional instructions for CI+"
310>;
311
312def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
313  "GFX8Insts",
314  "true",
315  "Additional instructions for GFX8+"
316>;
317
318def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
319  "GFX9Insts",
320  "true",
321  "Additional instructions for GFX9+"
322>;
323
324def FeatureGFX90AInsts : SubtargetFeature<"gfx90a-insts",
325  "GFX90AInsts",
326  "true",
327  "Additional instructions for GFX90A+"
328>;
329
330def FeatureGFX940Insts : SubtargetFeature<"gfx940-insts",
331  "GFX940Insts",
332  "true",
333  "Additional instructions for GFX940+"
334>;
335
336def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
337  "GFX10Insts",
338  "true",
339  "Additional instructions for GFX10+"
340>;
341
342def FeatureGFX11Insts : SubtargetFeature<"gfx11-insts",
343  "GFX11Insts",
344  "true",
345  "Additional instructions for GFX11+"
346>;
347
348def FeatureGFX12Insts : SubtargetFeature<"gfx12-insts",
349  "GFX12Insts",
350  "true",
351  "Additional instructions for GFX12+"
352>;
353
354def FeatureGFX10_3Insts : SubtargetFeature<"gfx10-3-insts",
355  "GFX10_3Insts",
356  "true",
357  "Additional instructions for GFX10.3"
358>;
359
360def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
361  "GFX7GFX8GFX9Insts",
362  "true",
363  "Instructions shared in GFX7, GFX8, GFX9"
364>;
365
366def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
367  "HasSMemRealTime",
368  "true",
369  "Has s_memrealtime instruction"
370>;
371
372def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
373  "HasInv2PiInlineImm",
374  "true",
375  "Has 1 / (2 * pi) as inline immediate"
376>;
377
378def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
379  "Has16BitInsts",
380  "true",
381  "Has i16/f16 instructions"
382>;
383
384def FeatureTrue16BitInsts : SubtargetFeature<"true16",
385  "HasTrue16BitInsts",
386  "true",
387  "True 16-bit operand instructions"
388>;
389
390def FeatureRealTrue16Insts : SubtargetFeature<"real-true16",
391  "EnableRealTrue16Insts",
392  "true",
393  "Use true 16-bit registers"
394>;
395
396def FeatureVOP3P : SubtargetFeature<"vop3p",
397  "HasVOP3PInsts",
398  "true",
399  "Has VOP3P packed instructions"
400>;
401
402def FeatureMovrel : SubtargetFeature<"movrel",
403  "HasMovrel",
404  "true",
405  "Has v_movrel*_b32 instructions"
406>;
407
408def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
409  "HasVGPRIndexMode",
410  "true",
411  "Has VGPR mode register indexing"
412>;
413
414def FeatureScalarDwordx3Loads : SubtargetFeature<"scalar-dwordx3-loads",
415  "HasScalarDwordx3Loads",
416  "true",
417  "Has 96-bit scalar load instructions"
418>;
419
420def FeatureScalarStores : SubtargetFeature<"scalar-stores",
421  "HasScalarStores",
422  "true",
423  "Has store scalar memory instructions"
424>;
425
426def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
427  "HasScalarAtomics",
428  "true",
429  "Has atomic scalar memory instructions"
430>;
431
432def FeatureSDWA : SubtargetFeature<"sdwa",
433  "HasSDWA",
434  "true",
435  "Support SDWA (Sub-DWORD Addressing) extension"
436>;
437
438def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
439  "HasSDWAOmod",
440  "true",
441  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
442>;
443
444def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
445  "HasSDWAScalar",
446  "true",
447  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
448>;
449
450def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
451  "HasSDWASdst",
452  "true",
453  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
454>;
455
456def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
457  "HasSDWAMac",
458  "true",
459  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
460>;
461
462def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
463  "HasSDWAOutModsVOPC",
464  "true",
465  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
466>;
467
468def FeatureDPP : SubtargetFeature<"dpp",
469  "HasDPP",
470  "true",
471  "Support DPP (Data Parallel Primitives) extension"
472>;
473
474// DPP8 allows arbitrary cross-lane swizzling within groups of 8 lanes.
475def FeatureDPP8 : SubtargetFeature<"dpp8",
476  "HasDPP8",
477  "true",
478  "Support DPP8 (Data Parallel Primitives) extension"
479>;
480
481def FeatureDPALU_DPP : SubtargetFeature<"dpp-64bit",
482  "HasDPALU_DPP",
483  "true",
484  "Support DPP (Data Parallel Primitives) extension in DP ALU"
485>;
486
487def FeatureDPPSrc1SGPR : SubtargetFeature<"dpp-src1-sgpr",
488  "HasDPPSrc1SGPR",
489  "true",
490  "Support SGPR for Src1 of DPP instructions"
491>;
492
493def FeaturePackedFP32Ops : SubtargetFeature<"packed-fp32-ops",
494  "HasPackedFP32Ops",
495  "true",
496  "Support packed fp32 instructions"
497>;
498
499def FeatureR128A16 : SubtargetFeature<"r128-a16",
500  "HasR128A16",
501  "true",
502  "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128"
503>;
504
505def FeatureA16 : SubtargetFeature<"a16",
506  "HasA16",
507  "true",
508  "Support A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands"
509>;
510
511def FeatureG16 : SubtargetFeature<"g16",
512  "HasG16",
513  "true",
514  "Support G16 for 16-bit gradient image operands"
515>;
516
517def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
518  "HasNSAEncoding",
519  "true",
520  "Support NSA encoding for image instructions"
521>;
522
523def FeaturePartialNSAEncoding : SubtargetFeature<"partial-nsa-encoding",
524  "HasPartialNSAEncoding",
525  "true",
526  "Support partial NSA encoding for image instructions"
527>;
528
529def FeatureImageInsts : SubtargetFeature<"image-insts",
530  "HasImageInsts",
531  "true",
532  "Support image instructions"
533>;
534
535def FeatureExtendedImageInsts : SubtargetFeature<"extended-image-insts",
536  "HasExtendedImageInsts",
537  "true",
538  "Support mips != 0, lod != 0, gather4, and get_lod"
539>;
540
541def FeatureGFX10_AEncoding : SubtargetFeature<"gfx10_a-encoding",
542  "GFX10_AEncoding",
543  "true",
544  "Has BVH ray tracing instructions"
545>;
546
547def FeatureGFX10_BEncoding : SubtargetFeature<"gfx10_b-encoding",
548  "GFX10_BEncoding",
549  "true",
550  "Encoding format GFX10_B"
551>;
552
553def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
554  "HasIntClamp",
555  "true",
556  "Support clamp for integer destination"
557>;
558
559def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
560  "HasUnpackedD16VMem",
561  "true",
562  "Has unpacked d16 vmem instructions"
563>;
564
565def FeatureDLInsts : SubtargetFeature<"dl-insts",
566  "HasDLInsts",
567  "true",
568  "Has v_fmac_f32 and v_xnor_b32 instructions"
569>;
570
571def FeatureFmacF64Inst : SubtargetFeature<"fmacf64-inst",
572  "HasFmacF64Inst",
573  "true",
574  "Has v_fmac_f64 instruction"
575>;
576
577def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
578  "HasDot1Insts",
579  "true",
580  "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
581>;
582
583def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
584  "HasDot2Insts",
585  "true",
586  "Has v_dot2_i32_i16, v_dot2_u32_u16 instructions"
587>;
588
589def FeatureDot3Insts : SubtargetFeature<"dot3-insts",
590  "HasDot3Insts",
591  "true",
592  "Has v_dot8c_i32_i4 instruction"
593>;
594
595def FeatureDot4Insts : SubtargetFeature<"dot4-insts",
596  "HasDot4Insts",
597  "true",
598  "Has v_dot2c_i32_i16 instruction"
599>;
600
601def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
602  "HasDot5Insts",
603  "true",
604  "Has v_dot2c_f32_f16 instruction"
605>;
606
607def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
608  "HasDot6Insts",
609  "true",
610  "Has v_dot4c_i32_i8 instruction"
611>;
612
613def FeatureDot7Insts : SubtargetFeature<"dot7-insts",
614  "HasDot7Insts",
615  "true",
616  "Has v_dot4_u32_u8, v_dot8_u32_u4 instructions"
617>;
618
619def FeatureDot8Insts : SubtargetFeature<"dot8-insts",
620  "HasDot8Insts",
621  "true",
622  "Has v_dot4_i32_iu8, v_dot8_i32_iu4 instructions"
623>;
624
625def FeatureDot9Insts : SubtargetFeature<"dot9-insts",
626  "HasDot9Insts",
627  "true",
628  "Has v_dot2_f16_f16, v_dot2_bf16_bf16, v_dot2_f32_bf16 instructions"
629>;
630
631def FeatureDot10Insts : SubtargetFeature<"dot10-insts",
632  "HasDot10Insts",
633  "true",
634  "Has v_dot2_f32_f16 instruction"
635>;
636
637def FeatureMAIInsts : SubtargetFeature<"mai-insts",
638  "HasMAIInsts",
639  "true",
640  "Has mAI instructions"
641>;
642
643def FeatureFP8Insts : SubtargetFeature<"fp8-insts",
644  "HasFP8Insts",
645  "true",
646  "Has fp8 and bf8 instructions"
647>;
648
649def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
650  "HasPkFmacF16Inst",
651  "true",
652  "Has v_pk_fmac_f16 instruction"
653>;
654
655def FeatureAtomicDsPkAdd16Insts : SubtargetFeature<"atomic-ds-pk-add-16-insts",
656  "HasAtomicDsPkAdd16Insts",
657  "true",
658  "Has ds_pk_add_bf16, ds_pk_add_f16, ds_pk_add_rtn_bf16, "
659  "ds_pk_add_rtn_f16 instructions"
660>;
661
662def FeatureAtomicFlatPkAdd16Insts : SubtargetFeature<"atomic-flat-pk-add-16-insts",
663  "HasAtomicFlatPkAdd16Insts",
664  "true",
665  "Has flat_atomic_pk_add_f16 and flat_atomic_pk_add_bf16 instructions"
666>;
667
668def FeatureAtomicFaddRtnInsts : SubtargetFeature<"atomic-fadd-rtn-insts",
669  "HasAtomicFaddRtnInsts",
670  "true",
671  "Has buffer_atomic_add_f32 and global_atomic_add_f32 instructions that "
672  "return original value",
673  [FeatureFlatGlobalInsts]
674>;
675
676def FeatureAtomicFaddNoRtnInsts : SubtargetFeature<"atomic-fadd-no-rtn-insts",
677  "HasAtomicFaddNoRtnInsts",
678  "true",
679  "Has buffer_atomic_add_f32 and global_atomic_add_f32 instructions that "
680  "don't return original value",
681  [FeatureFlatGlobalInsts]
682>;
683
684def FeatureAtomicBufferGlobalPkAddF16NoRtnInsts
685  : SubtargetFeature<"atomic-buffer-global-pk-add-f16-no-rtn-insts",
686  "HasAtomicBufferGlobalPkAddF16NoRtnInsts",
687  "true",
688  "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that "
689  "don't return original value",
690  [FeatureFlatGlobalInsts]
691>;
692
693def FeatureAtomicBufferGlobalPkAddF16Insts : SubtargetFeature<"atomic-buffer-global-pk-add-f16-insts",
694 "HasAtomicBufferGlobalPkAddF16Insts",
695 "true",
696 "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that "
697 "can return original value",
698 [FeatureFlatGlobalInsts]
699>;
700
701def FeatureAtomicGlobalPkAddBF16Inst : SubtargetFeature<"atomic-global-pk-add-bf16-inst",
702 "HasAtomicGlobalPkAddBF16Inst",
703 "true",
704 "Has global_atomic_pk_add_bf16 instruction",
705 [FeatureFlatGlobalInsts]
706>;
707
708def FeatureAtomicCSubNoRtnInsts : SubtargetFeature<"atomic-csub-no-rtn-insts",
709  "HasAtomicCSubNoRtnInsts",
710  "true",
711  "Has buffer_atomic_csub and global_atomic_csub instructions that don't "
712  "return original value"
713>;
714
715def FeatureFlatAtomicFaddF32Inst
716  : SubtargetFeature<"flat-atomic-fadd-f32-inst",
717  "HasFlatAtomicFaddF32Inst",
718  "true",
719  "Has flat_atomic_add_f32 instruction"
720>;
721
722def FeatureSupportsSRAMECC : SubtargetFeature<"sramecc-support",
723  "SupportsSRAMECC",
724  "true",
725  "Hardware supports SRAMECC"
726>;
727
728def FeatureSRAMECC : SubtargetFeature<"sramecc",
729  "EnableSRAMECC",
730  "true",
731  "Enable SRAMECC"
732>;
733
734def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
735  "HasNoSdstCMPX",
736  "true",
737  "V_CMPX does not write VCC/SGPR in addition to EXEC"
738>;
739
740def FeatureVscnt : SubtargetFeature<"vscnt",
741  "HasVscnt",
742  "true",
743  "Has separate store vscnt counter"
744>;
745
746def FeatureGetWaveIdInst : SubtargetFeature<"get-wave-id-inst",
747  "HasGetWaveIdInst",
748  "true",
749  "Has s_get_waveid_in_workgroup instruction"
750>;
751
752def FeatureSMemTimeInst : SubtargetFeature<"s-memtime-inst",
753  "HasSMemTimeInst",
754  "true",
755  "Has s_memtime instruction"
756>;
757
758def FeatureShaderCyclesRegister : SubtargetFeature<"shader-cycles-register",
759  "HasShaderCyclesRegister",
760  "true",
761  "Has SHADER_CYCLES hardware register"
762>;
763
764def FeatureShaderCyclesHiLoRegisters : SubtargetFeature<"shader-cycles-hi-lo-registers",
765  "HasShaderCyclesHiLoRegisters",
766  "true",
767  "Has SHADER_CYCLES_HI/LO hardware registers"
768>;
769
770def FeatureMadMacF32Insts : SubtargetFeature<"mad-mac-f32-insts",
771  "HasMadMacF32Insts",
772  "true",
773  "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions"
774>;
775
776def FeatureDsSrc2Insts : SubtargetFeature<"ds-src2-insts",
777  "HasDsSrc2Insts",
778  "true",
779  "Has ds_*_src2 instructions"
780>;
781
782def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
783  "HasVOP3Literal",
784  "true",
785  "Can use one literal in VOP3"
786>;
787
788def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
789  "HasNoDataDepHazard",
790  "true",
791  "Does not need SW waitstates"
792>;
793
794def FeatureGFX11FullVGPRs : SubtargetFeature<"gfx11-full-vgprs",
795  "HasGFX11FullVGPRs",
796  "true",
797  "GFX11 with 50% more physical VGPRs and 50% larger allocation granule than GFX10"
798>;
799
800
801def FeatureVOPD : SubtargetFeature<"vopd",
802  "HasVOPDInsts",
803  "true",
804  "Has VOPD dual issue wave32 instructions"
805>;
806
807def FeatureVALUTransUseHazard : SubtargetFeature<"valu-trans-use-hazard",
808  "HasVALUTransUseHazard",
809  "true",
810  "Hazard when TRANS instructions are closely followed by a use of the result"
811>;
812
813def FeatureForceStoreSC0SC1 : SubtargetFeature<"force-store-sc0-sc1",
814  "HasForceStoreSC0SC1",
815  "true",
816  "Has SC0 and SC1 on stores"
817>;
818
819def FeatureSALUFloatInsts : SubtargetFeature<"salu-float",
820  "HasSALUFloatInsts",
821  "true",
822  "Has SALU floating point instructions"
823>;
824
825def FeatureVGPRSingleUseHintInsts : SubtargetFeature<"vgpr-singleuse-hint",
826  "HasVGPRSingleUseHintInsts",
827  "true",
828  "Has single-use VGPR hint instructions"
829>;
830
831def FeaturePseudoScalarTrans : SubtargetFeature<"pseudo-scalar-trans",
832  "HasPseudoScalarTrans",
833  "true",
834  "Has Pseudo Scalar Transcendental instructions"
835>;
836
837def FeatureHasRestrictedSOffset : SubtargetFeature<"restricted-soffset",
838  "HasRestrictedSOffset",
839  "true",
840  "Has restricted SOffset (immediate not supported)."
841>;
842
843//===------------------------------------------------------------===//
844// Subtarget Features (options and debugging)
845//===------------------------------------------------------------===//
846
847class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
848  "max-private-element-size-"#size,
849  "MaxPrivateElementSize",
850  !cast<string>(size),
851  "Maximum private access size may be "#size
852>;
853
854def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
855def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
856def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
857
858def FeatureDumpCode : SubtargetFeature <"DumpCode",
859  "DumpCode",
860  "true",
861  "Dump MachineInstrs in the CodeEmitter"
862>;
863
864def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
865  "DumpCode",
866  "true",
867  "Dump MachineInstrs in the CodeEmitter"
868>;
869
870// XXX - This should probably be removed once enabled by default
871def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
872  "EnableLoadStoreOpt",
873  "true",
874  "Enable SI load/store optimizer pass"
875>;
876
877// Performance debugging feature. Allow using DS instruction immediate
878// offsets even if the base pointer can't be proven to be base. On SI,
879// base pointer values that won't give the same result as a 16-bit add
880// are not safe to fold, but this will override the conservative test
881// for the base pointer.
882def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
883  "unsafe-ds-offset-folding",
884  "EnableUnsafeDSOffsetFolding",
885  "true",
886  "Force using DS instruction immediate offsets on SI"
887>;
888
889def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
890  "EnableSIScheduler",
891  "true",
892  "Enable SI Machine Scheduler"
893>;
894
895def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
896  "EnableDS128",
897  "true",
898  "Use ds_{read|write}_b128"
899>;
900
901// Sparse texture support requires that all result registers are zeroed when
902// PRTStrictNull is set to true. This feature is turned on for all architectures
903// but is enabled as a feature in case there are situations where PRTStrictNull
904// is disabled by the driver.
905def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
906  "EnablePRTStrictNull",
907  "true",
908  "Enable zeroing of result registers for sparse texture fetches"
909>;
910
911// Unless +-flat-for-global is specified, turn on FlatForGlobal for
912// all OS-es on VI and newer hardware to avoid assertion failures due
913// to missing ADDR64 variants of MUBUF instructions.
914// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
915// instructions.
916
917def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
918  "FlatForGlobal",
919  "true",
920  "Force to generate flat instruction for global"
921>;
922
923def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
924  "auto-waitcnt-before-barrier",
925  "AutoWaitcntBeforeBarrier",
926  "true",
927  "Hardware automatically inserts waitcnt before barrier"
928>;
929
930def FeatureBackOffBarrier : SubtargetFeature <"back-off-barrier",
931  "BackOffBarrier",
932  "true",
933  "Hardware supports backing off s_barrier if an exception occurs"
934>;
935
936def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
937  "HasTrigReducedRange",
938  "true",
939  "Requires use of fract on arguments to trig instructions"
940>;
941
942def FeatureKernargPreload : SubtargetFeature <"kernarg-preload",
943  "KernargPreload",
944  "true",
945  "Hardware supports preloading of kernel arguments in user SGPRs."
946>;
947
948// Alignment enforcement is controlled by a configuration register:
949// SH_MEM_CONFIG.alignment_mode
950def FeatureUnalignedAccessMode : SubtargetFeature<"unaligned-access-mode",
951  "UnalignedAccessMode",
952  "true",
953  "Enable unaligned global, local and region loads and stores if the hardware"
954  " supports it"
955>;
956
957def FeaturePackedTID : SubtargetFeature<"packed-tid",
958  "HasPackedTID",
959  "true",
960  "Workitem IDs are packed into v0 at kernel launch"
961>;
962
963def FeatureArchitectedFlatScratch : SubtargetFeature<"architected-flat-scratch",
964  "HasArchitectedFlatScratch",
965  "true",
966  "Flat Scratch register is a readonly SPI initialized architected register"
967>;
968
969def FeatureArchitectedSGPRs : SubtargetFeature<"architected-sgprs",
970  "HasArchitectedSGPRs",
971  "true",
972  "Enable the architected SGPRs"
973>;
974
975def FeatureGDS : SubtargetFeature<"gds",
976  "HasGDS",
977  "true",
978  "Has Global Data Share"
979>;
980
981def FeatureGWS : SubtargetFeature<"gws",
982  "HasGWS",
983  "true",
984  "Has Global Wave Sync"
985>;
986
987// Dummy feature used to disable assembler instructions.
988def FeatureDisable : SubtargetFeature<"",
989  "FeatureDisable","true",
990  "Dummy feature to disable assembler instructions"
991>;
992
993//===----------------------------------------------------------------------===//
994
995class GCNSubtargetFeatureGeneration <string Value,
996                                     string FeatureName,
997                                     list<SubtargetFeature> Implies> :
998        SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
999
1000def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
1001    "southern-islands",
1002  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
1003  FeatureWavefrontSize64, FeatureSMemTimeInst, FeatureMadMacF32Insts,
1004  FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel,
1005  FeatureTrigReducedRange, FeatureExtendedImageInsts, FeatureImageInsts,
1006  FeatureGDS, FeatureGWS
1007  ]
1008>;
1009
1010def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
1011    "sea-islands",
1012  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
1013  FeatureWavefrontSize64, FeatureFlatAddressSpace,
1014  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
1015  FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
1016  FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureUnalignedBufferAccess,
1017  FeatureImageInsts, FeatureGDS, FeatureGWS
1018  ]
1019>;
1020
1021def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
1022  "volcanic-islands",
1023  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
1024   FeatureWavefrontSize64, FeatureFlatAddressSpace,
1025   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
1026   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
1027   FeatureScalarStores, FeatureInv2PiInlineImm,
1028   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
1029   FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts,
1030   FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
1031   FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureFastDenormalF32,
1032   FeatureUnalignedBufferAccess, FeatureImageInsts, FeatureGDS, FeatureGWS
1033  ]
1034>;
1035
1036def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
1037  "gfx9",
1038  [FeatureFP64, FeatureLocalMemorySize65536,
1039   FeatureWavefrontSize64, FeatureFlatAddressSpace,
1040   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
1041   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
1042   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
1043   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
1044   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
1045   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
1046   FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
1047   FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16,
1048   FeatureA16, FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureSupportsXNACK,
1049   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess,
1050   FeatureNegativeScratchOffsetBug, FeatureGWS
1051  ]
1052>;
1053
1054def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
1055  "gfx10",
1056  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
1057   FeatureFlatAddressSpace,
1058   FeatureCIInsts, Feature16BitInsts,
1059   FeatureSMemRealTime, FeatureInv2PiInlineImm,
1060   FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
1061   FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
1062   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
1063   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
1064   FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
1065   FeatureNoSdstCMPX, FeatureVscnt,
1066   FeatureVOP3Literal, FeatureDPP8, FeatureExtendedImageInsts,
1067   FeatureNoDataDepHazard, FeaturePkFmacF16Inst,
1068   FeatureA16, FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureG16,
1069   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess, FeatureImageInsts,
1070   FeatureGDS, FeatureGWS
1071  ]
1072>;
1073
1074def FeatureGFX11 : GCNSubtargetFeatureGeneration<"GFX11",
1075  "gfx11",
1076  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
1077   FeatureFlatAddressSpace, Feature16BitInsts,
1078   FeatureInv2PiInlineImm, FeatureApertureRegs,
1079   FeatureCIInsts, FeatureGFX8Insts, FeatureGFX9Insts, FeatureGFX10Insts,
1080   FeatureGFX10_AEncoding, FeatureGFX10_BEncoding, FeatureGFX10_3Insts,
1081   FeatureGFX11Insts, FeatureVOP3P, FeatureVOPD, FeatureTrue16BitInsts,
1082   FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
1083   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
1084   FeatureAddNoCarryInsts, FeatureFmaMixInsts,
1085   FeatureNoSdstCMPX, FeatureVscnt,
1086   FeatureVOP3Literal, FeatureDPP8, FeatureExtendedImageInsts,
1087   FeatureNoDataDepHazard, FeaturePkFmacF16Inst,
1088   FeatureA16, FeatureFastDenormalF32, FeatureG16,
1089   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess, FeatureGDS,
1090   FeatureGWS
1091  ]
1092>;
1093
1094def FeatureGFX12 : GCNSubtargetFeatureGeneration<"GFX12",
1095  "gfx12",
1096  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
1097   FeatureFlatAddressSpace, Feature16BitInsts,
1098   FeatureInv2PiInlineImm, FeatureApertureRegs,
1099   FeatureCIInsts, FeatureGFX8Insts, FeatureGFX9Insts, FeatureGFX10Insts,
1100   FeatureGFX10_AEncoding, FeatureGFX10_BEncoding, FeatureGFX10_3Insts,
1101   FeatureGFX11Insts, FeatureGFX12Insts, FeatureVOP3P, FeatureVOPD,
1102   FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
1103   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
1104   FeatureAddNoCarryInsts, FeatureFmaMixInsts,
1105   FeatureNoSdstCMPX, FeatureVscnt,
1106   FeatureVOP3Literal, FeatureDPP8,
1107   FeatureNoDataDepHazard, FeaturePkFmacF16Inst,
1108   FeatureA16, FeatureFastDenormalF32, FeatureG16,
1109   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess,
1110   FeatureTrue16BitInsts
1111  ]
1112>;
1113
1114//===----------------------------------------------------------------------===//
1115
1116class FeatureSet<list<SubtargetFeature> Features_> {
1117  list<SubtargetFeature> Features = Features_;
1118}
1119
1120def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
1121   FeatureFastFMAF32,
1122   HalfRate64Ops,
1123   FeatureLDSBankCount32]>;
1124
1125def FeatureISAVersion6_0_1 : FeatureSet<
1126  [FeatureSouthernIslands,
1127   FeatureLDSBankCount32]>;
1128
1129def FeatureISAVersion6_0_2 : FeatureSet<
1130  [FeatureSouthernIslands,
1131   FeatureLDSBankCount32]>;
1132
1133def FeatureISAVersion7_0_0 : FeatureSet<
1134  [FeatureSeaIslands,
1135   FeatureLDSBankCount32]>;
1136
1137def FeatureISAVersion7_0_1 : FeatureSet<
1138  [FeatureSeaIslands,
1139   HalfRate64Ops,
1140   FeatureLDSBankCount32,
1141   FeatureFastFMAF32]>;
1142
1143def FeatureISAVersion7_0_2 : FeatureSet<
1144  [FeatureSeaIslands,
1145   FeatureLDSBankCount16,
1146   FeatureFastFMAF32]>;
1147
1148def FeatureISAVersion7_0_3 : FeatureSet<
1149  [FeatureSeaIslands,
1150   FeatureLDSBankCount16]>;
1151
1152def FeatureISAVersion7_0_4 : FeatureSet<
1153  [FeatureSeaIslands,
1154   FeatureLDSBankCount32]>;
1155
1156def FeatureISAVersion7_0_5 : FeatureSet<
1157  [FeatureSeaIslands,
1158   FeatureLDSBankCount16]>;
1159
1160def FeatureISAVersion8_0_Common : FeatureSet<
1161  [FeatureVolcanicIslands,
1162   FeatureLDSBankCount32,
1163   FeatureUnpackedD16VMem]>;
1164
1165def FeatureISAVersion8_0_1 : FeatureSet<
1166  !listconcat(FeatureISAVersion8_0_Common.Features,
1167    [FeatureFastFMAF32,
1168     HalfRate64Ops,
1169     FeatureSupportsXNACK])>;
1170
1171def FeatureISAVersion8_0_2 : FeatureSet<
1172  !listconcat(FeatureISAVersion8_0_Common.Features,
1173    [FeatureSGPRInitBug])>;
1174
1175def FeatureISAVersion8_0_3 : FeatureSet<
1176  !listconcat(FeatureISAVersion8_0_Common.Features,
1177    [])>;
1178
1179def FeatureISAVersion8_0_5 : FeatureSet<
1180  !listconcat(FeatureISAVersion8_0_Common.Features,
1181    [FeatureSGPRInitBug])>;
1182
1183def FeatureISAVersion8_1_0 : FeatureSet<
1184  [FeatureVolcanicIslands,
1185   FeatureLDSBankCount16,
1186   FeatureSupportsXNACK,
1187   FeatureImageStoreD16Bug,
1188   FeatureImageGather4D16Bug]>;
1189
1190def FeatureISAVersion9_0_Common : FeatureSet<
1191  [FeatureGFX9,
1192   FeatureLDSBankCount32,
1193   FeatureImageInsts,
1194   FeatureMadMacF32Insts]>;
1195
1196def FeatureISAVersion9_0_MI_Common : FeatureSet<
1197  !listconcat(FeatureISAVersion9_0_Common.Features,
1198    [FeatureFmaMixInsts,
1199     FeatureDLInsts,
1200     FeatureDot1Insts,
1201     FeatureDot2Insts,
1202     FeatureDot3Insts,
1203     FeatureDot4Insts,
1204     FeatureDot5Insts,
1205     FeatureDot6Insts,
1206     FeatureDot7Insts,
1207     FeatureDot10Insts,
1208     FeatureMAIInsts,
1209     FeaturePkFmacF16Inst,
1210     FeatureAtomicFaddNoRtnInsts,
1211     FeatureSupportsSRAMECC])>;
1212
1213def FeatureISAVersion9_0_0 : FeatureSet<
1214  !listconcat(FeatureISAVersion9_0_Common.Features,
1215    [FeatureGDS,
1216     FeatureMadMixInsts,
1217     FeatureDsSrc2Insts,
1218     FeatureExtendedImageInsts,
1219     FeatureImageGather4D16Bug])>;
1220
1221def FeatureISAVersion9_0_2 : FeatureSet<
1222  !listconcat(FeatureISAVersion9_0_Common.Features,
1223    [FeatureGDS,
1224     FeatureMadMixInsts,
1225     FeatureDsSrc2Insts,
1226     FeatureExtendedImageInsts,
1227     FeatureImageGather4D16Bug])>;
1228
1229def FeatureISAVersion9_0_4 : FeatureSet<
1230  !listconcat(FeatureISAVersion9_0_Common.Features,
1231    [FeatureGDS,
1232     FeatureDsSrc2Insts,
1233     FeatureExtendedImageInsts,
1234     FeatureFmaMixInsts,
1235     FeatureImageGather4D16Bug])>;
1236
1237def FeatureISAVersion9_0_6 : FeatureSet<
1238  !listconcat(FeatureISAVersion9_0_Common.Features,
1239    [FeatureGDS,
1240     HalfRate64Ops,
1241     FeatureFmaMixInsts,
1242     FeatureDsSrc2Insts,
1243     FeatureExtendedImageInsts,
1244     FeatureDLInsts,
1245     FeatureDot1Insts,
1246     FeatureDot2Insts,
1247     FeatureDot7Insts,
1248     FeatureDot10Insts,
1249     FeatureSupportsSRAMECC,
1250     FeatureImageGather4D16Bug])>;
1251
1252def FeatureISAVersion9_0_8 : FeatureSet<
1253  !listconcat(FeatureISAVersion9_0_MI_Common.Features,
1254    [FeatureGDS,
1255     HalfRate64Ops,
1256     FeatureDsSrc2Insts,
1257     FeatureExtendedImageInsts,
1258     FeatureAtomicBufferGlobalPkAddF16NoRtnInsts,
1259     FeatureMFMAInlineLiteralBug,
1260     FeatureImageGather4D16Bug])>;
1261
1262def FeatureISAVersion9_0_9 : FeatureSet<
1263  !listconcat(FeatureISAVersion9_0_Common.Features,
1264    [FeatureGDS,
1265     FeatureMadMixInsts,
1266     FeatureDsSrc2Insts,
1267     FeatureExtendedImageInsts,
1268     FeatureImageInsts,
1269     FeatureImageGather4D16Bug])>;
1270
1271def FeatureISAVersion9_0_A : FeatureSet<
1272  !listconcat(FeatureISAVersion9_0_MI_Common.Features,
1273    [FeatureGFX90AInsts,
1274     FeatureFmacF64Inst,
1275     FeatureDPALU_DPP,
1276     FeaturePackedFP32Ops,
1277     FeatureAtomicFaddRtnInsts,
1278     FeatureAtomicBufferGlobalPkAddF16Insts,
1279     FeaturePackedTID,
1280     FullRate64Ops,
1281     FeatureBackOffBarrier,
1282     FeatureKernargPreload])>;
1283
1284def FeatureISAVersion9_0_C : FeatureSet<
1285  !listconcat(FeatureISAVersion9_0_Common.Features,
1286    [FeatureGDS,
1287     FeatureMadMixInsts,
1288     FeatureDsSrc2Insts,
1289     FeatureExtendedImageInsts,
1290     FeatureImageGather4D16Bug])>;
1291
1292def FeatureISAVersion9_4_Common : FeatureSet<
1293  [FeatureGFX9,
1294   FeatureGFX90AInsts,
1295   FeatureGFX940Insts,
1296   FeatureFmaMixInsts,
1297   FeatureLDSBankCount32,
1298   FeatureDLInsts,
1299   FeatureFmacF64Inst,
1300   FeatureDot1Insts,
1301   FeatureDot2Insts,
1302   FeatureDot3Insts,
1303   FeatureDot4Insts,
1304   FeatureDot5Insts,
1305   FeatureDot6Insts,
1306   FeatureDot7Insts,
1307   FeatureDot10Insts,
1308   FeatureAtomicDsPkAdd16Insts,
1309   FeatureAtomicFlatPkAdd16Insts,
1310   FeatureDPALU_DPP,
1311   FeaturePackedFP32Ops,
1312   FeatureMAIInsts,
1313   FeatureFP8Insts,
1314   FeaturePkFmacF16Inst,
1315   FeatureAtomicFaddRtnInsts,
1316   FeatureAtomicFaddNoRtnInsts,
1317   FeatureAtomicBufferGlobalPkAddF16Insts,
1318   FeatureAtomicGlobalPkAddBF16Inst,
1319   FeatureFlatAtomicFaddF32Inst,
1320   FeatureSupportsSRAMECC,
1321   FeaturePackedTID,
1322   FeatureArchitectedFlatScratch,
1323   FullRate64Ops,
1324   FeatureBackOffBarrier,
1325   FeatureKernargPreload]>;
1326
1327def FeatureISAVersion9_4_0 : FeatureSet<
1328  !listconcat(FeatureISAVersion9_4_Common.Features,
1329    [FeatureForceStoreSC0SC1])>;
1330
1331def FeatureISAVersion9_4_1 : FeatureSet<
1332  !listconcat(FeatureISAVersion9_4_Common.Features,
1333    [FeatureForceStoreSC0SC1])>;
1334
1335def FeatureISAVersion9_4_2 : FeatureSet<
1336  !listconcat(FeatureISAVersion9_4_Common.Features,
1337    [])>;
1338
1339def FeatureISAVersion10_Common : FeatureSet<
1340  [FeatureGFX10,
1341   FeatureLDSBankCount32,
1342   FeatureDLInsts,
1343   FeatureNSAEncoding,
1344   FeatureWavefrontSize32,
1345   FeatureBackOffBarrier]>;
1346
1347def FeatureISAVersion10_1_Common : FeatureSet<
1348  !listconcat(FeatureISAVersion10_Common.Features,
1349    [FeatureScalarStores,
1350     FeatureScalarAtomics,
1351     FeatureScalarFlatScratchInsts,
1352     FeatureGetWaveIdInst,
1353     FeatureMadMacF32Insts,
1354     FeatureDsSrc2Insts,
1355     FeatureLdsMisalignedBug,
1356     FeatureSupportsXNACK,
1357     // gfx101x bugs
1358     FeatureVcmpxPermlaneHazard,
1359     FeatureVMEMtoScalarWriteHazard,
1360     FeatureSMEMtoVectorWriteHazard,
1361     FeatureInstFwdPrefetchBug,
1362     FeatureVcmpxExecWARHazard,
1363     FeatureLdsBranchVmemWARHazard,
1364     FeatureNSAtoVMEMBug,
1365     FeatureNSAClauseBug,
1366     FeatureOffset3fBug,
1367     FeatureFlatSegmentOffsetBug,
1368     FeatureNegativeUnalignedScratchOffsetBug])>;
1369
1370def FeatureISAVersion10_1_0 : FeatureSet<
1371  !listconcat(FeatureISAVersion10_1_Common.Features,
1372    [])>;
1373
1374def FeatureISAVersion10_1_1 : FeatureSet<
1375  !listconcat(FeatureISAVersion10_1_Common.Features,
1376    [FeatureDot1Insts,
1377     FeatureDot2Insts,
1378     FeatureDot5Insts,
1379     FeatureDot6Insts,
1380     FeatureDot7Insts,
1381     FeatureDot10Insts])>;
1382
1383def FeatureISAVersion10_1_2 : FeatureSet<
1384  !listconcat(FeatureISAVersion10_1_Common.Features,
1385    [FeatureDot1Insts,
1386     FeatureDot2Insts,
1387     FeatureDot5Insts,
1388     FeatureDot6Insts,
1389     FeatureDot7Insts,
1390     FeatureDot10Insts])>;
1391
1392def FeatureISAVersion10_1_3 : FeatureSet<
1393  !listconcat(FeatureISAVersion10_1_Common.Features,
1394    [FeatureGFX10_AEncoding])>;
1395
1396def FeatureISAVersion10_3_0 : FeatureSet<
1397  !listconcat(FeatureISAVersion10_Common.Features,
1398    [FeatureGFX10_AEncoding,
1399     FeatureGFX10_BEncoding,
1400     FeatureGFX10_3Insts,
1401     FeatureDot1Insts,
1402     FeatureDot2Insts,
1403     FeatureDot5Insts,
1404     FeatureDot6Insts,
1405     FeatureDot7Insts,
1406     FeatureDot10Insts,
1407     FeatureShaderCyclesRegister])>;
1408
1409def FeatureISAVersion11_Common : FeatureSet<
1410  [FeatureGFX11,
1411   FeatureLDSBankCount32,
1412   FeatureDLInsts,
1413   FeatureDot5Insts,
1414   FeatureDot7Insts,
1415   FeatureDot8Insts,
1416   FeatureDot9Insts,
1417   FeatureDot10Insts,
1418   FeatureNSAEncoding,
1419   FeaturePartialNSAEncoding,
1420   FeatureWavefrontSize32,
1421   FeatureShaderCyclesRegister,
1422   FeatureArchitectedFlatScratch,
1423   FeatureAtomicFaddRtnInsts,
1424   FeatureAtomicFaddNoRtnInsts,
1425   FeatureFlatAtomicFaddF32Inst,
1426   FeatureImageInsts,
1427   FeaturePackedTID,
1428   FeatureVcmpxPermlaneHazard,
1429   FeatureMADIntraFwdBug]>;
1430
1431def FeatureISAVersion11_0_Common : FeatureSet<
1432  !listconcat(FeatureISAVersion11_Common.Features,
1433    [FeatureMSAALoadDstSelBug,
1434     FeatureVALUTransUseHazard])>;
1435
1436def FeatureISAVersion11_0_0 : FeatureSet<
1437  !listconcat(FeatureISAVersion11_0_Common.Features,
1438    [FeatureGFX11FullVGPRs,
1439     FeatureUserSGPRInit16Bug])>;
1440
1441def FeatureISAVersion11_0_1 : FeatureSet<
1442  !listconcat(FeatureISAVersion11_0_Common.Features,
1443    [FeatureGFX11FullVGPRs])>;
1444
1445def FeatureISAVersion11_0_2 : FeatureSet<
1446  !listconcat(FeatureISAVersion11_0_Common.Features,
1447    [FeatureUserSGPRInit16Bug])>;
1448
1449def FeatureISAVersion11_0_3 : FeatureSet<
1450  !listconcat(FeatureISAVersion11_0_Common.Features,
1451    [])>;
1452
1453def FeatureISAVersion11_5_0 : FeatureSet<
1454  !listconcat(FeatureISAVersion11_Common.Features,
1455    [FeatureSALUFloatInsts,
1456     FeatureDPPSrc1SGPR,
1457     FeatureVGPRSingleUseHintInsts])>;
1458
1459def FeatureISAVersion11_5_1 : FeatureSet<
1460  !listconcat(FeatureISAVersion11_Common.Features,
1461    [FeatureSALUFloatInsts,
1462     FeatureDPPSrc1SGPR,
1463     FeatureVGPRSingleUseHintInsts,
1464     FeatureGFX11FullVGPRs])>;
1465
1466def FeatureISAVersion12 : FeatureSet<
1467  [FeatureGFX12,
1468   FeatureLDSBankCount32,
1469   FeatureDLInsts,
1470   FeatureDot5Insts,
1471   FeatureDot7Insts,
1472   FeatureDot8Insts,
1473   FeatureDot9Insts,
1474   FeatureDot10Insts,
1475   FeatureNSAEncoding,
1476   FeaturePartialNSAEncoding,
1477   FeatureWavefrontSize32,
1478   FeatureShaderCyclesHiLoRegisters,
1479   FeatureArchitectedFlatScratch,
1480   FeatureAtomicFaddRtnInsts,
1481   FeatureAtomicFaddNoRtnInsts,
1482   FeatureFlatAtomicFaddF32Inst,
1483   FeatureImageInsts,
1484   FeatureExtendedImageInsts,
1485   FeaturePackedTID,
1486   FeatureVcmpxPermlaneHazard,
1487   FeatureSALUFloatInsts,
1488   FeaturePseudoScalarTrans,
1489   FeatureHasRestrictedSOffset,
1490   FeatureVGPRSingleUseHintInsts,
1491   FeatureMADIntraFwdBug,
1492   FeatureScalarDwordx3Loads]>;
1493
1494//===----------------------------------------------------------------------===//
1495
1496def AMDGPUInstrInfo : InstrInfo {
1497  let guessInstructionProperties = 1;
1498}
1499
1500def AMDGPUAsmParser : AsmParser {
1501  // Some of the R600 registers have the same name, so this crashes.
1502  // For example T0_XYZW and T0_XY both have the asm name T0.
1503  let ShouldEmitMatchRegisterName = 0;
1504
1505  // Call the custom operand parser for all operands.
1506  let OperandParserMethod = "parseCustomOperand";
1507  let CallCustomParserForAllOperands = true;
1508}
1509
1510def AMDGPUAsmWriter : AsmWriter {
1511  int PassSubtarget = 1;
1512}
1513
1514def AMDGPUAsmVariants {
1515  string Default = "Default";
1516  int Default_ID = 0;
1517  string VOP3 = "VOP3";
1518  int VOP3_ID = 1;
1519  string SDWA = "SDWA";
1520  int SDWA_ID = 2;
1521  string SDWA9 = "SDWA9";
1522  int SDWA9_ID = 3;
1523  string DPP = "DPP";
1524  int DPP_ID = 4;
1525  string VOP3_DPP = "VOP3_DPP";
1526  int VOP3_DPP_ID = 5;
1527  string Disable = "Disable";
1528  int Disable_ID = 6;
1529}
1530
1531def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
1532  let Variant = AMDGPUAsmVariants.Default_ID;
1533  let Name = AMDGPUAsmVariants.Default;
1534}
1535
1536def VOP3AsmParserVariant : AsmParserVariant {
1537  let Variant = AMDGPUAsmVariants.VOP3_ID;
1538  let Name = AMDGPUAsmVariants.VOP3;
1539}
1540
1541def SDWAAsmParserVariant : AsmParserVariant {
1542  let Variant = AMDGPUAsmVariants.SDWA_ID;
1543  let Name = AMDGPUAsmVariants.SDWA;
1544}
1545
1546def SDWA9AsmParserVariant : AsmParserVariant {
1547  let Variant = AMDGPUAsmVariants.SDWA9_ID;
1548  let Name = AMDGPUAsmVariants.SDWA9;
1549}
1550
1551def DPPAsmParserVariant : AsmParserVariant {
1552  let Variant = AMDGPUAsmVariants.DPP_ID;
1553  let Name = AMDGPUAsmVariants.DPP;
1554}
1555
1556def VOP3_DPPAsmParserVariant : AsmParserVariant {
1557  let Variant = AMDGPUAsmVariants.VOP3_DPP_ID;
1558  let Name = AMDGPUAsmVariants.VOP3_DPP;
1559}
1560
1561def AMDGPU : Target {
1562  // Pull in Instruction Info:
1563  let InstructionSet = AMDGPUInstrInfo;
1564  let AssemblyParsers = [AMDGPUAsmParser];
1565  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
1566                                VOP3AsmParserVariant,
1567                                SDWAAsmParserVariant,
1568                                SDWA9AsmParserVariant,
1569                                DPPAsmParserVariant,
1570                                VOP3_DPPAsmParserVariant];
1571  let AssemblyWriters = [AMDGPUAsmWriter];
1572  let AllowRegisterRenaming = 1;
1573}
1574
1575// Dummy Instruction itineraries for pseudo instructions
1576def ALU_NULL : FuncUnit;
1577def NullALU : InstrItinClass;
1578
1579//===----------------------------------------------------------------------===//
1580// Predicate helper class
1581//===----------------------------------------------------------------------===//
1582
1583def isGFX6 :
1584  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
1585  AssemblerPredicate<(all_of FeatureSouthernIslands)>;
1586
1587def isGFX6GFX7 :
1588  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1589            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1590  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX10Insts))>;
1591
1592def isGFX6GFX7GFX10 :
1593  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1594            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1595            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1596  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX11Insts))>;
1597
1598def isGFX6GFX7GFX10Plus :
1599  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1600            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1601            "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1602  AssemblerPredicate<(all_of (not FeatureGCN3Encoding))>;
1603
1604def isGFX7Only :
1605  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1606  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX10Insts))>;
1607
1608def isGFX7GFX10 :
1609  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1610            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1611  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX11Insts))>;
1612
1613def isGFX7GFX10GFX11 :
1614  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1615            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 ||"
1616            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX11">,
1617  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>;
1618
1619def isGFX7GFX8GFX9 :
1620  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1621            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1622            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1623  AssemblerPredicate<(all_of FeatureGFX7GFX8GFX9Insts)>;
1624
1625def isGFX6GFX7GFX8GFX9 :
1626  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1627            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1628            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1629            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1630  AssemblerPredicate<(all_of (not FeatureGFX10Insts))>;
1631
1632def isGFX6GFX7GFX8GFX9NotGFX90A :
1633  Predicate<"!Subtarget->hasGFX90AInsts() &&"
1634            "(Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1635            " Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1636            " Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1637            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1638  AssemblerPredicate<(all_of (not FeatureGFX10Insts), (not FeatureGFX90AInsts))>;
1639
1640def isGFX6GFX7GFX8GFX9GFX10 :
1641  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1642            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1643            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1644            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9 ||"
1645            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1646  AssemblerPredicate<(all_of (not FeatureGFX11Insts))>;
1647
1648def isNotGFX12Plus :
1649  Predicate<"Subtarget->getGeneration() <= AMDGPUSubtarget::GFX11">,
1650  AssemblerPredicate<(all_of (not FeatureGFX12Insts))>;
1651
1652def isGFX7GFX8GFX9GFX10 :
1653  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1654            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1655            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9 ||"
1656            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1657  AssemblerPredicate<(all_of FeatureCIInsts, (not FeatureGFX11Insts))>;
1658
1659def isGFX8GFX9GFX10GFX11 :
1660  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1661            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9 ||"
1662            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 ||"
1663            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX11">,
1664  AssemblerPredicate<(all_of FeatureGFX8Insts, (not FeatureGFX12Insts))>;
1665
1666def isGFX7Plus :
1667  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
1668  AssemblerPredicate<(all_of FeatureCIInsts)>;
1669
1670def isGFX8Plus :
1671  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1672  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1673
1674def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
1675                           "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1676  AssemblerPredicate <(all_of FeatureVolcanicIslands)>;
1677
1678def isGFX9Plus :
1679  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1680  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1681
1682def isNotGFX9Plus :
1683  Predicate<"Subtarget->getGeneration() < AMDGPUSubtarget::GFX9">;
1684
1685def isGFX9Only : Predicate <
1686  "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1687  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts)>;
1688
1689def isGCN3ExcludingGFX90A :
1690  Predicate<"Subtarget->isGCN3Encoding() && !Subtarget->hasGFX90AInsts()">,
1691  AssemblerPredicate<(all_of FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1692
1693def isGFX90APlus :
1694  Predicate<"Subtarget->hasGFX90AInsts()">,
1695  AssemblerPredicate<(all_of FeatureGFX90AInsts)>;
1696
1697def isNotGFX90APlus :
1698  Predicate<"!Subtarget->hasGFX90AInsts()">,
1699  AssemblerPredicate<(all_of (not FeatureGFX90AInsts))>;
1700
1701def isGFX8GFX9NotGFX90A :
1702  Predicate<"!Subtarget->hasGFX90AInsts() &&"
1703            "(Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1704            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1705  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1706
1707def isGFX90AOnly :
1708  Predicate<"Subtarget->hasGFX90AInsts() && !Subtarget->hasGFX940Insts()">,
1709  AssemblerPredicate<(all_of FeatureGFX90AInsts, (not FeatureGFX940Insts))>;
1710
1711def isGFX908orGFX90A :
1712  Predicate<"Subtarget->hasMAIInsts() && !Subtarget->hasGFX940Insts()">,
1713  AssemblerPredicate<(all_of FeatureMAIInsts, (not FeatureGFX940Insts))>;
1714
1715def isGFX940Plus :
1716  Predicate<"Subtarget->hasGFX940Insts()">,
1717  AssemblerPredicate<(all_of FeatureGFX940Insts)>;
1718
1719def isGFX8GFX9NotGFX940 :
1720  Predicate<"!Subtarget->hasGFX940Insts() &&"
1721            "(Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1722            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1723  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding, (not FeatureGFX940Insts))>;
1724
1725def isGFX8GFX9 :
1726  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1727            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1728  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>;
1729
1730def isGFX10Only :
1731  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1732  AssemblerPredicate<(all_of FeatureGFX10Insts, (not FeatureGFX11Insts))>;
1733
1734def isGFX10Plus :
1735  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1736  AssemblerPredicate<(all_of FeatureGFX10Insts)>;
1737
1738def isGFX10GFX11 :
1739  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 ||"
1740            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX11">,
1741  AssemblerPredicate<(all_of FeatureGFX10Insts, (not FeatureGFX12Insts))>;
1742
1743def isGFX10Before1030 :
1744  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 &&"
1745            "!Subtarget->hasGFX10_3Insts()">,
1746  AssemblerPredicate<(all_of FeatureGFX10Insts,(not FeatureGFX10_3Insts))>;
1747
1748def isGFX9GFX10 :
1749  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX9 ||"
1750            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1751  AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureGFX11Insts))>;
1752
1753def isGFX8GFX9GFX10 :
1754  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1755            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9 ||"
1756            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1757  AssemblerPredicate<(all_of FeatureGFX8Insts, (not FeatureGFX11Insts))>;
1758
1759def isGFX11Only :
1760  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX11">,
1761  AssemblerPredicate<(all_of FeatureGFX11Insts, (not FeatureGFX12Insts))>;
1762
1763def isGFX11Plus :
1764  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX11">,
1765  AssemblerPredicate<(all_of FeatureGFX11Insts)>;
1766
1767def isGFX12Only :
1768  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX12">,
1769  AssemblerPredicate<(all_of FeatureGFX12Insts)>;
1770
1771def isGFX12Plus :
1772  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12">,
1773  AssemblerPredicate<(all_of FeatureGFX12Insts)>;
1774
1775def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
1776  AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
1777
1778def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
1779  AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>;
1780def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
1781  AssemblerPredicate<(all_of FeatureFlatScratchInsts)>;
1782def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
1783  AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>;
1784def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
1785  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1786
1787def HasFlatScratchSTMode : Predicate<"Subtarget->hasFlatScratchSTMode()">,
1788  AssemblerPredicate<(any_of FeatureGFX10_3Insts, FeatureGFX940Insts)>;
1789def HasFlatScratchSVSMode : Predicate<"Subtarget->hasFlatScratchSVSMode()">,
1790  AssemblerPredicate<(any_of FeatureGFX940Insts, FeatureGFX11Insts)>;
1791
1792def HasGFX10_AEncoding : Predicate<"Subtarget->hasGFX10_AEncoding()">,
1793  AssemblerPredicate<(all_of FeatureGFX10_AEncoding)>;
1794
1795def HasGFX10_BEncoding : Predicate<"Subtarget->hasGFX10_BEncoding()">,
1796  AssemblerPredicate<(all_of FeatureGFX10_BEncoding)>;
1797
1798def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
1799  AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>;
1800def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
1801  AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>;
1802
1803def HasRestrictedSOffset : Predicate<"Subtarget->hasRestrictedSOffset()">,
1804  AssemblerPredicate<(all_of FeatureHasRestrictedSOffset)>;
1805def HasUnrestrictedSOffset : Predicate<"!Subtarget->hasRestrictedSOffset()">,
1806  AssemblerPredicate<(all_of (not FeatureHasRestrictedSOffset))>;
1807
1808def D16PreservesUnusedBits :
1809  Predicate<"Subtarget->d16PreservesUnusedBits()">,
1810  AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>;
1811
1812def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
1813def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
1814
1815def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1816  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1817
1818def HasLDSFPAtomicAdd : Predicate<"Subtarget->hasLDSFPAtomicAdd()">,
1819  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1820
1821def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
1822  AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>;
1823
1824def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
1825
1826def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
1827  AssemblerPredicate<(all_of Feature16BitInsts)>;
1828
1829def HasTrue16BitInsts : Predicate<"Subtarget->hasTrue16BitInsts()">,
1830  AssemblerPredicate<(all_of FeatureTrue16BitInsts)>;
1831def NotHasTrue16BitInsts : Predicate<"!Subtarget->hasTrue16BitInsts()">;
1832
1833// Control use of True16 instructions. The real True16 instructions are
1834// True16 instructions as they are defined in the ISA. Fake True16
1835// instructions have the same encoding as real ones but syntactically
1836// only allow 32-bit registers in operands and use low halves thereof.
1837def UseRealTrue16Insts : Predicate<"Subtarget->useRealTrue16Insts()">,
1838  AssemblerPredicate<(all_of FeatureTrue16BitInsts, FeatureRealTrue16Insts)>;
1839def UseFakeTrue16Insts : Predicate<"Subtarget->hasTrue16BitInsts() && "
1840                                   "!Subtarget->useRealTrue16Insts()">;
1841
1842def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
1843  AssemblerPredicate<(all_of FeatureVOP3P)>;
1844
1845def NotHasMed3_16 : Predicate<"!Subtarget->hasMed3_16()">;
1846
1847def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">;
1848def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">;
1849
1850def HasFminFmaxLegacy : Predicate<"Subtarget->hasFminFmaxLegacy()">;
1851
1852def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
1853  AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
1854
1855def HasSDWA9 :
1856  Predicate<"Subtarget->hasSDWA()">,
1857  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>;
1858
1859def HasSDWA10 :
1860  Predicate<"Subtarget->hasSDWA()">,
1861  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureSDWA)>;
1862
1863def HasDPP : Predicate<"Subtarget->hasDPP()">,
1864  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>;
1865
1866def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
1867  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>;
1868
1869def HasDPALU_DPP : Predicate<"Subtarget->hasDPALU_DPP()">,
1870  AssemblerPredicate<(all_of FeatureDPALU_DPP)>;
1871
1872def HasPackedFP32Ops : Predicate<"Subtarget->hasPackedFP32Ops()">,
1873  AssemblerPredicate<(all_of FeaturePackedFP32Ops)>;
1874
1875def HasPkMovB32 : Predicate<"Subtarget->hasPkMovB32()">,
1876  AssemblerPredicate<(all_of FeatureGFX90AInsts)>;
1877
1878def HasFmaakFmamkF32Insts :
1879  Predicate<"Subtarget->hasFmaakFmamkF32Insts()">,
1880  AssemblerPredicate<(any_of FeatureGFX10Insts, FeatureGFX940Insts)>;
1881
1882def HasImageInsts : Predicate<"Subtarget->hasImageInsts()">,
1883  AssemblerPredicate<(all_of FeatureImageInsts)>;
1884
1885def HasExtendedImageInsts : Predicate<"Subtarget->hasExtendedImageInsts()">,
1886  AssemblerPredicate<(all_of FeatureExtendedImageInsts)>;
1887
1888def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
1889  AssemblerPredicate<(all_of FeatureR128A16)>;
1890
1891def HasA16 : Predicate<"Subtarget->hasA16()">,
1892  AssemblerPredicate<(all_of FeatureA16)>;
1893
1894def HasG16 : Predicate<"Subtarget->hasG16()">,
1895  AssemblerPredicate<(all_of FeatureG16)>;
1896
1897def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
1898  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP)>;
1899
1900def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
1901  AssemblerPredicate<(all_of FeatureIntClamp)>;
1902
1903def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
1904  AssemblerPredicate<(all_of FeatureMadMixInsts)>;
1905
1906def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
1907  AssemblerPredicate<(all_of FeatureScalarStores)>;
1908
1909def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
1910  AssemblerPredicate<(all_of FeatureScalarAtomics)>;
1911
1912def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
1913  AssemblerPredicate<(all_of FeatureNoSdstCMPX)>;
1914
1915def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
1916  AssemblerPredicate<(all_of (not FeatureNoSdstCMPX))>;
1917
1918def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
1919def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
1920def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
1921                      AssemblerPredicate<(all_of FeatureVGPRIndexMode)>;
1922def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
1923                AssemblerPredicate<(all_of FeatureMovrel)>;
1924
1925def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
1926  AssemblerPredicate<(all_of FeatureFmaMixInsts)>;
1927
1928def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
1929  AssemblerPredicate<(all_of FeatureDLInsts)>;
1930
1931def HasFmacF64Inst : Predicate<"Subtarget->hasFmacF64Inst()">,
1932  AssemblerPredicate<(all_of FeatureFmacF64Inst)>;
1933
1934def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
1935  AssemblerPredicate<(all_of FeatureDot1Insts)>;
1936
1937def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
1938  AssemblerPredicate<(all_of FeatureDot2Insts)>;
1939
1940def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">,
1941  AssemblerPredicate<(all_of FeatureDot3Insts)>;
1942
1943def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">,
1944  AssemblerPredicate<(all_of FeatureDot4Insts)>;
1945
1946def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
1947  AssemblerPredicate<(all_of FeatureDot5Insts)>;
1948
1949def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
1950  AssemblerPredicate<(all_of FeatureDot6Insts)>;
1951
1952def HasDot7Insts : Predicate<"Subtarget->hasDot7Insts()">,
1953  AssemblerPredicate<(all_of FeatureDot7Insts)>;
1954
1955def HasDot8Insts : Predicate<"Subtarget->hasDot8Insts()">,
1956  AssemblerPredicate<(all_of FeatureDot8Insts)>;
1957
1958def HasDot9Insts : Predicate<"Subtarget->hasDot9Insts()">,
1959  AssemblerPredicate<(all_of FeatureDot9Insts)>;
1960
1961def HasDot10Insts : Predicate<"Subtarget->hasDot10Insts()">,
1962  AssemblerPredicate<(all_of FeatureDot10Insts)>;
1963
1964def HasGetWaveIdInst : Predicate<"Subtarget->hasGetWaveIdInst()">,
1965  AssemblerPredicate<(all_of FeatureGetWaveIdInst)>;
1966
1967def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
1968  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1969
1970def HasSMemRealTime : Predicate<"Subtarget->hasSMemRealTime()">,
1971  AssemblerPredicate<(all_of FeatureSMemRealTime)>;
1972
1973def HasSMemTimeInst : Predicate<"Subtarget->hasSMemTimeInst()">,
1974  AssemblerPredicate<(all_of FeatureSMemTimeInst)>;
1975
1976def HasShaderCyclesRegister : Predicate<"Subtarget->hasShaderCyclesRegister()">,
1977  AssemblerPredicate<(all_of FeatureShaderCyclesRegister)>;
1978
1979def HasShaderCyclesHiLoRegisters : Predicate<"Subtarget->hasShaderCyclesHiLoRegisters()">;
1980
1981def HasFP8Insts : Predicate<"Subtarget->hasFP8Insts()">,
1982  AssemblerPredicate<(all_of FeatureFP8Insts)>;
1983
1984def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">,
1985  AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>;
1986
1987def HasMadMacF32Insts : Predicate<"Subtarget->hasMadMacF32Insts()">,
1988  AssemblerPredicate<(all_of FeatureMadMacF32Insts)>;
1989
1990def HasFmaLegacy32 : Predicate<"Subtarget->hasGFX10_3Insts()">,
1991  AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1992
1993def HasAtomicDsPkAdd16Insts : Predicate<"Subtarget->hasAtomicDsPkAdd16Insts()">,
1994  AssemblerPredicate<(any_of FeatureAtomicDsPkAdd16Insts)>;
1995
1996def HasAtomicFlatPkAdd16Insts : Predicate<"Subtarget->hasAtomicFlatPkAdd16Insts()">,
1997  AssemblerPredicate<(any_of FeatureAtomicFlatPkAdd16Insts)>;
1998
1999def HasAtomicFaddRtnInsts : Predicate<"Subtarget->hasAtomicFaddRtnInsts()">,
2000  AssemblerPredicate<(all_of FeatureAtomicFaddRtnInsts)>;
2001def HasAtomicFaddNoRtnInsts : Predicate<"Subtarget->hasAtomicFaddNoRtnInsts()">,
2002  AssemblerPredicate<(all_of FeatureAtomicFaddNoRtnInsts)>;
2003def HasAtomicBufferGlobalPkAddF16NoRtnInsts
2004  : Predicate<"Subtarget->hasAtomicBufferGlobalPkAddF16NoRtnInsts() || Subtarget->hasAtomicBufferGlobalPkAddF16Insts()">,
2005  AssemblerPredicate<(any_of FeatureAtomicBufferGlobalPkAddF16NoRtnInsts, FeatureAtomicBufferGlobalPkAddF16Insts)>;
2006def HasAtomicBufferGlobalPkAddF16Insts
2007  : Predicate<"Subtarget->hasAtomicBufferGlobalPkAddF16Insts()">,
2008  AssemblerPredicate<(all_of FeatureAtomicBufferGlobalPkAddF16Insts)>;
2009def HasAtomicGlobalPkAddBF16Inst
2010  : Predicate<"Subtarget->hasAtomicGlobalPkAddBF16Inst()">,
2011  AssemblerPredicate<(all_of FeatureAtomicGlobalPkAddBF16Inst)>;
2012def HasFlatAtomicFaddF32Inst
2013  : Predicate<"Subtarget->hasFlatAtomicFaddF32Inst()">,
2014  AssemblerPredicate<(all_of FeatureFlatAtomicFaddF32Inst)>;
2015
2016def HasDsSrc2Insts : Predicate<"!Subtarget->hasDsSrc2Insts()">,
2017  AssemblerPredicate<(all_of FeatureDsSrc2Insts)>;
2018
2019def EnableLateCFGStructurize : Predicate<
2020  "EnableLateStructurizeCFG">;
2021
2022def EnableFlatScratch : Predicate<"Subtarget->enableFlatScratch()">;
2023
2024def DisableFlatScratch : Predicate<"!Subtarget->enableFlatScratch()">;
2025
2026def HasUnalignedAccessMode : Predicate<"Subtarget->hasUnalignedAccessMode()">,
2027  AssemblerPredicate<(all_of FeatureUnalignedAccessMode)>;
2028
2029def HasMADIntraFwdBug : Predicate<"Subtarget->hasMADIntraFwdBug()">;
2030
2031def HasNotMADIntraFwdBug : Predicate<"!Subtarget->hasMADIntraFwdBug()">;
2032
2033def HasSALUFloatInsts : Predicate<"Subtarget->hasSALUFloatInsts()">,
2034  AssemblerPredicate<(all_of FeatureSALUFloatInsts)>;
2035
2036def HasVGPRSingleUseHintInsts : Predicate<"Subtarget->hasVGPRSingleUseHintInsts()">,
2037  AssemblerPredicate<(all_of FeatureVGPRSingleUseHintInsts)>;
2038
2039def HasPseudoScalarTrans : Predicate<"Subtarget->hasPseudoScalarTrans()">,
2040  AssemblerPredicate<(all_of FeaturePseudoScalarTrans)>;
2041
2042def HasGDS : Predicate<"Subtarget->hasGDS()">;
2043
2044def HasGWS : Predicate<"Subtarget->hasGWS()">;
2045
2046def HasCvtFP8VOP1Bug : Predicate<"Subtarget->hasCvtFP8VOP1Bug()">;
2047def HasNoCvtFP8VOP1Bug : Predicate<"!Subtarget->hasCvtFP8VOP1Bug()">;
2048
2049def HasAtomicCSubNoRtnInsts : Predicate<"Subtarget->hasAtomicCSubNoRtnInsts()">;
2050
2051def HasScalarDwordx3Loads : Predicate<"Subtarget->hasScalarDwordx3Loads()">;
2052
2053// Include AMDGPU TD files
2054include "SISchedule.td"
2055include "GCNProcessors.td"
2056include "AMDGPUInstrInfo.td"
2057include "SIRegisterInfo.td"
2058include "AMDGPURegisterBanks.td"
2059include "AMDGPUInstructions.td"
2060include "SIInstrInfo.td"
2061include "AMDGPUCallingConv.td"
2062include "AMDGPUSearchableTables.td"
2063