1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 /// \file 8 //===----------------------------------------------------------------------===// 9 10 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 11 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 12 13 #include "llvm/Target/TargetMachine.h" 14 15 namespace llvm { 16 17 class AMDGPUTargetMachine; 18 class FunctionPass; 19 class GCNTargetMachine; 20 class ModulePass; 21 class Pass; 22 class Target; 23 class TargetMachine; 24 class TargetOptions; 25 class PassRegistry; 26 class Module; 27 28 // R600 Passes 29 FunctionPass *createR600VectorRegMerger(); 30 FunctionPass *createR600ExpandSpecialInstrsPass(); 31 FunctionPass *createR600EmitClauseMarkers(); 32 FunctionPass *createR600ClauseMergePass(); 33 FunctionPass *createR600Packetizer(); 34 FunctionPass *createR600ControlFlowFinalizer(); 35 FunctionPass *createAMDGPUCFGStructurizerPass(); 36 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel); 37 38 // SI Passes 39 FunctionPass *createGCNDPPCombinePass(); 40 FunctionPass *createSIAnnotateControlFlowPass(); 41 FunctionPass *createSIFoldOperandsPass(); 42 FunctionPass *createSIPeepholeSDWAPass(); 43 FunctionPass *createSILowerI1CopiesPass(); 44 FunctionPass *createSIFixupVectorISelPass(); 45 FunctionPass *createSIAddIMGInitPass(); 46 FunctionPass *createSIShrinkInstructionsPass(); 47 FunctionPass *createSILoadStoreOptimizerPass(); 48 FunctionPass *createSIWholeQuadModePass(); 49 FunctionPass *createSIFixControlFlowLiveIntervalsPass(); 50 FunctionPass *createSIOptimizeExecMaskingPreRAPass(); 51 FunctionPass *createSIFixSGPRCopiesPass(); 52 FunctionPass *createSIMemoryLegalizerPass(); 53 FunctionPass *createSIInsertWaitcntsPass(); 54 FunctionPass *createSIPreAllocateWWMRegsPass(); 55 FunctionPass *createSIFormMemoryClausesPass(); 56 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetOptions &, 57 const TargetMachine *); 58 FunctionPass *createAMDGPUUseNativeCallsPass(); 59 FunctionPass *createAMDGPUCodeGenPreparePass(); 60 FunctionPass *createAMDGPUMachineCFGStructurizerPass(); 61 FunctionPass *createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *); 62 ModulePass *createAMDGPUPropagateAttributesLatePass(const TargetMachine *); 63 FunctionPass *createAMDGPURewriteOutArgumentsPass(); 64 FunctionPass *createSIModeRegisterPass(); 65 66 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&); 67 68 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&); 69 extern char &AMDGPUMachineCFGStructurizerID; 70 71 void initializeAMDGPUAlwaysInlinePass(PassRegistry&); 72 73 Pass *createAMDGPUAnnotateKernelFeaturesPass(); 74 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &); 75 extern char &AMDGPUAnnotateKernelFeaturesID; 76 77 FunctionPass *createAMDGPUAtomicOptimizerPass(); 78 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &); 79 extern char &AMDGPUAtomicOptimizerID; 80 81 ModulePass *createAMDGPULowerIntrinsicsPass(); 82 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &); 83 extern char &AMDGPULowerIntrinsicsID; 84 85 ModulePass *createAMDGPUFixFunctionBitcastsPass(); 86 void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &); 87 extern char &AMDGPUFixFunctionBitcastsID; 88 89 FunctionPass *createAMDGPULowerKernelArgumentsPass(); 90 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &); 91 extern char &AMDGPULowerKernelArgumentsID; 92 93 ModulePass *createAMDGPULowerKernelAttributesPass(); 94 void initializeAMDGPULowerKernelAttributesPass(PassRegistry &); 95 extern char &AMDGPULowerKernelAttributesID; 96 97 void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &); 98 extern char &AMDGPUPropagateAttributesEarlyID; 99 100 void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &); 101 extern char &AMDGPUPropagateAttributesLateID; 102 103 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &); 104 extern char &AMDGPURewriteOutArgumentsID; 105 106 void initializeGCNDPPCombinePass(PassRegistry &); 107 extern char &GCNDPPCombineID; 108 109 void initializeR600ClauseMergePassPass(PassRegistry &); 110 extern char &R600ClauseMergePassID; 111 112 void initializeR600ControlFlowFinalizerPass(PassRegistry &); 113 extern char &R600ControlFlowFinalizerID; 114 115 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &); 116 extern char &R600ExpandSpecialInstrsPassID; 117 118 void initializeR600VectorRegMergerPass(PassRegistry &); 119 extern char &R600VectorRegMergerID; 120 121 void initializeR600PacketizerPass(PassRegistry &); 122 extern char &R600PacketizerID; 123 124 void initializeSIFoldOperandsPass(PassRegistry &); 125 extern char &SIFoldOperandsID; 126 127 void initializeSIPeepholeSDWAPass(PassRegistry &); 128 extern char &SIPeepholeSDWAID; 129 130 void initializeSIShrinkInstructionsPass(PassRegistry&); 131 extern char &SIShrinkInstructionsID; 132 133 void initializeSIFixSGPRCopiesPass(PassRegistry &); 134 extern char &SIFixSGPRCopiesID; 135 136 void initializeSIFixVGPRCopiesPass(PassRegistry &); 137 extern char &SIFixVGPRCopiesID; 138 139 void initializeSIFixupVectorISelPass(PassRegistry &); 140 extern char &SIFixupVectorISelID; 141 142 void initializeSILowerI1CopiesPass(PassRegistry &); 143 extern char &SILowerI1CopiesID; 144 145 void initializeSILowerSGPRSpillsPass(PassRegistry &); 146 extern char &SILowerSGPRSpillsID; 147 148 void initializeSILoadStoreOptimizerPass(PassRegistry &); 149 extern char &SILoadStoreOptimizerID; 150 151 void initializeSIWholeQuadModePass(PassRegistry &); 152 extern char &SIWholeQuadModeID; 153 154 void initializeSILowerControlFlowPass(PassRegistry &); 155 extern char &SILowerControlFlowID; 156 157 void initializeSIInsertSkipsPass(PassRegistry &); 158 extern char &SIInsertSkipsPassID; 159 160 void initializeSIOptimizeExecMaskingPass(PassRegistry &); 161 extern char &SIOptimizeExecMaskingID; 162 163 void initializeSIPreAllocateWWMRegsPass(PassRegistry &); 164 extern char &SIPreAllocateWWMRegsID; 165 166 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &); 167 extern char &AMDGPUSimplifyLibCallsID; 168 169 void initializeAMDGPUUseNativeCallsPass(PassRegistry &); 170 extern char &AMDGPUUseNativeCallsID; 171 172 void initializeSIAddIMGInitPass(PassRegistry &); 173 extern char &SIAddIMGInitID; 174 175 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &); 176 extern char &AMDGPUPerfHintAnalysisID; 177 178 // Passes common to R600 and SI 179 FunctionPass *createAMDGPUPromoteAlloca(); 180 void initializeAMDGPUPromoteAllocaPass(PassRegistry&); 181 extern char &AMDGPUPromoteAllocaID; 182 183 Pass *createAMDGPUStructurizeCFGPass(); 184 FunctionPass *createAMDGPUISelDag( 185 TargetMachine *TM = nullptr, 186 CodeGenOpt::Level OptLevel = CodeGenOpt::Default); 187 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true); 188 ModulePass *createR600OpenCLImageTypeLoweringPass(); 189 FunctionPass *createAMDGPUAnnotateUniformValues(); 190 191 ModulePass* createAMDGPUUnifyMetadataPass(); 192 void initializeAMDGPUUnifyMetadataPass(PassRegistry&); 193 extern char &AMDGPUUnifyMetadataID; 194 195 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&); 196 extern char &SIOptimizeExecMaskingPreRAID; 197 198 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); 199 extern char &AMDGPUAnnotateUniformValuesPassID; 200 201 void initializeAMDGPUCodeGenPreparePass(PassRegistry&); 202 extern char &AMDGPUCodeGenPrepareID; 203 204 void initializeSIAnnotateControlFlowPass(PassRegistry&); 205 extern char &SIAnnotateControlFlowPassID; 206 207 void initializeSIMemoryLegalizerPass(PassRegistry&); 208 extern char &SIMemoryLegalizerID; 209 210 void initializeSIModeRegisterPass(PassRegistry&); 211 extern char &SIModeRegisterID; 212 213 void initializeSIInsertWaitcntsPass(PassRegistry&); 214 extern char &SIInsertWaitcntsID; 215 216 void initializeSIFormMemoryClausesPass(PassRegistry&); 217 extern char &SIFormMemoryClausesID; 218 219 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&); 220 extern char &AMDGPUUnifyDivergentExitNodesID; 221 222 ImmutablePass *createAMDGPUAAWrapperPass(); 223 void initializeAMDGPUAAWrapperPassPass(PassRegistry&); 224 ImmutablePass *createAMDGPUExternalAAWrapperPass(); 225 void initializeAMDGPUExternalAAWrapperPass(PassRegistry&); 226 227 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &); 228 229 Pass *createAMDGPUFunctionInliningPass(); 230 void initializeAMDGPUInlinerPass(PassRegistry&); 231 232 ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass(); 233 void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &); 234 extern char &AMDGPUOpenCLEnqueuedBlockLoweringID; 235 236 void initializeGCNRegBankReassignPass(PassRegistry &); 237 extern char &GCNRegBankReassignID; 238 239 void initializeGCNNSAReassignPass(PassRegistry &); 240 extern char &GCNNSAReassignID; 241 242 namespace AMDGPU { 243 enum TargetIndex { 244 TI_CONSTDATA_START, 245 TI_SCRATCH_RSRC_DWORD0, 246 TI_SCRATCH_RSRC_DWORD1, 247 TI_SCRATCH_RSRC_DWORD2, 248 TI_SCRATCH_RSRC_DWORD3 249 }; 250 } 251 252 } // End namespace llvm 253 254 /// OpenCL uses address spaces to differentiate between 255 /// various memory regions on the hardware. On the CPU 256 /// all of the address spaces point to the same memory, 257 /// however on the GPU, each address space points to 258 /// a separate piece of memory that is unique from other 259 /// memory locations. 260 namespace AMDGPUAS { 261 enum : unsigned { 262 // The maximum value for flat, generic, local, private, constant and region. 263 MAX_AMDGPU_ADDRESS = 7, 264 265 FLAT_ADDRESS = 0, ///< Address space for flat memory. 266 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). 267 REGION_ADDRESS = 2, ///< Address space for region memory. (GDS) 268 269 CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2). 270 LOCAL_ADDRESS = 3, ///< Address space for local memory. 271 PRIVATE_ADDRESS = 5, ///< Address space for private memory. 272 273 CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory. 274 275 BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers. 276 277 /// Address space for direct addressible parameter memory (CONST0). 278 PARAM_D_ADDRESS = 6, 279 /// Address space for indirect addressible parameter memory (VTX1). 280 PARAM_I_ADDRESS = 7, 281 282 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on 283 // this order to be able to dynamically index a constant buffer, for 284 // example: 285 // 286 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 287 288 CONSTANT_BUFFER_0 = 8, 289 CONSTANT_BUFFER_1 = 9, 290 CONSTANT_BUFFER_2 = 10, 291 CONSTANT_BUFFER_3 = 11, 292 CONSTANT_BUFFER_4 = 12, 293 CONSTANT_BUFFER_5 = 13, 294 CONSTANT_BUFFER_6 = 14, 295 CONSTANT_BUFFER_7 = 15, 296 CONSTANT_BUFFER_8 = 16, 297 CONSTANT_BUFFER_9 = 17, 298 CONSTANT_BUFFER_10 = 18, 299 CONSTANT_BUFFER_11 = 19, 300 CONSTANT_BUFFER_12 = 20, 301 CONSTANT_BUFFER_13 = 21, 302 CONSTANT_BUFFER_14 = 22, 303 CONSTANT_BUFFER_15 = 23, 304 305 // Some places use this if the address space can't be determined. 306 UNKNOWN_ADDRESS_SPACE = ~0u, 307 }; 308 } 309 310 #endif 311