1*0b57cec5SDimitry Andric //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric /// \file 8*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 9*0b57cec5SDimitry Andric 10*0b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 11*0b57cec5SDimitry Andric #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 12*0b57cec5SDimitry Andric 13*0b57cec5SDimitry Andric #include "llvm/Target/TargetMachine.h" 14*0b57cec5SDimitry Andric 15*0b57cec5SDimitry Andric namespace llvm { 16*0b57cec5SDimitry Andric 17*0b57cec5SDimitry Andric class AMDGPUTargetMachine; 18*0b57cec5SDimitry Andric class FunctionPass; 19*0b57cec5SDimitry Andric class GCNTargetMachine; 20*0b57cec5SDimitry Andric class ModulePass; 21*0b57cec5SDimitry Andric class Pass; 22*0b57cec5SDimitry Andric class Target; 23*0b57cec5SDimitry Andric class TargetMachine; 24*0b57cec5SDimitry Andric class TargetOptions; 25*0b57cec5SDimitry Andric class PassRegistry; 26*0b57cec5SDimitry Andric class Module; 27*0b57cec5SDimitry Andric 28*0b57cec5SDimitry Andric // R600 Passes 29*0b57cec5SDimitry Andric FunctionPass *createR600VectorRegMerger(); 30*0b57cec5SDimitry Andric FunctionPass *createR600ExpandSpecialInstrsPass(); 31*0b57cec5SDimitry Andric FunctionPass *createR600EmitClauseMarkers(); 32*0b57cec5SDimitry Andric FunctionPass *createR600ClauseMergePass(); 33*0b57cec5SDimitry Andric FunctionPass *createR600Packetizer(); 34*0b57cec5SDimitry Andric FunctionPass *createR600ControlFlowFinalizer(); 35*0b57cec5SDimitry Andric FunctionPass *createAMDGPUCFGStructurizerPass(); 36*0b57cec5SDimitry Andric FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel); 37*0b57cec5SDimitry Andric 38*0b57cec5SDimitry Andric // SI Passes 39*0b57cec5SDimitry Andric FunctionPass *createGCNDPPCombinePass(); 40*0b57cec5SDimitry Andric FunctionPass *createSIAnnotateControlFlowPass(); 41*0b57cec5SDimitry Andric FunctionPass *createSIFoldOperandsPass(); 42*0b57cec5SDimitry Andric FunctionPass *createSIPeepholeSDWAPass(); 43*0b57cec5SDimitry Andric FunctionPass *createSILowerI1CopiesPass(); 44*0b57cec5SDimitry Andric FunctionPass *createSIFixupVectorISelPass(); 45*0b57cec5SDimitry Andric FunctionPass *createSIAddIMGInitPass(); 46*0b57cec5SDimitry Andric FunctionPass *createSIShrinkInstructionsPass(); 47*0b57cec5SDimitry Andric FunctionPass *createSILoadStoreOptimizerPass(); 48*0b57cec5SDimitry Andric FunctionPass *createSIWholeQuadModePass(); 49*0b57cec5SDimitry Andric FunctionPass *createSIFixControlFlowLiveIntervalsPass(); 50*0b57cec5SDimitry Andric FunctionPass *createSIOptimizeExecMaskingPreRAPass(); 51*0b57cec5SDimitry Andric FunctionPass *createSIFixSGPRCopiesPass(); 52*0b57cec5SDimitry Andric FunctionPass *createSIMemoryLegalizerPass(); 53*0b57cec5SDimitry Andric FunctionPass *createSIInsertWaitcntsPass(); 54*0b57cec5SDimitry Andric FunctionPass *createSIPreAllocateWWMRegsPass(); 55*0b57cec5SDimitry Andric FunctionPass *createSIFormMemoryClausesPass(); 56*0b57cec5SDimitry Andric FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetOptions &, 57*0b57cec5SDimitry Andric const TargetMachine *); 58*0b57cec5SDimitry Andric FunctionPass *createAMDGPUUseNativeCallsPass(); 59*0b57cec5SDimitry Andric FunctionPass *createAMDGPUCodeGenPreparePass(); 60*0b57cec5SDimitry Andric FunctionPass *createAMDGPUMachineCFGStructurizerPass(); 61*0b57cec5SDimitry Andric FunctionPass *createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *); 62*0b57cec5SDimitry Andric ModulePass *createAMDGPUPropagateAttributesLatePass(const TargetMachine *); 63*0b57cec5SDimitry Andric FunctionPass *createAMDGPURewriteOutArgumentsPass(); 64*0b57cec5SDimitry Andric FunctionPass *createSIModeRegisterPass(); 65*0b57cec5SDimitry Andric 66*0b57cec5SDimitry Andric void initializeAMDGPUDAGToDAGISelPass(PassRegistry&); 67*0b57cec5SDimitry Andric 68*0b57cec5SDimitry Andric void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&); 69*0b57cec5SDimitry Andric extern char &AMDGPUMachineCFGStructurizerID; 70*0b57cec5SDimitry Andric 71*0b57cec5SDimitry Andric void initializeAMDGPUAlwaysInlinePass(PassRegistry&); 72*0b57cec5SDimitry Andric 73*0b57cec5SDimitry Andric Pass *createAMDGPUAnnotateKernelFeaturesPass(); 74*0b57cec5SDimitry Andric void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &); 75*0b57cec5SDimitry Andric extern char &AMDGPUAnnotateKernelFeaturesID; 76*0b57cec5SDimitry Andric 77*0b57cec5SDimitry Andric FunctionPass *createAMDGPUAtomicOptimizerPass(); 78*0b57cec5SDimitry Andric void initializeAMDGPUAtomicOptimizerPass(PassRegistry &); 79*0b57cec5SDimitry Andric extern char &AMDGPUAtomicOptimizerID; 80*0b57cec5SDimitry Andric 81*0b57cec5SDimitry Andric ModulePass *createAMDGPULowerIntrinsicsPass(); 82*0b57cec5SDimitry Andric void initializeAMDGPULowerIntrinsicsPass(PassRegistry &); 83*0b57cec5SDimitry Andric extern char &AMDGPULowerIntrinsicsID; 84*0b57cec5SDimitry Andric 85*0b57cec5SDimitry Andric ModulePass *createAMDGPUFixFunctionBitcastsPass(); 86*0b57cec5SDimitry Andric void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &); 87*0b57cec5SDimitry Andric extern char &AMDGPUFixFunctionBitcastsID; 88*0b57cec5SDimitry Andric 89*0b57cec5SDimitry Andric FunctionPass *createAMDGPULowerKernelArgumentsPass(); 90*0b57cec5SDimitry Andric void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &); 91*0b57cec5SDimitry Andric extern char &AMDGPULowerKernelArgumentsID; 92*0b57cec5SDimitry Andric 93*0b57cec5SDimitry Andric ModulePass *createAMDGPULowerKernelAttributesPass(); 94*0b57cec5SDimitry Andric void initializeAMDGPULowerKernelAttributesPass(PassRegistry &); 95*0b57cec5SDimitry Andric extern char &AMDGPULowerKernelAttributesID; 96*0b57cec5SDimitry Andric 97*0b57cec5SDimitry Andric void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &); 98*0b57cec5SDimitry Andric extern char &AMDGPUPropagateAttributesEarlyID; 99*0b57cec5SDimitry Andric 100*0b57cec5SDimitry Andric void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &); 101*0b57cec5SDimitry Andric extern char &AMDGPUPropagateAttributesLateID; 102*0b57cec5SDimitry Andric 103*0b57cec5SDimitry Andric void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &); 104*0b57cec5SDimitry Andric extern char &AMDGPURewriteOutArgumentsID; 105*0b57cec5SDimitry Andric 106*0b57cec5SDimitry Andric void initializeGCNDPPCombinePass(PassRegistry &); 107*0b57cec5SDimitry Andric extern char &GCNDPPCombineID; 108*0b57cec5SDimitry Andric 109*0b57cec5SDimitry Andric void initializeR600ClauseMergePassPass(PassRegistry &); 110*0b57cec5SDimitry Andric extern char &R600ClauseMergePassID; 111*0b57cec5SDimitry Andric 112*0b57cec5SDimitry Andric void initializeR600ControlFlowFinalizerPass(PassRegistry &); 113*0b57cec5SDimitry Andric extern char &R600ControlFlowFinalizerID; 114*0b57cec5SDimitry Andric 115*0b57cec5SDimitry Andric void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &); 116*0b57cec5SDimitry Andric extern char &R600ExpandSpecialInstrsPassID; 117*0b57cec5SDimitry Andric 118*0b57cec5SDimitry Andric void initializeR600VectorRegMergerPass(PassRegistry &); 119*0b57cec5SDimitry Andric extern char &R600VectorRegMergerID; 120*0b57cec5SDimitry Andric 121*0b57cec5SDimitry Andric void initializeR600PacketizerPass(PassRegistry &); 122*0b57cec5SDimitry Andric extern char &R600PacketizerID; 123*0b57cec5SDimitry Andric 124*0b57cec5SDimitry Andric void initializeSIFoldOperandsPass(PassRegistry &); 125*0b57cec5SDimitry Andric extern char &SIFoldOperandsID; 126*0b57cec5SDimitry Andric 127*0b57cec5SDimitry Andric void initializeSIPeepholeSDWAPass(PassRegistry &); 128*0b57cec5SDimitry Andric extern char &SIPeepholeSDWAID; 129*0b57cec5SDimitry Andric 130*0b57cec5SDimitry Andric void initializeSIShrinkInstructionsPass(PassRegistry&); 131*0b57cec5SDimitry Andric extern char &SIShrinkInstructionsID; 132*0b57cec5SDimitry Andric 133*0b57cec5SDimitry Andric void initializeSIFixSGPRCopiesPass(PassRegistry &); 134*0b57cec5SDimitry Andric extern char &SIFixSGPRCopiesID; 135*0b57cec5SDimitry Andric 136*0b57cec5SDimitry Andric void initializeSIFixVGPRCopiesPass(PassRegistry &); 137*0b57cec5SDimitry Andric extern char &SIFixVGPRCopiesID; 138*0b57cec5SDimitry Andric 139*0b57cec5SDimitry Andric void initializeSIFixupVectorISelPass(PassRegistry &); 140*0b57cec5SDimitry Andric extern char &SIFixupVectorISelID; 141*0b57cec5SDimitry Andric 142*0b57cec5SDimitry Andric void initializeSILowerI1CopiesPass(PassRegistry &); 143*0b57cec5SDimitry Andric extern char &SILowerI1CopiesID; 144*0b57cec5SDimitry Andric 145*0b57cec5SDimitry Andric void initializeSILowerSGPRSpillsPass(PassRegistry &); 146*0b57cec5SDimitry Andric extern char &SILowerSGPRSpillsID; 147*0b57cec5SDimitry Andric 148*0b57cec5SDimitry Andric void initializeSILoadStoreOptimizerPass(PassRegistry &); 149*0b57cec5SDimitry Andric extern char &SILoadStoreOptimizerID; 150*0b57cec5SDimitry Andric 151*0b57cec5SDimitry Andric void initializeSIWholeQuadModePass(PassRegistry &); 152*0b57cec5SDimitry Andric extern char &SIWholeQuadModeID; 153*0b57cec5SDimitry Andric 154*0b57cec5SDimitry Andric void initializeSILowerControlFlowPass(PassRegistry &); 155*0b57cec5SDimitry Andric extern char &SILowerControlFlowID; 156*0b57cec5SDimitry Andric 157*0b57cec5SDimitry Andric void initializeSIInsertSkipsPass(PassRegistry &); 158*0b57cec5SDimitry Andric extern char &SIInsertSkipsPassID; 159*0b57cec5SDimitry Andric 160*0b57cec5SDimitry Andric void initializeSIOptimizeExecMaskingPass(PassRegistry &); 161*0b57cec5SDimitry Andric extern char &SIOptimizeExecMaskingID; 162*0b57cec5SDimitry Andric 163*0b57cec5SDimitry Andric void initializeSIPreAllocateWWMRegsPass(PassRegistry &); 164*0b57cec5SDimitry Andric extern char &SIPreAllocateWWMRegsID; 165*0b57cec5SDimitry Andric 166*0b57cec5SDimitry Andric void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &); 167*0b57cec5SDimitry Andric extern char &AMDGPUSimplifyLibCallsID; 168*0b57cec5SDimitry Andric 169*0b57cec5SDimitry Andric void initializeAMDGPUUseNativeCallsPass(PassRegistry &); 170*0b57cec5SDimitry Andric extern char &AMDGPUUseNativeCallsID; 171*0b57cec5SDimitry Andric 172*0b57cec5SDimitry Andric void initializeSIAddIMGInitPass(PassRegistry &); 173*0b57cec5SDimitry Andric extern char &SIAddIMGInitID; 174*0b57cec5SDimitry Andric 175*0b57cec5SDimitry Andric void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &); 176*0b57cec5SDimitry Andric extern char &AMDGPUPerfHintAnalysisID; 177*0b57cec5SDimitry Andric 178*0b57cec5SDimitry Andric // Passes common to R600 and SI 179*0b57cec5SDimitry Andric FunctionPass *createAMDGPUPromoteAlloca(); 180*0b57cec5SDimitry Andric void initializeAMDGPUPromoteAllocaPass(PassRegistry&); 181*0b57cec5SDimitry Andric extern char &AMDGPUPromoteAllocaID; 182*0b57cec5SDimitry Andric 183*0b57cec5SDimitry Andric Pass *createAMDGPUStructurizeCFGPass(); 184*0b57cec5SDimitry Andric FunctionPass *createAMDGPUISelDag( 185*0b57cec5SDimitry Andric TargetMachine *TM = nullptr, 186*0b57cec5SDimitry Andric CodeGenOpt::Level OptLevel = CodeGenOpt::Default); 187*0b57cec5SDimitry Andric ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true); 188*0b57cec5SDimitry Andric ModulePass *createR600OpenCLImageTypeLoweringPass(); 189*0b57cec5SDimitry Andric FunctionPass *createAMDGPUAnnotateUniformValues(); 190*0b57cec5SDimitry Andric 191*0b57cec5SDimitry Andric ModulePass* createAMDGPUUnifyMetadataPass(); 192*0b57cec5SDimitry Andric void initializeAMDGPUUnifyMetadataPass(PassRegistry&); 193*0b57cec5SDimitry Andric extern char &AMDGPUUnifyMetadataID; 194*0b57cec5SDimitry Andric 195*0b57cec5SDimitry Andric void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&); 196*0b57cec5SDimitry Andric extern char &SIOptimizeExecMaskingPreRAID; 197*0b57cec5SDimitry Andric 198*0b57cec5SDimitry Andric void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); 199*0b57cec5SDimitry Andric extern char &AMDGPUAnnotateUniformValuesPassID; 200*0b57cec5SDimitry Andric 201*0b57cec5SDimitry Andric void initializeAMDGPUCodeGenPreparePass(PassRegistry&); 202*0b57cec5SDimitry Andric extern char &AMDGPUCodeGenPrepareID; 203*0b57cec5SDimitry Andric 204*0b57cec5SDimitry Andric void initializeSIAnnotateControlFlowPass(PassRegistry&); 205*0b57cec5SDimitry Andric extern char &SIAnnotateControlFlowPassID; 206*0b57cec5SDimitry Andric 207*0b57cec5SDimitry Andric void initializeSIMemoryLegalizerPass(PassRegistry&); 208*0b57cec5SDimitry Andric extern char &SIMemoryLegalizerID; 209*0b57cec5SDimitry Andric 210*0b57cec5SDimitry Andric void initializeSIModeRegisterPass(PassRegistry&); 211*0b57cec5SDimitry Andric extern char &SIModeRegisterID; 212*0b57cec5SDimitry Andric 213*0b57cec5SDimitry Andric void initializeSIInsertWaitcntsPass(PassRegistry&); 214*0b57cec5SDimitry Andric extern char &SIInsertWaitcntsID; 215*0b57cec5SDimitry Andric 216*0b57cec5SDimitry Andric void initializeSIFormMemoryClausesPass(PassRegistry&); 217*0b57cec5SDimitry Andric extern char &SIFormMemoryClausesID; 218*0b57cec5SDimitry Andric 219*0b57cec5SDimitry Andric void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&); 220*0b57cec5SDimitry Andric extern char &AMDGPUUnifyDivergentExitNodesID; 221*0b57cec5SDimitry Andric 222*0b57cec5SDimitry Andric ImmutablePass *createAMDGPUAAWrapperPass(); 223*0b57cec5SDimitry Andric void initializeAMDGPUAAWrapperPassPass(PassRegistry&); 224*0b57cec5SDimitry Andric ImmutablePass *createAMDGPUExternalAAWrapperPass(); 225*0b57cec5SDimitry Andric void initializeAMDGPUExternalAAWrapperPass(PassRegistry&); 226*0b57cec5SDimitry Andric 227*0b57cec5SDimitry Andric void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &); 228*0b57cec5SDimitry Andric 229*0b57cec5SDimitry Andric Pass *createAMDGPUFunctionInliningPass(); 230*0b57cec5SDimitry Andric void initializeAMDGPUInlinerPass(PassRegistry&); 231*0b57cec5SDimitry Andric 232*0b57cec5SDimitry Andric ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass(); 233*0b57cec5SDimitry Andric void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &); 234*0b57cec5SDimitry Andric extern char &AMDGPUOpenCLEnqueuedBlockLoweringID; 235*0b57cec5SDimitry Andric 236*0b57cec5SDimitry Andric void initializeGCNRegBankReassignPass(PassRegistry &); 237*0b57cec5SDimitry Andric extern char &GCNRegBankReassignID; 238*0b57cec5SDimitry Andric 239*0b57cec5SDimitry Andric void initializeGCNNSAReassignPass(PassRegistry &); 240*0b57cec5SDimitry Andric extern char &GCNNSAReassignID; 241*0b57cec5SDimitry Andric 242*0b57cec5SDimitry Andric namespace AMDGPU { 243*0b57cec5SDimitry Andric enum TargetIndex { 244*0b57cec5SDimitry Andric TI_CONSTDATA_START, 245*0b57cec5SDimitry Andric TI_SCRATCH_RSRC_DWORD0, 246*0b57cec5SDimitry Andric TI_SCRATCH_RSRC_DWORD1, 247*0b57cec5SDimitry Andric TI_SCRATCH_RSRC_DWORD2, 248*0b57cec5SDimitry Andric TI_SCRATCH_RSRC_DWORD3 249*0b57cec5SDimitry Andric }; 250*0b57cec5SDimitry Andric } 251*0b57cec5SDimitry Andric 252*0b57cec5SDimitry Andric } // End namespace llvm 253*0b57cec5SDimitry Andric 254*0b57cec5SDimitry Andric /// OpenCL uses address spaces to differentiate between 255*0b57cec5SDimitry Andric /// various memory regions on the hardware. On the CPU 256*0b57cec5SDimitry Andric /// all of the address spaces point to the same memory, 257*0b57cec5SDimitry Andric /// however on the GPU, each address space points to 258*0b57cec5SDimitry Andric /// a separate piece of memory that is unique from other 259*0b57cec5SDimitry Andric /// memory locations. 260*0b57cec5SDimitry Andric namespace AMDGPUAS { 261*0b57cec5SDimitry Andric enum : unsigned { 262*0b57cec5SDimitry Andric // The maximum value for flat, generic, local, private, constant and region. 263*0b57cec5SDimitry Andric MAX_AMDGPU_ADDRESS = 7, 264*0b57cec5SDimitry Andric 265*0b57cec5SDimitry Andric FLAT_ADDRESS = 0, ///< Address space for flat memory. 266*0b57cec5SDimitry Andric GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). 267*0b57cec5SDimitry Andric REGION_ADDRESS = 2, ///< Address space for region memory. (GDS) 268*0b57cec5SDimitry Andric 269*0b57cec5SDimitry Andric CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2). 270*0b57cec5SDimitry Andric LOCAL_ADDRESS = 3, ///< Address space for local memory. 271*0b57cec5SDimitry Andric PRIVATE_ADDRESS = 5, ///< Address space for private memory. 272*0b57cec5SDimitry Andric 273*0b57cec5SDimitry Andric CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory. 274*0b57cec5SDimitry Andric 275*0b57cec5SDimitry Andric BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers. 276*0b57cec5SDimitry Andric 277*0b57cec5SDimitry Andric /// Address space for direct addressible parameter memory (CONST0). 278*0b57cec5SDimitry Andric PARAM_D_ADDRESS = 6, 279*0b57cec5SDimitry Andric /// Address space for indirect addressible parameter memory (VTX1). 280*0b57cec5SDimitry Andric PARAM_I_ADDRESS = 7, 281*0b57cec5SDimitry Andric 282*0b57cec5SDimitry Andric // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on 283*0b57cec5SDimitry Andric // this order to be able to dynamically index a constant buffer, for 284*0b57cec5SDimitry Andric // example: 285*0b57cec5SDimitry Andric // 286*0b57cec5SDimitry Andric // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 287*0b57cec5SDimitry Andric 288*0b57cec5SDimitry Andric CONSTANT_BUFFER_0 = 8, 289*0b57cec5SDimitry Andric CONSTANT_BUFFER_1 = 9, 290*0b57cec5SDimitry Andric CONSTANT_BUFFER_2 = 10, 291*0b57cec5SDimitry Andric CONSTANT_BUFFER_3 = 11, 292*0b57cec5SDimitry Andric CONSTANT_BUFFER_4 = 12, 293*0b57cec5SDimitry Andric CONSTANT_BUFFER_5 = 13, 294*0b57cec5SDimitry Andric CONSTANT_BUFFER_6 = 14, 295*0b57cec5SDimitry Andric CONSTANT_BUFFER_7 = 15, 296*0b57cec5SDimitry Andric CONSTANT_BUFFER_8 = 16, 297*0b57cec5SDimitry Andric CONSTANT_BUFFER_9 = 17, 298*0b57cec5SDimitry Andric CONSTANT_BUFFER_10 = 18, 299*0b57cec5SDimitry Andric CONSTANT_BUFFER_11 = 19, 300*0b57cec5SDimitry Andric CONSTANT_BUFFER_12 = 20, 301*0b57cec5SDimitry Andric CONSTANT_BUFFER_13 = 21, 302*0b57cec5SDimitry Andric CONSTANT_BUFFER_14 = 22, 303*0b57cec5SDimitry Andric CONSTANT_BUFFER_15 = 23, 304*0b57cec5SDimitry Andric 305*0b57cec5SDimitry Andric // Some places use this if the address space can't be determined. 306*0b57cec5SDimitry Andric UNKNOWN_ADDRESS_SPACE = ~0u, 307*0b57cec5SDimitry Andric }; 308*0b57cec5SDimitry Andric } 309*0b57cec5SDimitry Andric 310*0b57cec5SDimitry Andric #endif 311