1 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains small standalone helper functions and enum definitions for 10 // the AArch64 target useful for the compiler back-end and the MC libraries. 11 // As such, it deliberately does not include references to LLVM core 12 // code gen types, passes, etc.. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H 17 #define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H 18 19 // FIXME: Is it easiest to fix this layering violation by moving the .inc 20 // #includes from AArch64MCTargetDesc.h to here? 21 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends. 22 #include "llvm/ADT/STLExtras.h" 23 #include "llvm/ADT/StringSwitch.h" 24 #include "llvm/MC/SubtargetFeature.h" 25 #include "llvm/Support/ErrorHandling.h" 26 27 namespace llvm { 28 29 inline static unsigned getWRegFromXReg(unsigned Reg) { 30 switch (Reg) { 31 case AArch64::X0: return AArch64::W0; 32 case AArch64::X1: return AArch64::W1; 33 case AArch64::X2: return AArch64::W2; 34 case AArch64::X3: return AArch64::W3; 35 case AArch64::X4: return AArch64::W4; 36 case AArch64::X5: return AArch64::W5; 37 case AArch64::X6: return AArch64::W6; 38 case AArch64::X7: return AArch64::W7; 39 case AArch64::X8: return AArch64::W8; 40 case AArch64::X9: return AArch64::W9; 41 case AArch64::X10: return AArch64::W10; 42 case AArch64::X11: return AArch64::W11; 43 case AArch64::X12: return AArch64::W12; 44 case AArch64::X13: return AArch64::W13; 45 case AArch64::X14: return AArch64::W14; 46 case AArch64::X15: return AArch64::W15; 47 case AArch64::X16: return AArch64::W16; 48 case AArch64::X17: return AArch64::W17; 49 case AArch64::X18: return AArch64::W18; 50 case AArch64::X19: return AArch64::W19; 51 case AArch64::X20: return AArch64::W20; 52 case AArch64::X21: return AArch64::W21; 53 case AArch64::X22: return AArch64::W22; 54 case AArch64::X23: return AArch64::W23; 55 case AArch64::X24: return AArch64::W24; 56 case AArch64::X25: return AArch64::W25; 57 case AArch64::X26: return AArch64::W26; 58 case AArch64::X27: return AArch64::W27; 59 case AArch64::X28: return AArch64::W28; 60 case AArch64::FP: return AArch64::W29; 61 case AArch64::LR: return AArch64::W30; 62 case AArch64::SP: return AArch64::WSP; 63 case AArch64::XZR: return AArch64::WZR; 64 } 65 // For anything else, return it unchanged. 66 return Reg; 67 } 68 69 inline static unsigned getXRegFromWReg(unsigned Reg) { 70 switch (Reg) { 71 case AArch64::W0: return AArch64::X0; 72 case AArch64::W1: return AArch64::X1; 73 case AArch64::W2: return AArch64::X2; 74 case AArch64::W3: return AArch64::X3; 75 case AArch64::W4: return AArch64::X4; 76 case AArch64::W5: return AArch64::X5; 77 case AArch64::W6: return AArch64::X6; 78 case AArch64::W7: return AArch64::X7; 79 case AArch64::W8: return AArch64::X8; 80 case AArch64::W9: return AArch64::X9; 81 case AArch64::W10: return AArch64::X10; 82 case AArch64::W11: return AArch64::X11; 83 case AArch64::W12: return AArch64::X12; 84 case AArch64::W13: return AArch64::X13; 85 case AArch64::W14: return AArch64::X14; 86 case AArch64::W15: return AArch64::X15; 87 case AArch64::W16: return AArch64::X16; 88 case AArch64::W17: return AArch64::X17; 89 case AArch64::W18: return AArch64::X18; 90 case AArch64::W19: return AArch64::X19; 91 case AArch64::W20: return AArch64::X20; 92 case AArch64::W21: return AArch64::X21; 93 case AArch64::W22: return AArch64::X22; 94 case AArch64::W23: return AArch64::X23; 95 case AArch64::W24: return AArch64::X24; 96 case AArch64::W25: return AArch64::X25; 97 case AArch64::W26: return AArch64::X26; 98 case AArch64::W27: return AArch64::X27; 99 case AArch64::W28: return AArch64::X28; 100 case AArch64::W29: return AArch64::FP; 101 case AArch64::W30: return AArch64::LR; 102 case AArch64::WSP: return AArch64::SP; 103 case AArch64::WZR: return AArch64::XZR; 104 } 105 // For anything else, return it unchanged. 106 return Reg; 107 } 108 109 static inline unsigned getBRegFromDReg(unsigned Reg) { 110 switch (Reg) { 111 case AArch64::D0: return AArch64::B0; 112 case AArch64::D1: return AArch64::B1; 113 case AArch64::D2: return AArch64::B2; 114 case AArch64::D3: return AArch64::B3; 115 case AArch64::D4: return AArch64::B4; 116 case AArch64::D5: return AArch64::B5; 117 case AArch64::D6: return AArch64::B6; 118 case AArch64::D7: return AArch64::B7; 119 case AArch64::D8: return AArch64::B8; 120 case AArch64::D9: return AArch64::B9; 121 case AArch64::D10: return AArch64::B10; 122 case AArch64::D11: return AArch64::B11; 123 case AArch64::D12: return AArch64::B12; 124 case AArch64::D13: return AArch64::B13; 125 case AArch64::D14: return AArch64::B14; 126 case AArch64::D15: return AArch64::B15; 127 case AArch64::D16: return AArch64::B16; 128 case AArch64::D17: return AArch64::B17; 129 case AArch64::D18: return AArch64::B18; 130 case AArch64::D19: return AArch64::B19; 131 case AArch64::D20: return AArch64::B20; 132 case AArch64::D21: return AArch64::B21; 133 case AArch64::D22: return AArch64::B22; 134 case AArch64::D23: return AArch64::B23; 135 case AArch64::D24: return AArch64::B24; 136 case AArch64::D25: return AArch64::B25; 137 case AArch64::D26: return AArch64::B26; 138 case AArch64::D27: return AArch64::B27; 139 case AArch64::D28: return AArch64::B28; 140 case AArch64::D29: return AArch64::B29; 141 case AArch64::D30: return AArch64::B30; 142 case AArch64::D31: return AArch64::B31; 143 } 144 // For anything else, return it unchanged. 145 return Reg; 146 } 147 148 149 static inline unsigned getDRegFromBReg(unsigned Reg) { 150 switch (Reg) { 151 case AArch64::B0: return AArch64::D0; 152 case AArch64::B1: return AArch64::D1; 153 case AArch64::B2: return AArch64::D2; 154 case AArch64::B3: return AArch64::D3; 155 case AArch64::B4: return AArch64::D4; 156 case AArch64::B5: return AArch64::D5; 157 case AArch64::B6: return AArch64::D6; 158 case AArch64::B7: return AArch64::D7; 159 case AArch64::B8: return AArch64::D8; 160 case AArch64::B9: return AArch64::D9; 161 case AArch64::B10: return AArch64::D10; 162 case AArch64::B11: return AArch64::D11; 163 case AArch64::B12: return AArch64::D12; 164 case AArch64::B13: return AArch64::D13; 165 case AArch64::B14: return AArch64::D14; 166 case AArch64::B15: return AArch64::D15; 167 case AArch64::B16: return AArch64::D16; 168 case AArch64::B17: return AArch64::D17; 169 case AArch64::B18: return AArch64::D18; 170 case AArch64::B19: return AArch64::D19; 171 case AArch64::B20: return AArch64::D20; 172 case AArch64::B21: return AArch64::D21; 173 case AArch64::B22: return AArch64::D22; 174 case AArch64::B23: return AArch64::D23; 175 case AArch64::B24: return AArch64::D24; 176 case AArch64::B25: return AArch64::D25; 177 case AArch64::B26: return AArch64::D26; 178 case AArch64::B27: return AArch64::D27; 179 case AArch64::B28: return AArch64::D28; 180 case AArch64::B29: return AArch64::D29; 181 case AArch64::B30: return AArch64::D30; 182 case AArch64::B31: return AArch64::D31; 183 } 184 // For anything else, return it unchanged. 185 return Reg; 186 } 187 188 static inline bool atomicBarrierDroppedOnZero(unsigned Opcode) { 189 switch (Opcode) { 190 case AArch64::LDADDAB: case AArch64::LDADDAH: 191 case AArch64::LDADDAW: case AArch64::LDADDAX: 192 case AArch64::LDADDALB: case AArch64::LDADDALH: 193 case AArch64::LDADDALW: case AArch64::LDADDALX: 194 case AArch64::LDCLRAB: case AArch64::LDCLRAH: 195 case AArch64::LDCLRAW: case AArch64::LDCLRAX: 196 case AArch64::LDCLRALB: case AArch64::LDCLRALH: 197 case AArch64::LDCLRALW: case AArch64::LDCLRALX: 198 case AArch64::LDEORAB: case AArch64::LDEORAH: 199 case AArch64::LDEORAW: case AArch64::LDEORAX: 200 case AArch64::LDEORALB: case AArch64::LDEORALH: 201 case AArch64::LDEORALW: case AArch64::LDEORALX: 202 case AArch64::LDSETAB: case AArch64::LDSETAH: 203 case AArch64::LDSETAW: case AArch64::LDSETAX: 204 case AArch64::LDSETALB: case AArch64::LDSETALH: 205 case AArch64::LDSETALW: case AArch64::LDSETALX: 206 case AArch64::LDSMAXAB: case AArch64::LDSMAXAH: 207 case AArch64::LDSMAXAW: case AArch64::LDSMAXAX: 208 case AArch64::LDSMAXALB: case AArch64::LDSMAXALH: 209 case AArch64::LDSMAXALW: case AArch64::LDSMAXALX: 210 case AArch64::LDSMINAB: case AArch64::LDSMINAH: 211 case AArch64::LDSMINAW: case AArch64::LDSMINAX: 212 case AArch64::LDSMINALB: case AArch64::LDSMINALH: 213 case AArch64::LDSMINALW: case AArch64::LDSMINALX: 214 case AArch64::LDUMAXAB: case AArch64::LDUMAXAH: 215 case AArch64::LDUMAXAW: case AArch64::LDUMAXAX: 216 case AArch64::LDUMAXALB: case AArch64::LDUMAXALH: 217 case AArch64::LDUMAXALW: case AArch64::LDUMAXALX: 218 case AArch64::LDUMINAB: case AArch64::LDUMINAH: 219 case AArch64::LDUMINAW: case AArch64::LDUMINAX: 220 case AArch64::LDUMINALB: case AArch64::LDUMINALH: 221 case AArch64::LDUMINALW: case AArch64::LDUMINALX: 222 case AArch64::SWPAB: case AArch64::SWPAH: 223 case AArch64::SWPAW: case AArch64::SWPAX: 224 case AArch64::SWPALB: case AArch64::SWPALH: 225 case AArch64::SWPALW: case AArch64::SWPALX: 226 return true; 227 } 228 return false; 229 } 230 231 namespace AArch64CC { 232 233 // The CondCodes constants map directly to the 4-bit encoding of the condition 234 // field for predicated instructions. 235 enum CondCode { // Meaning (integer) Meaning (floating-point) 236 EQ = 0x0, // Equal Equal 237 NE = 0x1, // Not equal Not equal, or unordered 238 HS = 0x2, // Unsigned higher or same >, ==, or unordered 239 LO = 0x3, // Unsigned lower Less than 240 MI = 0x4, // Minus, negative Less than 241 PL = 0x5, // Plus, positive or zero >, ==, or unordered 242 VS = 0x6, // Overflow Unordered 243 VC = 0x7, // No overflow Not unordered 244 HI = 0x8, // Unsigned higher Greater than, or unordered 245 LS = 0x9, // Unsigned lower or same Less than or equal 246 GE = 0xa, // Greater than or equal Greater than or equal 247 LT = 0xb, // Less than Less than, or unordered 248 GT = 0xc, // Greater than Greater than 249 LE = 0xd, // Less than or equal <, ==, or unordered 250 AL = 0xe, // Always (unconditional) Always (unconditional) 251 NV = 0xf, // Always (unconditional) Always (unconditional) 252 // Note the NV exists purely to disassemble 0b1111. Execution is "always". 253 Invalid 254 }; 255 256 inline static const char *getCondCodeName(CondCode Code) { 257 switch (Code) { 258 default: llvm_unreachable("Unknown condition code"); 259 case EQ: return "eq"; 260 case NE: return "ne"; 261 case HS: return "hs"; 262 case LO: return "lo"; 263 case MI: return "mi"; 264 case PL: return "pl"; 265 case VS: return "vs"; 266 case VC: return "vc"; 267 case HI: return "hi"; 268 case LS: return "ls"; 269 case GE: return "ge"; 270 case LT: return "lt"; 271 case GT: return "gt"; 272 case LE: return "le"; 273 case AL: return "al"; 274 case NV: return "nv"; 275 } 276 } 277 278 inline static CondCode getInvertedCondCode(CondCode Code) { 279 // To reverse a condition it's necessary to only invert the low bit: 280 281 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1); 282 } 283 284 /// Given a condition code, return NZCV flags that would satisfy that condition. 285 /// The flag bits are in the format expected by the ccmp instructions. 286 /// Note that many different flag settings can satisfy a given condition code, 287 /// this function just returns one of them. 288 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) { 289 // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7. 290 enum { N = 8, Z = 4, C = 2, V = 1 }; 291 switch (Code) { 292 default: llvm_unreachable("Unknown condition code"); 293 case EQ: return Z; // Z == 1 294 case NE: return 0; // Z == 0 295 case HS: return C; // C == 1 296 case LO: return 0; // C == 0 297 case MI: return N; // N == 1 298 case PL: return 0; // N == 0 299 case VS: return V; // V == 1 300 case VC: return 0; // V == 0 301 case HI: return C; // C == 1 && Z == 0 302 case LS: return 0; // C == 0 || Z == 1 303 case GE: return 0; // N == V 304 case LT: return N; // N != V 305 case GT: return 0; // Z == 0 && N == V 306 case LE: return Z; // Z == 1 || N != V 307 } 308 } 309 } // end namespace AArch64CC 310 311 struct SysAlias { 312 const char *Name; 313 uint16_t Encoding; 314 FeatureBitset FeaturesRequired; 315 316 constexpr SysAlias(const char *N, uint16_t E) : Name(N), Encoding(E) {} 317 constexpr SysAlias(const char *N, uint16_t E, FeatureBitset F) 318 : Name(N), Encoding(E), FeaturesRequired(F) {} 319 320 bool haveFeatures(FeatureBitset ActiveFeatures) const { 321 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired; 322 } 323 324 FeatureBitset getRequiredFeatures() const { return FeaturesRequired; } 325 }; 326 327 struct SysAliasReg : SysAlias { 328 bool NeedsReg; 329 constexpr SysAliasReg(const char *N, uint16_t E, bool R) 330 : SysAlias(N, E), NeedsReg(R) {} 331 constexpr SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F) 332 : SysAlias(N, E, F), NeedsReg(R) {} 333 }; 334 335 namespace AArch64AT{ 336 struct AT : SysAlias { 337 using SysAlias::SysAlias; 338 }; 339 #define GET_AT_DECL 340 #include "AArch64GenSystemOperands.inc" 341 } 342 343 namespace AArch64DB { 344 struct DB : SysAlias { 345 using SysAlias::SysAlias; 346 }; 347 #define GET_DB_DECL 348 #include "AArch64GenSystemOperands.inc" 349 } 350 351 namespace AArch64DC { 352 struct DC : SysAlias { 353 using SysAlias::SysAlias; 354 }; 355 #define GET_DC_DECL 356 #include "AArch64GenSystemOperands.inc" 357 } 358 359 namespace AArch64IC { 360 struct IC : SysAliasReg { 361 using SysAliasReg::SysAliasReg; 362 }; 363 #define GET_IC_DECL 364 #include "AArch64GenSystemOperands.inc" 365 } 366 367 namespace AArch64ISB { 368 struct ISB : SysAlias { 369 using SysAlias::SysAlias; 370 }; 371 #define GET_ISB_DECL 372 #include "AArch64GenSystemOperands.inc" 373 } 374 375 namespace AArch64TSB { 376 struct TSB : SysAlias { 377 using SysAlias::SysAlias; 378 }; 379 #define GET_TSB_DECL 380 #include "AArch64GenSystemOperands.inc" 381 } 382 383 namespace AArch64PRFM { 384 struct PRFM : SysAlias { 385 using SysAlias::SysAlias; 386 }; 387 #define GET_PRFM_DECL 388 #include "AArch64GenSystemOperands.inc" 389 } 390 391 namespace AArch64SVEPRFM { 392 struct SVEPRFM : SysAlias { 393 using SysAlias::SysAlias; 394 }; 395 #define GET_SVEPRFM_DECL 396 #include "AArch64GenSystemOperands.inc" 397 } 398 399 namespace AArch64SVEPredPattern { 400 struct SVEPREDPAT { 401 const char *Name; 402 uint16_t Encoding; 403 }; 404 #define GET_SVEPREDPAT_DECL 405 #include "AArch64GenSystemOperands.inc" 406 } 407 408 namespace AArch64ExactFPImm { 409 struct ExactFPImm { 410 const char *Name; 411 int Enum; 412 const char *Repr; 413 }; 414 #define GET_EXACTFPIMM_DECL 415 #include "AArch64GenSystemOperands.inc" 416 } 417 418 namespace AArch64PState { 419 struct PState : SysAlias{ 420 using SysAlias::SysAlias; 421 }; 422 #define GET_PSTATE_DECL 423 #include "AArch64GenSystemOperands.inc" 424 } 425 426 namespace AArch64PSBHint { 427 struct PSB : SysAlias { 428 using SysAlias::SysAlias; 429 }; 430 #define GET_PSB_DECL 431 #include "AArch64GenSystemOperands.inc" 432 } 433 434 namespace AArch64BTIHint { 435 struct BTI : SysAlias { 436 using SysAlias::SysAlias; 437 }; 438 #define GET_BTI_DECL 439 #include "AArch64GenSystemOperands.inc" 440 } 441 442 namespace AArch64SE { 443 enum ShiftExtSpecifiers { 444 Invalid = -1, 445 LSL, 446 MSL, 447 LSR, 448 ASR, 449 ROR, 450 451 UXTB, 452 UXTH, 453 UXTW, 454 UXTX, 455 456 SXTB, 457 SXTH, 458 SXTW, 459 SXTX 460 }; 461 } 462 463 namespace AArch64Layout { 464 enum VectorLayout { 465 Invalid = -1, 466 VL_8B, 467 VL_4H, 468 VL_2S, 469 VL_1D, 470 471 VL_16B, 472 VL_8H, 473 VL_4S, 474 VL_2D, 475 476 // Bare layout for the 128-bit vector 477 // (only show ".b", ".h", ".s", ".d" without vector number) 478 VL_B, 479 VL_H, 480 VL_S, 481 VL_D 482 }; 483 } 484 485 inline static const char * 486 AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout) { 487 switch (Layout) { 488 case AArch64Layout::VL_8B: return ".8b"; 489 case AArch64Layout::VL_4H: return ".4h"; 490 case AArch64Layout::VL_2S: return ".2s"; 491 case AArch64Layout::VL_1D: return ".1d"; 492 case AArch64Layout::VL_16B: return ".16b"; 493 case AArch64Layout::VL_8H: return ".8h"; 494 case AArch64Layout::VL_4S: return ".4s"; 495 case AArch64Layout::VL_2D: return ".2d"; 496 case AArch64Layout::VL_B: return ".b"; 497 case AArch64Layout::VL_H: return ".h"; 498 case AArch64Layout::VL_S: return ".s"; 499 case AArch64Layout::VL_D: return ".d"; 500 default: llvm_unreachable("Unknown Vector Layout"); 501 } 502 } 503 504 inline static AArch64Layout::VectorLayout 505 AArch64StringToVectorLayout(StringRef LayoutStr) { 506 return StringSwitch<AArch64Layout::VectorLayout>(LayoutStr) 507 .Case(".8b", AArch64Layout::VL_8B) 508 .Case(".4h", AArch64Layout::VL_4H) 509 .Case(".2s", AArch64Layout::VL_2S) 510 .Case(".1d", AArch64Layout::VL_1D) 511 .Case(".16b", AArch64Layout::VL_16B) 512 .Case(".8h", AArch64Layout::VL_8H) 513 .Case(".4s", AArch64Layout::VL_4S) 514 .Case(".2d", AArch64Layout::VL_2D) 515 .Case(".b", AArch64Layout::VL_B) 516 .Case(".h", AArch64Layout::VL_H) 517 .Case(".s", AArch64Layout::VL_S) 518 .Case(".d", AArch64Layout::VL_D) 519 .Default(AArch64Layout::Invalid); 520 } 521 522 namespace AArch64SysReg { 523 struct SysReg { 524 const char *Name; 525 unsigned Encoding; 526 bool Readable; 527 bool Writeable; 528 FeatureBitset FeaturesRequired; 529 530 bool haveFeatures(FeatureBitset ActiveFeatures) const { 531 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired; 532 } 533 }; 534 535 #define GET_SYSREG_DECL 536 #include "AArch64GenSystemOperands.inc" 537 538 const SysReg *lookupSysRegByName(StringRef); 539 const SysReg *lookupSysRegByEncoding(uint16_t); 540 541 uint32_t parseGenericRegister(StringRef Name); 542 std::string genericRegisterString(uint32_t Bits); 543 } 544 545 namespace AArch64TLBI { 546 struct TLBI : SysAliasReg { 547 using SysAliasReg::SysAliasReg; 548 }; 549 #define GET_TLBI_DECL 550 #include "AArch64GenSystemOperands.inc" 551 } 552 553 namespace AArch64PRCTX { 554 struct PRCTX : SysAliasReg { 555 using SysAliasReg::SysAliasReg; 556 }; 557 #define GET_PRCTX_DECL 558 #include "AArch64GenSystemOperands.inc" 559 } 560 561 namespace AArch64II { 562 /// Target Operand Flag enum. 563 enum TOF { 564 //===------------------------------------------------------------------===// 565 // AArch64 Specific MachineOperand flags. 566 567 MO_NO_FLAG, 568 569 MO_FRAGMENT = 0x7, 570 571 /// MO_PAGE - A symbol operand with this flag represents the pc-relative 572 /// offset of the 4K page containing the symbol. This is used with the 573 /// ADRP instruction. 574 MO_PAGE = 1, 575 576 /// MO_PAGEOFF - A symbol operand with this flag represents the offset of 577 /// that symbol within a 4K page. This offset is added to the page address 578 /// to produce the complete address. 579 MO_PAGEOFF = 2, 580 581 /// MO_G3 - A symbol operand with this flag (granule 3) represents the high 582 /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction 583 MO_G3 = 3, 584 585 /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits 586 /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction 587 MO_G2 = 4, 588 589 /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits 590 /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction 591 MO_G1 = 5, 592 593 /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits 594 /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction 595 MO_G0 = 6, 596 597 /// MO_HI12 - This flag indicates that a symbol operand represents the bits 598 /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left- 599 /// by-12-bits instruction. 600 MO_HI12 = 7, 601 602 /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the 603 /// reference is actually to the ".refptrp.FOO" symbol. This is used for 604 /// stub symbols on windows. 605 MO_COFFSTUB = 0x8, 606 607 /// MO_GOT - This flag indicates that a symbol operand represents the 608 /// address of the GOT entry for the symbol, rather than the address of 609 /// the symbol itself. 610 MO_GOT = 0x10, 611 612 /// MO_NC - Indicates whether the linker is expected to check the symbol 613 /// reference for overflow. For example in an ADRP/ADD pair of relocations 614 /// the ADRP usually does check, but not the ADD. 615 MO_NC = 0x20, 616 617 /// MO_TLS - Indicates that the operand being accessed is some kind of 618 /// thread-local symbol. On Darwin, only one type of thread-local access 619 /// exists (pre linker-relaxation), but on ELF the TLSModel used for the 620 /// referee will affect interpretation. 621 MO_TLS = 0x40, 622 623 /// MO_DLLIMPORT - On a symbol operand, this represents that the reference 624 /// to the symbol is for an import stub. This is used for DLL import 625 /// storage class indication on Windows. 626 MO_DLLIMPORT = 0x80, 627 628 /// MO_S - Indicates that the bits of the symbol operand represented by 629 /// MO_G0 etc are signed. 630 MO_S = 0x100, 631 632 /// MO_PREL - Indicates that the bits of the symbol operand represented by 633 /// MO_G0 etc are PC relative. 634 MO_PREL = 0x200, 635 636 /// MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag 637 /// in bits 56-63. 638 /// On a FrameIndex operand, indicates that the underlying memory is tagged 639 /// with an unknown tag value (MTE); this needs to be lowered either to an 640 /// SP-relative load or store instruction (which do not check tags), or to 641 /// an LDG instruction to obtain the tag value. 642 MO_TAGGED = 0x400, 643 }; 644 } // end namespace AArch64II 645 646 } // end namespace llvm 647 648 #endif 649