1//=-- SVEInstrFormats.td - AArch64 SVE Instruction classes -*- tablegen -*--=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// AArch64 Scalable Vector Extension (SVE) Instruction Class Definitions. 10// 11//===----------------------------------------------------------------------===// 12 13def SVEPatternOperand : AsmOperandClass { 14 let Name = "SVEPattern"; 15 let ParserMethod = "tryParseSVEPattern"; 16 let PredicateMethod = "isSVEPattern"; 17 let RenderMethod = "addImmOperands"; 18 let DiagnosticType = "InvalidSVEPattern"; 19} 20 21def sve_pred_enum : Operand<i32>, ImmLeaf<i32, [{ 22 return (((uint32_t)Imm) < 32); 23 }]> { 24 25 let PrintMethod = "printSVEPattern"; 26 let ParserMatchClass = SVEPatternOperand; 27} 28 29def SVEPrefetchOperand : AsmOperandClass { 30 let Name = "SVEPrefetch"; 31 let ParserMethod = "tryParsePrefetch<true>"; 32 let PredicateMethod = "isPrefetch"; 33 let RenderMethod = "addPrefetchOperands"; 34} 35 36def sve_prfop : Operand<i32>, ImmLeaf<i32, [{ 37 return (((uint32_t)Imm) <= 15); 38 }]> { 39 let PrintMethod = "printPrefetchOp<true>"; 40 let ParserMatchClass = SVEPrefetchOperand; 41} 42 43class SVELogicalImmOperand<int Width> : AsmOperandClass { 44 let Name = "SVELogicalImm" # Width; 45 let DiagnosticType = "LogicalSecondSource"; 46 let PredicateMethod = "isLogicalImm<int" # Width # "_t>"; 47 let RenderMethod = "addLogicalImmOperands<int" # Width # "_t>"; 48} 49 50def sve_logical_imm8 : Operand<i64> { 51 let ParserMatchClass = SVELogicalImmOperand<8>; 52 let PrintMethod = "printLogicalImm<int8_t>"; 53 54 let MCOperandPredicate = [{ 55 if (!MCOp.isImm()) 56 return false; 57 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); 58 return AArch64_AM::isSVEMaskOfIdenticalElements<int8_t>(Val); 59 }]; 60} 61 62def sve_logical_imm16 : Operand<i64> { 63 let ParserMatchClass = SVELogicalImmOperand<16>; 64 let PrintMethod = "printLogicalImm<int16_t>"; 65 66 let MCOperandPredicate = [{ 67 if (!MCOp.isImm()) 68 return false; 69 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); 70 return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val); 71 }]; 72} 73 74def sve_logical_imm32 : Operand<i64> { 75 let ParserMatchClass = SVELogicalImmOperand<32>; 76 let PrintMethod = "printLogicalImm<int32_t>"; 77 78 let MCOperandPredicate = [{ 79 if (!MCOp.isImm()) 80 return false; 81 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); 82 return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val); 83 }]; 84} 85 86class SVEPreferredLogicalImmOperand<int Width> : AsmOperandClass { 87 let Name = "SVEPreferredLogicalImm" # Width; 88 let PredicateMethod = "isSVEPreferredLogicalImm<int" # Width # "_t>"; 89 let RenderMethod = "addLogicalImmOperands<int" # Width # "_t>"; 90} 91 92def sve_preferred_logical_imm16 : Operand<i64> { 93 let ParserMatchClass = SVEPreferredLogicalImmOperand<16>; 94 let PrintMethod = "printSVELogicalImm<int16_t>"; 95 96 let MCOperandPredicate = [{ 97 if (!MCOp.isImm()) 98 return false; 99 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); 100 return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val) && 101 AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val); 102 }]; 103} 104 105def sve_preferred_logical_imm32 : Operand<i64> { 106 let ParserMatchClass = SVEPreferredLogicalImmOperand<32>; 107 let PrintMethod = "printSVELogicalImm<int32_t>"; 108 109 let MCOperandPredicate = [{ 110 if (!MCOp.isImm()) 111 return false; 112 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); 113 return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val) && 114 AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val); 115 }]; 116} 117 118def sve_preferred_logical_imm64 : Operand<i64> { 119 let ParserMatchClass = SVEPreferredLogicalImmOperand<64>; 120 let PrintMethod = "printSVELogicalImm<int64_t>"; 121 122 let MCOperandPredicate = [{ 123 if (!MCOp.isImm()) 124 return false; 125 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); 126 return AArch64_AM::isSVEMaskOfIdenticalElements<int64_t>(Val) && 127 AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val); 128 }]; 129} 130 131class SVELogicalImmNotOperand<int Width> : AsmOperandClass { 132 let Name = "SVELogicalImm" # Width # "Not"; 133 let DiagnosticType = "LogicalSecondSource"; 134 let PredicateMethod = "isLogicalImm<int" # Width # "_t>"; 135 let RenderMethod = "addLogicalImmNotOperands<int" # Width # "_t>"; 136} 137 138def sve_logical_imm8_not : Operand<i64> { 139 let ParserMatchClass = SVELogicalImmNotOperand<8>; 140} 141 142def sve_logical_imm16_not : Operand<i64> { 143 let ParserMatchClass = SVELogicalImmNotOperand<16>; 144} 145 146def sve_logical_imm32_not : Operand<i64> { 147 let ParserMatchClass = SVELogicalImmNotOperand<32>; 148} 149 150class SVEShiftedImmOperand<int ElementWidth, string Infix, string Predicate> 151 : AsmOperandClass { 152 let Name = "SVE" # Infix # "Imm" # ElementWidth; 153 let DiagnosticType = "Invalid" # Name; 154 let RenderMethod = "addImmWithOptionalShiftOperands<8>"; 155 let ParserMethod = "tryParseImmWithOptionalShift"; 156 let PredicateMethod = Predicate; 157} 158 159def SVECpyImmOperand8 : SVEShiftedImmOperand<8, "Cpy", "isSVECpyImm<int8_t>">; 160def SVECpyImmOperand16 : SVEShiftedImmOperand<16, "Cpy", "isSVECpyImm<int16_t>">; 161def SVECpyImmOperand32 : SVEShiftedImmOperand<32, "Cpy", "isSVECpyImm<int32_t>">; 162def SVECpyImmOperand64 : SVEShiftedImmOperand<64, "Cpy", "isSVECpyImm<int64_t>">; 163 164def SVEAddSubImmOperand8 : SVEShiftedImmOperand<8, "AddSub", "isSVEAddSubImm<int8_t>">; 165def SVEAddSubImmOperand16 : SVEShiftedImmOperand<16, "AddSub", "isSVEAddSubImm<int16_t>">; 166def SVEAddSubImmOperand32 : SVEShiftedImmOperand<32, "AddSub", "isSVEAddSubImm<int32_t>">; 167def SVEAddSubImmOperand64 : SVEShiftedImmOperand<64, "AddSub", "isSVEAddSubImm<int64_t>">; 168 169class imm8_opt_lsl<int ElementWidth, string printType, 170 AsmOperandClass OpndClass, code Predicate> 171 : Operand<i32>, ImmLeaf<i32, Predicate> { 172 let EncoderMethod = "getImm8OptLsl"; 173 let DecoderMethod = "DecodeImm8OptLsl<" # ElementWidth # ">"; 174 let PrintMethod = "printImm8OptLsl<" # printType # ">"; 175 let ParserMatchClass = OpndClass; 176 let MIOperandInfo = (ops i32imm, i32imm); 177} 178 179def cpy_imm8_opt_lsl_i8 : imm8_opt_lsl<8, "int8_t", SVECpyImmOperand8, [{ 180 return AArch64_AM::isSVECpyImm<int8_t>(Imm); 181}]>; 182def cpy_imm8_opt_lsl_i16 : imm8_opt_lsl<16, "int16_t", SVECpyImmOperand16, [{ 183 return AArch64_AM::isSVECpyImm<int16_t>(Imm); 184}]>; 185def cpy_imm8_opt_lsl_i32 : imm8_opt_lsl<32, "int32_t", SVECpyImmOperand32, [{ 186 return AArch64_AM::isSVECpyImm<int32_t>(Imm); 187}]>; 188def cpy_imm8_opt_lsl_i64 : imm8_opt_lsl<64, "int64_t", SVECpyImmOperand64, [{ 189 return AArch64_AM::isSVECpyImm<int64_t>(Imm); 190}]>; 191 192def addsub_imm8_opt_lsl_i8 : imm8_opt_lsl<8, "uint8_t", SVEAddSubImmOperand8, [{ 193 return AArch64_AM::isSVEAddSubImm<int8_t>(Imm); 194}]>; 195def addsub_imm8_opt_lsl_i16 : imm8_opt_lsl<16, "uint16_t", SVEAddSubImmOperand16, [{ 196 return AArch64_AM::isSVEAddSubImm<int16_t>(Imm); 197}]>; 198def addsub_imm8_opt_lsl_i32 : imm8_opt_lsl<32, "uint32_t", SVEAddSubImmOperand32, [{ 199 return AArch64_AM::isSVEAddSubImm<int32_t>(Imm); 200}]>; 201def addsub_imm8_opt_lsl_i64 : imm8_opt_lsl<64, "uint64_t", SVEAddSubImmOperand64, [{ 202 return AArch64_AM::isSVEAddSubImm<int64_t>(Imm); 203}]>; 204 205class SVEExactFPImm<string Suffix, string ValA, string ValB> : AsmOperandClass { 206 let Name = "SVEExactFPImmOperand" # Suffix; 207 let DiagnosticType = "Invalid" # Name; 208 let ParserMethod = "tryParseFPImm<false>"; 209 let PredicateMethod = "isExactFPImm<" # ValA # ", " # ValB # ">"; 210 let RenderMethod = "addExactFPImmOperands<" # ValA # ", " # ValB # ">"; 211} 212 213class SVEExactFPImmOperand<string Suffix, string ValA, string ValB> : Operand<i32> { 214 let PrintMethod = "printExactFPImm<" # ValA # ", " # ValB # ">"; 215 let ParserMatchClass = SVEExactFPImm<Suffix, ValA, ValB>; 216} 217 218def sve_fpimm_half_one 219 : SVEExactFPImmOperand<"HalfOne", "AArch64ExactFPImm::half", 220 "AArch64ExactFPImm::one">; 221def sve_fpimm_half_two 222 : SVEExactFPImmOperand<"HalfTwo", "AArch64ExactFPImm::half", 223 "AArch64ExactFPImm::two">; 224def sve_fpimm_zero_one 225 : SVEExactFPImmOperand<"ZeroOne", "AArch64ExactFPImm::zero", 226 "AArch64ExactFPImm::one">; 227 228def sve_incdec_imm : Operand<i32>, ImmLeaf<i32, [{ 229 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17); 230}]> { 231 let ParserMatchClass = Imm1_16Operand; 232 let EncoderMethod = "getSVEIncDecImm"; 233 let DecoderMethod = "DecodeSVEIncDecImm"; 234} 235 236//===----------------------------------------------------------------------===// 237// SVE PTrue - These are used extensively throughout the pattern matching so 238// it's important we define them first. 239//===----------------------------------------------------------------------===// 240 241class sve_int_ptrue<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty> 242: I<(outs pprty:$Pd), (ins sve_pred_enum:$pattern), 243 asm, "\t$Pd, $pattern", 244 "", 245 []>, Sched<[]> { 246 bits<4> Pd; 247 bits<5> pattern; 248 let Inst{31-24} = 0b00100101; 249 let Inst{23-22} = sz8_64; 250 let Inst{21-19} = 0b011; 251 let Inst{18-17} = opc{2-1}; 252 let Inst{16} = opc{0}; 253 let Inst{15-10} = 0b111000; 254 let Inst{9-5} = pattern; 255 let Inst{4} = 0b0; 256 let Inst{3-0} = Pd; 257 258 let Defs = !if(!eq (opc{0}, 1), [NZCV], []); 259} 260 261multiclass sve_int_ptrue<bits<3> opc, string asm> { 262 def _B : sve_int_ptrue<0b00, opc, asm, PPR8>; 263 def _H : sve_int_ptrue<0b01, opc, asm, PPR16>; 264 def _S : sve_int_ptrue<0b10, opc, asm, PPR32>; 265 def _D : sve_int_ptrue<0b11, opc, asm, PPR64>; 266 267 def : InstAlias<asm # "\t$Pd", 268 (!cast<Instruction>(NAME # _B) PPR8:$Pd, 0b11111), 1>; 269 def : InstAlias<asm # "\t$Pd", 270 (!cast<Instruction>(NAME # _H) PPR16:$Pd, 0b11111), 1>; 271 def : InstAlias<asm # "\t$Pd", 272 (!cast<Instruction>(NAME # _S) PPR32:$Pd, 0b11111), 1>; 273 def : InstAlias<asm # "\t$Pd", 274 (!cast<Instruction>(NAME # _D) PPR64:$Pd, 0b11111), 1>; 275} 276 277let Predicates = [HasSVE] in { 278 defm PTRUE : sve_int_ptrue<0b000, "ptrue">; 279 defm PTRUES : sve_int_ptrue<0b001, "ptrues">; 280} 281 282 283//===----------------------------------------------------------------------===// 284// SVE Predicate Misc Group 285//===----------------------------------------------------------------------===// 286 287class sve_int_pfalse<bits<6> opc, string asm> 288: I<(outs PPR8:$Pd), (ins), 289 asm, "\t$Pd", 290 "", 291 []>, Sched<[]> { 292 bits<4> Pd; 293 let Inst{31-24} = 0b00100101; 294 let Inst{23-22} = opc{5-4}; 295 let Inst{21-19} = 0b011; 296 let Inst{18-16} = opc{3-1}; 297 let Inst{15-10} = 0b111001; 298 let Inst{9} = opc{0}; 299 let Inst{8-4} = 0b00000; 300 let Inst{3-0} = Pd; 301} 302 303class sve_int_ptest<bits<6> opc, string asm> 304: I<(outs), (ins PPRAny:$Pg, PPR8:$Pn), 305 asm, "\t$Pg, $Pn", 306 "", 307 []>, Sched<[]> { 308 bits<4> Pg; 309 bits<4> Pn; 310 let Inst{31-24} = 0b00100101; 311 let Inst{23-22} = opc{5-4}; 312 let Inst{21-19} = 0b010; 313 let Inst{18-16} = opc{3-1}; 314 let Inst{15-14} = 0b11; 315 let Inst{13-10} = Pg; 316 let Inst{9} = opc{0}; 317 let Inst{8-5} = Pn; 318 let Inst{4-0} = 0b00000; 319 320 let Defs = [NZCV]; 321} 322 323class sve_int_pfirst_next<bits<2> sz8_64, bits<5> opc, string asm, 324 PPRRegOp pprty> 325: I<(outs pprty:$Pdn), (ins PPRAny:$Pg, pprty:$_Pdn), 326 asm, "\t$Pdn, $Pg, $_Pdn", 327 "", 328 []>, Sched<[]> { 329 bits<4> Pdn; 330 bits<4> Pg; 331 let Inst{31-24} = 0b00100101; 332 let Inst{23-22} = sz8_64; 333 let Inst{21-19} = 0b011; 334 let Inst{18-16} = opc{4-2}; 335 let Inst{15-11} = 0b11000; 336 let Inst{10-9} = opc{1-0}; 337 let Inst{8-5} = Pg; 338 let Inst{4} = 0; 339 let Inst{3-0} = Pdn; 340 341 let Constraints = "$Pdn = $_Pdn"; 342 let Defs = [NZCV]; 343} 344 345multiclass sve_int_pfirst<bits<5> opc, string asm> { 346 def : sve_int_pfirst_next<0b01, opc, asm, PPR8>; 347} 348 349multiclass sve_int_pnext<bits<5> opc, string asm> { 350 def _B : sve_int_pfirst_next<0b00, opc, asm, PPR8>; 351 def _H : sve_int_pfirst_next<0b01, opc, asm, PPR16>; 352 def _S : sve_int_pfirst_next<0b10, opc, asm, PPR32>; 353 def _D : sve_int_pfirst_next<0b11, opc, asm, PPR64>; 354} 355 356//===----------------------------------------------------------------------===// 357// SVE Predicate Count Group 358//===----------------------------------------------------------------------===// 359 360class sve_int_count_r<bits<2> sz8_64, bits<5> opc, string asm, 361 RegisterOperand dty, PPRRegOp pprty, RegisterOperand sty> 362: I<(outs dty:$Rdn), (ins pprty:$Pg, sty:$_Rdn), 363 asm, "\t$Rdn, $Pg", 364 "", 365 []>, Sched<[]> { 366 bits<5> Rdn; 367 bits<4> Pg; 368 let Inst{31-24} = 0b00100101; 369 let Inst{23-22} = sz8_64; 370 let Inst{21-19} = 0b101; 371 let Inst{18-16} = opc{4-2}; 372 let Inst{15-11} = 0b10001; 373 let Inst{10-9} = opc{1-0}; 374 let Inst{8-5} = Pg; 375 let Inst{4-0} = Rdn; 376 377 // Signed 32bit forms require their GPR operand printed. 378 let AsmString = !if(!eq(opc{4,2-0}, 0b0000), 379 !strconcat(asm, "\t$Rdn, $Pg, $_Rdn"), 380 !strconcat(asm, "\t$Rdn, $Pg")); 381 let Constraints = "$Rdn = $_Rdn"; 382} 383 384multiclass sve_int_count_r_s32<bits<5> opc, string asm> { 385 def _B : sve_int_count_r<0b00, opc, asm, GPR64z, PPR8, GPR64as32>; 386 def _H : sve_int_count_r<0b01, opc, asm, GPR64z, PPR16, GPR64as32>; 387 def _S : sve_int_count_r<0b10, opc, asm, GPR64z, PPR32, GPR64as32>; 388 def _D : sve_int_count_r<0b11, opc, asm, GPR64z, PPR64, GPR64as32>; 389} 390 391multiclass sve_int_count_r_u32<bits<5> opc, string asm> { 392 def _B : sve_int_count_r<0b00, opc, asm, GPR32z, PPR8, GPR32z>; 393 def _H : sve_int_count_r<0b01, opc, asm, GPR32z, PPR16, GPR32z>; 394 def _S : sve_int_count_r<0b10, opc, asm, GPR32z, PPR32, GPR32z>; 395 def _D : sve_int_count_r<0b11, opc, asm, GPR32z, PPR64, GPR32z>; 396} 397 398multiclass sve_int_count_r_x64<bits<5> opc, string asm> { 399 def _B : sve_int_count_r<0b00, opc, asm, GPR64z, PPR8, GPR64z>; 400 def _H : sve_int_count_r<0b01, opc, asm, GPR64z, PPR16, GPR64z>; 401 def _S : sve_int_count_r<0b10, opc, asm, GPR64z, PPR32, GPR64z>; 402 def _D : sve_int_count_r<0b11, opc, asm, GPR64z, PPR64, GPR64z>; 403} 404 405class sve_int_count_v<bits<2> sz8_64, bits<5> opc, string asm, 406 ZPRRegOp zprty, PPRRegOp pprty> 407: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, pprty:$Pm), 408 asm, "\t$Zdn, $Pm", 409 "", 410 []>, Sched<[]> { 411 bits<4> Pm; 412 bits<5> Zdn; 413 let Inst{31-24} = 0b00100101; 414 let Inst{23-22} = sz8_64; 415 let Inst{21-19} = 0b101; 416 let Inst{18-16} = opc{4-2}; 417 let Inst{15-11} = 0b10000; 418 let Inst{10-9} = opc{1-0}; 419 let Inst{8-5} = Pm; 420 let Inst{4-0} = Zdn; 421 422 let Constraints = "$Zdn = $_Zdn"; 423 let DestructiveInstType = Destructive; 424 let ElementSize = ElementSizeNone; 425} 426 427multiclass sve_int_count_v<bits<5> opc, string asm> { 428 def _H : sve_int_count_v<0b01, opc, asm, ZPR16, PPR16>; 429 def _S : sve_int_count_v<0b10, opc, asm, ZPR32, PPR32>; 430 def _D : sve_int_count_v<0b11, opc, asm, ZPR64, PPR64>; 431 432 def : InstAlias<asm # "\t$Zdn, $Pm", 433 (!cast<Instruction>(NAME # "_H") ZPR16:$Zdn, PPRAny:$Pm), 0>; 434 def : InstAlias<asm # "\t$Zdn, $Pm", 435 (!cast<Instruction>(NAME # "_S") ZPR32:$Zdn, PPRAny:$Pm), 0>; 436 def : InstAlias<asm # "\t$Zdn, $Pm", 437 (!cast<Instruction>(NAME # "_D") ZPR64:$Zdn, PPRAny:$Pm), 0>; 438} 439 440class sve_int_pcount_pred<bits<2> sz8_64, bits<4> opc, string asm, 441 PPRRegOp pprty> 442: I<(outs GPR64:$Rd), (ins PPRAny:$Pg, pprty:$Pn), 443 asm, "\t$Rd, $Pg, $Pn", 444 "", 445 []>, Sched<[]> { 446 bits<4> Pg; 447 bits<4> Pn; 448 bits<5> Rd; 449 let Inst{31-24} = 0b00100101; 450 let Inst{23-22} = sz8_64; 451 let Inst{21-19} = 0b100; 452 let Inst{18-16} = opc{3-1}; 453 let Inst{15-14} = 0b10; 454 let Inst{13-10} = Pg; 455 let Inst{9} = opc{0}; 456 let Inst{8-5} = Pn; 457 let Inst{4-0} = Rd; 458} 459 460multiclass sve_int_pcount_pred<bits<4> opc, string asm> { 461 def _B : sve_int_pcount_pred<0b00, opc, asm, PPR8>; 462 def _H : sve_int_pcount_pred<0b01, opc, asm, PPR16>; 463 def _S : sve_int_pcount_pred<0b10, opc, asm, PPR32>; 464 def _D : sve_int_pcount_pred<0b11, opc, asm, PPR64>; 465} 466 467//===----------------------------------------------------------------------===// 468// SVE Element Count Group 469//===----------------------------------------------------------------------===// 470 471class sve_int_count<bits<3> opc, string asm> 472: I<(outs GPR64:$Rd), (ins sve_pred_enum:$pattern, sve_incdec_imm:$imm4), 473 asm, "\t$Rd, $pattern, mul $imm4", 474 "", 475 []>, Sched<[]> { 476 bits<5> Rd; 477 bits<4> imm4; 478 bits<5> pattern; 479 let Inst{31-24} = 0b00000100; 480 let Inst{23-22} = opc{2-1}; 481 let Inst{21-20} = 0b10; 482 let Inst{19-16} = imm4; 483 let Inst{15-11} = 0b11100; 484 let Inst{10} = opc{0}; 485 let Inst{9-5} = pattern; 486 let Inst{4-0} = Rd; 487} 488 489multiclass sve_int_count<bits<3> opc, string asm> { 490 def NAME : sve_int_count<opc, asm>; 491 492 def : InstAlias<asm # "\t$Rd, $pattern", 493 (!cast<Instruction>(NAME) GPR64:$Rd, sve_pred_enum:$pattern, 1), 1>; 494 def : InstAlias<asm # "\t$Rd", 495 (!cast<Instruction>(NAME) GPR64:$Rd, 0b11111, 1), 2>; 496} 497 498class sve_int_countvlv<bits<5> opc, string asm, ZPRRegOp zprty> 499: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4), 500 asm, "\t$Zdn, $pattern, mul $imm4", 501 "", 502 []>, Sched<[]> { 503 bits<5> Zdn; 504 bits<5> pattern; 505 bits<4> imm4; 506 let Inst{31-24} = 0b00000100; 507 let Inst{23-22} = opc{4-3}; 508 let Inst{21} = 0b1; 509 let Inst{20} = opc{2}; 510 let Inst{19-16} = imm4; 511 let Inst{15-12} = 0b1100; 512 let Inst{11-10} = opc{1-0}; 513 let Inst{9-5} = pattern; 514 let Inst{4-0} = Zdn; 515 516 let Constraints = "$Zdn = $_Zdn"; 517 let DestructiveInstType = Destructive; 518 let ElementSize = ElementSizeNone; 519} 520 521multiclass sve_int_countvlv<bits<5> opc, string asm, ZPRRegOp zprty> { 522 def NAME : sve_int_countvlv<opc, asm, zprty>; 523 524 def : InstAlias<asm # "\t$Zdn, $pattern", 525 (!cast<Instruction>(NAME) zprty:$Zdn, sve_pred_enum:$pattern, 1), 1>; 526 def : InstAlias<asm # "\t$Zdn", 527 (!cast<Instruction>(NAME) zprty:$Zdn, 0b11111, 1), 2>; 528} 529 530class sve_int_pred_pattern_a<bits<3> opc, string asm> 531: I<(outs GPR64:$Rdn), (ins GPR64:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4), 532 asm, "\t$Rdn, $pattern, mul $imm4", 533 "", 534 []>, Sched<[]> { 535 bits<5> Rdn; 536 bits<5> pattern; 537 bits<4> imm4; 538 let Inst{31-24} = 0b00000100; 539 let Inst{23-22} = opc{2-1}; 540 let Inst{21-20} = 0b11; 541 let Inst{19-16} = imm4; 542 let Inst{15-11} = 0b11100; 543 let Inst{10} = opc{0}; 544 let Inst{9-5} = pattern; 545 let Inst{4-0} = Rdn; 546 547 let Constraints = "$Rdn = $_Rdn"; 548} 549 550multiclass sve_int_pred_pattern_a<bits<3> opc, string asm> { 551 def NAME : sve_int_pred_pattern_a<opc, asm>; 552 553 def : InstAlias<asm # "\t$Rdn, $pattern", 554 (!cast<Instruction>(NAME) GPR64:$Rdn, sve_pred_enum:$pattern, 1), 1>; 555 def : InstAlias<asm # "\t$Rdn", 556 (!cast<Instruction>(NAME) GPR64:$Rdn, 0b11111, 1), 2>; 557} 558 559class sve_int_pred_pattern_b<bits<5> opc, string asm, RegisterOperand dt, 560 RegisterOperand st> 561: I<(outs dt:$Rdn), (ins st:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4), 562 asm, "\t$Rdn, $pattern, mul $imm4", 563 "", 564 []>, Sched<[]> { 565 bits<5> Rdn; 566 bits<5> pattern; 567 bits<4> imm4; 568 let Inst{31-24} = 0b00000100; 569 let Inst{23-22} = opc{4-3}; 570 let Inst{21} = 0b1; 571 let Inst{20} = opc{2}; 572 let Inst{19-16} = imm4; 573 let Inst{15-12} = 0b1111; 574 let Inst{11-10} = opc{1-0}; 575 let Inst{9-5} = pattern; 576 let Inst{4-0} = Rdn; 577 578 // Signed 32bit forms require their GPR operand printed. 579 let AsmString = !if(!eq(opc{2,0}, 0b00), 580 !strconcat(asm, "\t$Rdn, $_Rdn, $pattern, mul $imm4"), 581 !strconcat(asm, "\t$Rdn, $pattern, mul $imm4")); 582 583 let Constraints = "$Rdn = $_Rdn"; 584} 585 586multiclass sve_int_pred_pattern_b_s32<bits<5> opc, string asm> { 587 def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64as32>; 588 589 def : InstAlias<asm # "\t$Rd, $Rn, $pattern", 590 (!cast<Instruction>(NAME) GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1), 1>; 591 def : InstAlias<asm # "\t$Rd, $Rn", 592 (!cast<Instruction>(NAME) GPR64z:$Rd, GPR64as32:$Rn, 0b11111, 1), 2>; 593} 594 595multiclass sve_int_pred_pattern_b_u32<bits<5> opc, string asm> { 596 def NAME : sve_int_pred_pattern_b<opc, asm, GPR32z, GPR32z>; 597 598 def : InstAlias<asm # "\t$Rdn, $pattern", 599 (!cast<Instruction>(NAME) GPR32z:$Rdn, sve_pred_enum:$pattern, 1), 1>; 600 def : InstAlias<asm # "\t$Rdn", 601 (!cast<Instruction>(NAME) GPR32z:$Rdn, 0b11111, 1), 2>; 602} 603 604multiclass sve_int_pred_pattern_b_x64<bits<5> opc, string asm> { 605 def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64z>; 606 607 def : InstAlias<asm # "\t$Rdn, $pattern", 608 (!cast<Instruction>(NAME) GPR64z:$Rdn, sve_pred_enum:$pattern, 1), 1>; 609 def : InstAlias<asm # "\t$Rdn", 610 (!cast<Instruction>(NAME) GPR64z:$Rdn, 0b11111, 1), 2>; 611} 612 613 614//===----------------------------------------------------------------------===// 615// SVE Permute - Cross Lane Group 616//===----------------------------------------------------------------------===// 617 618class sve_int_perm_dup_r<bits<2> sz8_64, string asm, ZPRRegOp zprty, 619 RegisterClass srcRegType> 620: I<(outs zprty:$Zd), (ins srcRegType:$Rn), 621 asm, "\t$Zd, $Rn", 622 "", 623 []>, Sched<[]> { 624 bits<5> Rn; 625 bits<5> Zd; 626 let Inst{31-24} = 0b00000101; 627 let Inst{23-22} = sz8_64; 628 let Inst{21-10} = 0b100000001110; 629 let Inst{9-5} = Rn; 630 let Inst{4-0} = Zd; 631} 632 633multiclass sve_int_perm_dup_r<string asm> { 634 def _B : sve_int_perm_dup_r<0b00, asm, ZPR8, GPR32sp>; 635 def _H : sve_int_perm_dup_r<0b01, asm, ZPR16, GPR32sp>; 636 def _S : sve_int_perm_dup_r<0b10, asm, ZPR32, GPR32sp>; 637 def _D : sve_int_perm_dup_r<0b11, asm, ZPR64, GPR64sp>; 638 639 def : InstAlias<"mov $Zd, $Rn", 640 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, GPR32sp:$Rn), 1>; 641 def : InstAlias<"mov $Zd, $Rn", 642 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, GPR32sp:$Rn), 1>; 643 def : InstAlias<"mov $Zd, $Rn", 644 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, GPR32sp:$Rn), 1>; 645 def : InstAlias<"mov $Zd, $Rn", 646 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, GPR64sp:$Rn), 1>; 647} 648 649class sve_int_perm_dup_i<bits<5> tsz, Operand immtype, string asm, 650 ZPRRegOp zprty> 651: I<(outs zprty:$Zd), (ins zprty:$Zn, immtype:$idx), 652 asm, "\t$Zd, $Zn$idx", 653 "", 654 []>, Sched<[]> { 655 bits<5> Zd; 656 bits<5> Zn; 657 bits<7> idx; 658 let Inst{31-24} = 0b00000101; 659 let Inst{23-22} = {?,?}; // imm3h 660 let Inst{21} = 0b1; 661 let Inst{20-16} = tsz; 662 let Inst{15-10} = 0b001000; 663 let Inst{9-5} = Zn; 664 let Inst{4-0} = Zd; 665} 666 667multiclass sve_int_perm_dup_i<string asm> { 668 def _B : sve_int_perm_dup_i<{?,?,?,?,1}, sve_elm_idx_extdup_b, asm, ZPR8> { 669 let Inst{23-22} = idx{5-4}; 670 let Inst{20-17} = idx{3-0}; 671 } 672 def _H : sve_int_perm_dup_i<{?,?,?,1,0}, sve_elm_idx_extdup_h, asm, ZPR16> { 673 let Inst{23-22} = idx{4-3}; 674 let Inst{20-18} = idx{2-0}; 675 } 676 def _S : sve_int_perm_dup_i<{?,?,1,0,0}, sve_elm_idx_extdup_s, asm, ZPR32> { 677 let Inst{23-22} = idx{3-2}; 678 let Inst{20-19} = idx{1-0}; 679 } 680 def _D : sve_int_perm_dup_i<{?,1,0,0,0}, sve_elm_idx_extdup_d, asm, ZPR64> { 681 let Inst{23-22} = idx{2-1}; 682 let Inst{20} = idx{0}; 683 } 684 def _Q : sve_int_perm_dup_i<{1,0,0,0,0}, sve_elm_idx_extdup_q, asm, ZPR128> { 685 let Inst{23-22} = idx{1-0}; 686 } 687 688 def : InstAlias<"mov $Zd, $Zn$idx", 689 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, ZPR8:$Zn, sve_elm_idx_extdup_b:$idx), 1>; 690 def : InstAlias<"mov $Zd, $Zn$idx", 691 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, ZPR16:$Zn, sve_elm_idx_extdup_h:$idx), 1>; 692 def : InstAlias<"mov $Zd, $Zn$idx", 693 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, ZPR32:$Zn, sve_elm_idx_extdup_s:$idx), 1>; 694 def : InstAlias<"mov $Zd, $Zn$idx", 695 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, ZPR64:$Zn, sve_elm_idx_extdup_d:$idx), 1>; 696 def : InstAlias<"mov $Zd, $Zn$idx", 697 (!cast<Instruction>(NAME # _Q) ZPR128:$Zd, ZPR128:$Zn, sve_elm_idx_extdup_q:$idx), 1>; 698 def : InstAlias<"mov $Zd, $Bn", 699 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, FPR8asZPR:$Bn, 0), 2>; 700 def : InstAlias<"mov $Zd, $Hn", 701 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, FPR16asZPR:$Hn, 0), 2>; 702 def : InstAlias<"mov $Zd, $Sn", 703 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, FPR32asZPR:$Sn, 0), 2>; 704 def : InstAlias<"mov $Zd, $Dn", 705 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, FPR64asZPR:$Dn, 0), 2>; 706 def : InstAlias<"mov $Zd, $Qn", 707 (!cast<Instruction>(NAME # _Q) ZPR128:$Zd, FPR128asZPR:$Qn, 0), 2>; 708} 709 710class sve_int_perm_tbl<bits<2> sz8_64, bits<2> opc, string asm, 711 ZPRRegOp zprty, RegisterOperand VecList> 712: I<(outs zprty:$Zd), (ins VecList:$Zn, zprty:$Zm), 713 asm, "\t$Zd, $Zn, $Zm", 714 "", 715 []>, Sched<[]> { 716 bits<5> Zd; 717 bits<5> Zm; 718 bits<5> Zn; 719 let Inst{31-24} = 0b00000101; 720 let Inst{23-22} = sz8_64; 721 let Inst{21} = 0b1; 722 let Inst{20-16} = Zm; 723 let Inst{15-13} = 0b001; 724 let Inst{12-11} = opc; 725 let Inst{10} = 0b0; 726 let Inst{9-5} = Zn; 727 let Inst{4-0} = Zd; 728} 729 730multiclass sve_int_perm_tbl<string asm> { 731 def _B : sve_int_perm_tbl<0b00, 0b10, asm, ZPR8, Z_b>; 732 def _H : sve_int_perm_tbl<0b01, 0b10, asm, ZPR16, Z_h>; 733 def _S : sve_int_perm_tbl<0b10, 0b10, asm, ZPR32, Z_s>; 734 def _D : sve_int_perm_tbl<0b11, 0b10, asm, ZPR64, Z_d>; 735 736 def : InstAlias<asm # "\t$Zd, $Zn, $Zm", 737 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 0>; 738 def : InstAlias<asm # "\t$Zd, $Zn, $Zm", 739 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, ZPR16:$Zn, ZPR16:$Zm), 0>; 740 def : InstAlias<asm # "\t$Zd, $Zn, $Zm", 741 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, ZPR32:$Zn, ZPR32:$Zm), 0>; 742 def : InstAlias<asm # "\t$Zd, $Zn, $Zm", 743 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zm), 0>; 744} 745 746multiclass sve2_int_perm_tbl<string asm> { 747 def _B : sve_int_perm_tbl<0b00, 0b01, asm, ZPR8, ZZ_b>; 748 def _H : sve_int_perm_tbl<0b01, 0b01, asm, ZPR16, ZZ_h>; 749 def _S : sve_int_perm_tbl<0b10, 0b01, asm, ZPR32, ZZ_s>; 750 def _D : sve_int_perm_tbl<0b11, 0b01, asm, ZPR64, ZZ_d>; 751} 752 753class sve2_int_perm_tbx<bits<2> sz8_64, string asm, ZPRRegOp zprty> 754: I<(outs zprty:$Zd), (ins zprty:$_Zd, zprty:$Zn, zprty:$Zm), 755 asm, "\t$Zd, $Zn, $Zm", 756 "", 757 []>, Sched<[]> { 758 bits<5> Zd; 759 bits<5> Zm; 760 bits<5> Zn; 761 let Inst{31-24} = 0b00000101; 762 let Inst{23-22} = sz8_64; 763 let Inst{21} = 0b1; 764 let Inst{20-16} = Zm; 765 let Inst{15-10} = 0b001011; 766 let Inst{9-5} = Zn; 767 let Inst{4-0} = Zd; 768 769 let Constraints = "$Zd = $_Zd"; 770} 771 772multiclass sve2_int_perm_tbx<string asm> { 773 def _B : sve2_int_perm_tbx<0b00, asm, ZPR8>; 774 def _H : sve2_int_perm_tbx<0b01, asm, ZPR16>; 775 def _S : sve2_int_perm_tbx<0b10, asm, ZPR32>; 776 def _D : sve2_int_perm_tbx<0b11, asm, ZPR64>; 777} 778 779class sve_int_perm_reverse_z<bits<2> sz8_64, string asm, ZPRRegOp zprty> 780: I<(outs zprty:$Zd), (ins zprty:$Zn), 781 asm, "\t$Zd, $Zn", 782 "", 783 []>, Sched<[]> { 784 bits<5> Zd; 785 bits<5> Zn; 786 let Inst{31-24} = 0b00000101; 787 let Inst{23-22} = sz8_64; 788 let Inst{21-10} = 0b111000001110; 789 let Inst{9-5} = Zn; 790 let Inst{4-0} = Zd; 791} 792 793multiclass sve_int_perm_reverse_z<string asm> { 794 def _B : sve_int_perm_reverse_z<0b00, asm, ZPR8>; 795 def _H : sve_int_perm_reverse_z<0b01, asm, ZPR16>; 796 def _S : sve_int_perm_reverse_z<0b10, asm, ZPR32>; 797 def _D : sve_int_perm_reverse_z<0b11, asm, ZPR64>; 798} 799 800class sve_int_perm_reverse_p<bits<2> sz8_64, string asm, PPRRegOp pprty> 801: I<(outs pprty:$Pd), (ins pprty:$Pn), 802 asm, "\t$Pd, $Pn", 803 "", 804 []>, Sched<[]> { 805 bits<4> Pd; 806 bits<4> Pn; 807 let Inst{31-24} = 0b00000101; 808 let Inst{23-22} = sz8_64; 809 let Inst{21-9} = 0b1101000100000; 810 let Inst{8-5} = Pn; 811 let Inst{4} = 0b0; 812 let Inst{3-0} = Pd; 813} 814 815multiclass sve_int_perm_reverse_p<string asm> { 816 def _B : sve_int_perm_reverse_p<0b00, asm, PPR8>; 817 def _H : sve_int_perm_reverse_p<0b01, asm, PPR16>; 818 def _S : sve_int_perm_reverse_p<0b10, asm, PPR32>; 819 def _D : sve_int_perm_reverse_p<0b11, asm, PPR64>; 820} 821 822class sve_int_perm_unpk<bits<2> sz16_64, bits<2> opc, string asm, 823 ZPRRegOp zprty1, ZPRRegOp zprty2> 824: I<(outs zprty1:$Zd), (ins zprty2:$Zn), 825 asm, "\t$Zd, $Zn", 826 "", []>, Sched<[]> { 827 bits<5> Zd; 828 bits<5> Zn; 829 let Inst{31-24} = 0b00000101; 830 let Inst{23-22} = sz16_64; 831 let Inst{21-18} = 0b1100; 832 let Inst{17-16} = opc; 833 let Inst{15-10} = 0b001110; 834 let Inst{9-5} = Zn; 835 let Inst{4-0} = Zd; 836} 837 838multiclass sve_int_perm_unpk<bits<2> opc, string asm> { 839 def _H : sve_int_perm_unpk<0b01, opc, asm, ZPR16, ZPR8>; 840 def _S : sve_int_perm_unpk<0b10, opc, asm, ZPR32, ZPR16>; 841 def _D : sve_int_perm_unpk<0b11, opc, asm, ZPR64, ZPR32>; 842} 843 844class sve_int_perm_insrs<bits<2> sz8_64, string asm, ZPRRegOp zprty, 845 RegisterClass srcRegType> 846: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Rm), 847 asm, "\t$Zdn, $Rm", 848 "", 849 []>, Sched<[]> { 850 bits<5> Rm; 851 bits<5> Zdn; 852 let Inst{31-24} = 0b00000101; 853 let Inst{23-22} = sz8_64; 854 let Inst{21-10} = 0b100100001110; 855 let Inst{9-5} = Rm; 856 let Inst{4-0} = Zdn; 857 858 let Constraints = "$Zdn = $_Zdn"; 859 let DestructiveInstType = Destructive; 860 let ElementSize = ElementSizeNone; 861} 862 863multiclass sve_int_perm_insrs<string asm> { 864 def _B : sve_int_perm_insrs<0b00, asm, ZPR8, GPR32>; 865 def _H : sve_int_perm_insrs<0b01, asm, ZPR16, GPR32>; 866 def _S : sve_int_perm_insrs<0b10, asm, ZPR32, GPR32>; 867 def _D : sve_int_perm_insrs<0b11, asm, ZPR64, GPR64>; 868} 869 870class sve_int_perm_insrv<bits<2> sz8_64, string asm, ZPRRegOp zprty, 871 RegisterClass srcRegType> 872: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Vm), 873 asm, "\t$Zdn, $Vm", 874 "", 875 []>, Sched<[]> { 876 bits<5> Vm; 877 bits<5> Zdn; 878 let Inst{31-24} = 0b00000101; 879 let Inst{23-22} = sz8_64; 880 let Inst{21-10} = 0b110100001110; 881 let Inst{9-5} = Vm; 882 let Inst{4-0} = Zdn; 883 884 let Constraints = "$Zdn = $_Zdn"; 885 let DestructiveInstType = Destructive; 886 let ElementSize = ElementSizeNone; 887} 888 889multiclass sve_int_perm_insrv<string asm> { 890 def _B : sve_int_perm_insrv<0b00, asm, ZPR8, FPR8>; 891 def _H : sve_int_perm_insrv<0b01, asm, ZPR16, FPR16>; 892 def _S : sve_int_perm_insrv<0b10, asm, ZPR32, FPR32>; 893 def _D : sve_int_perm_insrv<0b11, asm, ZPR64, FPR64>; 894} 895 896//===----------------------------------------------------------------------===// 897// SVE Permute - Extract Group 898//===----------------------------------------------------------------------===// 899 900class sve_int_perm_extract_i<string asm> 901: I<(outs ZPR8:$Zdn), (ins ZPR8:$_Zdn, ZPR8:$Zm, imm0_255:$imm8), 902 asm, "\t$Zdn, $_Zdn, $Zm, $imm8", 903 "", []>, Sched<[]> { 904 bits<5> Zdn; 905 bits<5> Zm; 906 bits<8> imm8; 907 let Inst{31-21} = 0b00000101001; 908 let Inst{20-16} = imm8{7-3}; 909 let Inst{15-13} = 0b000; 910 let Inst{12-10} = imm8{2-0}; 911 let Inst{9-5} = Zm; 912 let Inst{4-0} = Zdn; 913 914 let Constraints = "$Zdn = $_Zdn"; 915 let DestructiveInstType = Destructive; 916 let ElementSize = ElementSizeNone; 917} 918 919class sve2_int_perm_extract_i_cons<string asm> 920: I<(outs ZPR8:$Zd), (ins ZZ_b:$Zn, imm0_255:$imm8), 921 asm, "\t$Zd, $Zn, $imm8", 922 "", []>, Sched<[]> { 923 bits<5> Zd; 924 bits<5> Zn; 925 bits<8> imm8; 926 let Inst{31-21} = 0b00000101011; 927 let Inst{20-16} = imm8{7-3}; 928 let Inst{15-13} = 0b000; 929 let Inst{12-10} = imm8{2-0}; 930 let Inst{9-5} = Zn; 931 let Inst{4-0} = Zd; 932} 933 934//===----------------------------------------------------------------------===// 935// SVE Vector Select Group 936//===----------------------------------------------------------------------===// 937 938class sve_int_sel_vvv<bits<2> sz8_64, string asm, ZPRRegOp zprty> 939: I<(outs zprty:$Zd), (ins PPRAny:$Pg, zprty:$Zn, zprty:$Zm), 940 asm, "\t$Zd, $Pg, $Zn, $Zm", 941 "", 942 []>, Sched<[]> { 943 bits<4> Pg; 944 bits<5> Zd; 945 bits<5> Zm; 946 bits<5> Zn; 947 let Inst{31-24} = 0b00000101; 948 let Inst{23-22} = sz8_64; 949 let Inst{21} = 0b1; 950 let Inst{20-16} = Zm; 951 let Inst{15-14} = 0b11; 952 let Inst{13-10} = Pg; 953 let Inst{9-5} = Zn; 954 let Inst{4-0} = Zd; 955} 956 957multiclass sve_int_sel_vvv<string asm> { 958 def _B : sve_int_sel_vvv<0b00, asm, ZPR8>; 959 def _H : sve_int_sel_vvv<0b01, asm, ZPR16>; 960 def _S : sve_int_sel_vvv<0b10, asm, ZPR32>; 961 def _D : sve_int_sel_vvv<0b11, asm, ZPR64>; 962 963 def : InstAlias<"mov $Zd, $Pg/m, $Zn", 964 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd), 1>; 965 def : InstAlias<"mov $Zd, $Pg/m, $Zn", 966 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, ZPR16:$Zn, ZPR16:$Zd), 1>; 967 def : InstAlias<"mov $Zd, $Pg/m, $Zn", 968 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, ZPR32:$Zn, ZPR32:$Zd), 1>; 969 def : InstAlias<"mov $Zd, $Pg/m, $Zn", 970 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, ZPR64:$Zn, ZPR64:$Zd), 1>; 971} 972 973 974//===----------------------------------------------------------------------===// 975// SVE Predicate Logical Operations Group 976//===----------------------------------------------------------------------===// 977 978class sve_int_pred_log<bits<4> opc, string asm> 979: I<(outs PPR8:$Pd), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$Pm), 980 asm, "\t$Pd, $Pg/z, $Pn, $Pm", 981 "", 982 []>, Sched<[]> { 983 bits<4> Pd; 984 bits<4> Pg; 985 bits<4> Pm; 986 bits<4> Pn; 987 let Inst{31-24} = 0b00100101; 988 let Inst{23-22} = opc{3-2}; 989 let Inst{21-20} = 0b00; 990 let Inst{19-16} = Pm; 991 let Inst{15-14} = 0b01; 992 let Inst{13-10} = Pg; 993 let Inst{9} = opc{1}; 994 let Inst{8-5} = Pn; 995 let Inst{4} = opc{0}; 996 let Inst{3-0} = Pd; 997 998 // SEL has no predication qualifier. 999 let AsmString = !if(!eq(opc, 0b0011), 1000 !strconcat(asm, "\t$Pd, $Pg, $Pn, $Pm"), 1001 !strconcat(asm, "\t$Pd, $Pg/z, $Pn, $Pm")); 1002 1003 let Defs = !if(!eq (opc{2}, 1), [NZCV], []); 1004} 1005 1006 1007//===----------------------------------------------------------------------===// 1008// SVE Logical Mask Immediate Group 1009//===----------------------------------------------------------------------===// 1010 1011class sve_int_log_imm<bits<2> opc, string asm> 1012: I<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, logical_imm64:$imms13), 1013 asm, "\t$Zdn, $_Zdn, $imms13", 1014 "", []>, Sched<[]> { 1015 bits<5> Zdn; 1016 bits<13> imms13; 1017 let Inst{31-24} = 0b00000101; 1018 let Inst{23-22} = opc; 1019 let Inst{21-18} = 0b0000; 1020 let Inst{17-5} = imms13; 1021 let Inst{4-0} = Zdn; 1022 1023 let Constraints = "$Zdn = $_Zdn"; 1024 let DecoderMethod = "DecodeSVELogicalImmInstruction"; 1025 let DestructiveInstType = Destructive; 1026 let ElementSize = ElementSizeNone; 1027} 1028 1029multiclass sve_int_log_imm<bits<2> opc, string asm, string alias> { 1030 def NAME : sve_int_log_imm<opc, asm>; 1031 1032 def : InstAlias<asm # "\t$Zdn, $Zdn, $imm", 1033 (!cast<Instruction>(NAME) ZPR8:$Zdn, sve_logical_imm8:$imm), 4>; 1034 def : InstAlias<asm # "\t$Zdn, $Zdn, $imm", 1035 (!cast<Instruction>(NAME) ZPR16:$Zdn, sve_logical_imm16:$imm), 3>; 1036 def : InstAlias<asm # "\t$Zdn, $Zdn, $imm", 1037 (!cast<Instruction>(NAME) ZPR32:$Zdn, sve_logical_imm32:$imm), 2>; 1038 1039 def : InstAlias<alias # "\t$Zdn, $Zdn, $imm", 1040 (!cast<Instruction>(NAME) ZPR8:$Zdn, sve_logical_imm8_not:$imm), 0>; 1041 def : InstAlias<alias # "\t$Zdn, $Zdn, $imm", 1042 (!cast<Instruction>(NAME) ZPR16:$Zdn, sve_logical_imm16_not:$imm), 0>; 1043 def : InstAlias<alias # "\t$Zdn, $Zdn, $imm", 1044 (!cast<Instruction>(NAME) ZPR32:$Zdn, sve_logical_imm32_not:$imm), 0>; 1045 def : InstAlias<alias # "\t$Zdn, $Zdn, $imm", 1046 (!cast<Instruction>(NAME) ZPR64:$Zdn, logical_imm64_not:$imm), 0>; 1047} 1048 1049class sve_int_dup_mask_imm<string asm> 1050: I<(outs ZPR64:$Zd), (ins logical_imm64:$imms), 1051 asm, "\t$Zd, $imms", 1052 "", 1053 []>, Sched<[]> { 1054 bits<5> Zd; 1055 bits<13> imms; 1056 let Inst{31-18} = 0b00000101110000; 1057 let Inst{17-5} = imms; 1058 let Inst{4-0} = Zd; 1059 1060 let isReMaterializable = 1; 1061 let DecoderMethod = "DecodeSVELogicalImmInstruction"; 1062} 1063 1064multiclass sve_int_dup_mask_imm<string asm> { 1065 def NAME : sve_int_dup_mask_imm<asm>; 1066 1067 def : InstAlias<"dupm $Zd, $imm", 1068 (!cast<Instruction>(NAME) ZPR8:$Zd, sve_logical_imm8:$imm), 4>; 1069 def : InstAlias<"dupm $Zd, $imm", 1070 (!cast<Instruction>(NAME) ZPR16:$Zd, sve_logical_imm16:$imm), 3>; 1071 def : InstAlias<"dupm $Zd, $imm", 1072 (!cast<Instruction>(NAME) ZPR32:$Zd, sve_logical_imm32:$imm), 2>; 1073 1074 // All Zd.b forms have a CPY/DUP equivalent, hence no byte alias here. 1075 def : InstAlias<"mov $Zd, $imm", 1076 (!cast<Instruction>(NAME) ZPR16:$Zd, sve_preferred_logical_imm16:$imm), 7>; 1077 def : InstAlias<"mov $Zd, $imm", 1078 (!cast<Instruction>(NAME) ZPR32:$Zd, sve_preferred_logical_imm32:$imm), 6>; 1079 def : InstAlias<"mov $Zd, $imm", 1080 (!cast<Instruction>(NAME) ZPR64:$Zd, sve_preferred_logical_imm64:$imm), 5>; 1081} 1082 1083//===----------------------------------------------------------------------===// 1084// SVE Integer Arithmetic - Unpredicated Group. 1085//===----------------------------------------------------------------------===// 1086 1087class sve_int_bin_cons_arit_0<bits<2> sz8_64, bits<3> opc, string asm, 1088 ZPRRegOp zprty> 1089: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), 1090 asm, "\t$Zd, $Zn, $Zm", 1091 "", []>, Sched<[]> { 1092 bits<5> Zd; 1093 bits<5> Zm; 1094 bits<5> Zn; 1095 let Inst{31-24} = 0b00000100; 1096 let Inst{23-22} = sz8_64; 1097 let Inst{21} = 0b1; 1098 let Inst{20-16} = Zm; 1099 let Inst{15-13} = 0b000; 1100 let Inst{12-10} = opc; 1101 let Inst{9-5} = Zn; 1102 let Inst{4-0} = Zd; 1103} 1104 1105multiclass sve_int_bin_cons_arit_0<bits<3> opc, string asm> { 1106 def _B : sve_int_bin_cons_arit_0<0b00, opc, asm, ZPR8>; 1107 def _H : sve_int_bin_cons_arit_0<0b01, opc, asm, ZPR16>; 1108 def _S : sve_int_bin_cons_arit_0<0b10, opc, asm, ZPR32>; 1109 def _D : sve_int_bin_cons_arit_0<0b11, opc, asm, ZPR64>; 1110} 1111 1112//===----------------------------------------------------------------------===// 1113// SVE Floating Point Arithmetic - Predicated Group 1114//===----------------------------------------------------------------------===// 1115 1116class sve_fp_2op_i_p_zds<bits<2> sz, bits<3> opc, string asm, 1117 ZPRRegOp zprty, 1118 Operand imm_ty> 1119: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, imm_ty:$i1), 1120 asm, "\t$Zdn, $Pg/m, $_Zdn, $i1", 1121 "", 1122 []>, Sched<[]> { 1123 bits<3> Pg; 1124 bits<5> Zdn; 1125 bit i1; 1126 let Inst{31-24} = 0b01100101; 1127 let Inst{23-22} = sz; 1128 let Inst{21-19} = 0b011; 1129 let Inst{18-16} = opc; 1130 let Inst{15-13} = 0b100; 1131 let Inst{12-10} = Pg; 1132 let Inst{9-6} = 0b0000; 1133 let Inst{5} = i1; 1134 let Inst{4-0} = Zdn; 1135 1136 let Constraints = "$Zdn = $_Zdn"; 1137 let DestructiveInstType = Destructive; 1138 let ElementSize = zprty.ElementSize; 1139} 1140 1141multiclass sve_fp_2op_i_p_zds<bits<3> opc, string asm, Operand imm_ty> { 1142 def _H : sve_fp_2op_i_p_zds<0b01, opc, asm, ZPR16, imm_ty>; 1143 def _S : sve_fp_2op_i_p_zds<0b10, opc, asm, ZPR32, imm_ty>; 1144 def _D : sve_fp_2op_i_p_zds<0b11, opc, asm, ZPR64, imm_ty>; 1145} 1146 1147class sve_fp_2op_p_zds<bits<2> sz, bits<4> opc, string asm, 1148 ZPRRegOp zprty> 1149: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), 1150 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", 1151 "", 1152 []>, Sched<[]> { 1153 bits<3> Pg; 1154 bits<5> Zdn; 1155 bits<5> Zm; 1156 let Inst{31-24} = 0b01100101; 1157 let Inst{23-22} = sz; 1158 let Inst{21-20} = 0b00; 1159 let Inst{19-16} = opc; 1160 let Inst{15-13} = 0b100; 1161 let Inst{12-10} = Pg; 1162 let Inst{9-5} = Zm; 1163 let Inst{4-0} = Zdn; 1164 1165 let Constraints = "$Zdn = $_Zdn"; 1166 let DestructiveInstType = Destructive; 1167 let ElementSize = zprty.ElementSize; 1168} 1169 1170multiclass sve_fp_2op_p_zds<bits<4> opc, string asm> { 1171 def _H : sve_fp_2op_p_zds<0b01, opc, asm, ZPR16>; 1172 def _S : sve_fp_2op_p_zds<0b10, opc, asm, ZPR32>; 1173 def _D : sve_fp_2op_p_zds<0b11, opc, asm, ZPR64>; 1174} 1175 1176class sve_fp_ftmad<bits<2> sz, string asm, ZPRRegOp zprty> 1177: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, imm0_7:$imm3), 1178 asm, "\t$Zdn, $_Zdn, $Zm, $imm3", 1179 "", 1180 []>, Sched<[]> { 1181 bits<5> Zdn; 1182 bits<5> Zm; 1183 bits<3> imm3; 1184 let Inst{31-24} = 0b01100101; 1185 let Inst{23-22} = sz; 1186 let Inst{21-19} = 0b010; 1187 let Inst{18-16} = imm3; 1188 let Inst{15-10} = 0b100000; 1189 let Inst{9-5} = Zm; 1190 let Inst{4-0} = Zdn; 1191 1192 let Constraints = "$Zdn = $_Zdn"; 1193 let DestructiveInstType = Destructive; 1194 let ElementSize = ElementSizeNone; 1195} 1196 1197multiclass sve_fp_ftmad<string asm> { 1198 def _H : sve_fp_ftmad<0b01, asm, ZPR16>; 1199 def _S : sve_fp_ftmad<0b10, asm, ZPR32>; 1200 def _D : sve_fp_ftmad<0b11, asm, ZPR64>; 1201} 1202 1203 1204//===----------------------------------------------------------------------===// 1205// SVE Floating Point Arithmetic - Unpredicated Group 1206//===----------------------------------------------------------------------===// 1207 1208class sve_fp_3op_u_zd<bits<2> sz, bits<3> opc, string asm, 1209 ZPRRegOp zprty> 1210: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), 1211 asm, "\t$Zd, $Zn, $Zm", 1212 "", []>, Sched<[]> { 1213 bits<5> Zd; 1214 bits<5> Zm; 1215 bits<5> Zn; 1216 let Inst{31-24} = 0b01100101; 1217 let Inst{23-22} = sz; 1218 let Inst{21} = 0b0; 1219 let Inst{20-16} = Zm; 1220 let Inst{15-13} = 0b000; 1221 let Inst{12-10} = opc; 1222 let Inst{9-5} = Zn; 1223 let Inst{4-0} = Zd; 1224} 1225 1226multiclass sve_fp_3op_u_zd<bits<3> opc, string asm> { 1227 def _H : sve_fp_3op_u_zd<0b01, opc, asm, ZPR16>; 1228 def _S : sve_fp_3op_u_zd<0b10, opc, asm, ZPR32>; 1229 def _D : sve_fp_3op_u_zd<0b11, opc, asm, ZPR64>; 1230} 1231 1232//===----------------------------------------------------------------------===// 1233// SVE Floating Point Fused Multiply-Add Group 1234//===----------------------------------------------------------------------===// 1235 1236class sve_fp_3op_p_zds_a<bits<2> sz, bits<2> opc, string asm, ZPRRegOp zprty> 1237: I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm), 1238 asm, "\t$Zda, $Pg/m, $Zn, $Zm", 1239 "", 1240 []>, Sched<[]> { 1241 bits<3> Pg; 1242 bits<5> Zda; 1243 bits<5> Zm; 1244 bits<5> Zn; 1245 let Inst{31-24} = 0b01100101; 1246 let Inst{23-22} = sz; 1247 let Inst{21} = 0b1; 1248 let Inst{20-16} = Zm; 1249 let Inst{15} = 0b0; 1250 let Inst{14-13} = opc; 1251 let Inst{12-10} = Pg; 1252 let Inst{9-5} = Zn; 1253 let Inst{4-0} = Zda; 1254 1255 let Constraints = "$Zda = $_Zda"; 1256 let DestructiveInstType = Destructive; 1257 let ElementSize = zprty.ElementSize; 1258} 1259 1260multiclass sve_fp_3op_p_zds_a<bits<2> opc, string asm> { 1261 def _H : sve_fp_3op_p_zds_a<0b01, opc, asm, ZPR16>; 1262 def _S : sve_fp_3op_p_zds_a<0b10, opc, asm, ZPR32>; 1263 def _D : sve_fp_3op_p_zds_a<0b11, opc, asm, ZPR64>; 1264} 1265 1266class sve_fp_3op_p_zds_b<bits<2> sz, bits<2> opc, string asm, 1267 ZPRRegOp zprty> 1268: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za), 1269 asm, "\t$Zdn, $Pg/m, $Zm, $Za", 1270 "", 1271 []>, Sched<[]> { 1272 bits<3> Pg; 1273 bits<5> Za; 1274 bits<5> Zdn; 1275 bits<5> Zm; 1276 let Inst{31-24} = 0b01100101; 1277 let Inst{23-22} = sz; 1278 let Inst{21} = 0b1; 1279 let Inst{20-16} = Za; 1280 let Inst{15} = 0b1; 1281 let Inst{14-13} = opc; 1282 let Inst{12-10} = Pg; 1283 let Inst{9-5} = Zm; 1284 let Inst{4-0} = Zdn; 1285 1286 let Constraints = "$Zdn = $_Zdn"; 1287 let DestructiveInstType = Destructive; 1288 let ElementSize = zprty.ElementSize; 1289} 1290 1291multiclass sve_fp_3op_p_zds_b<bits<2> opc, string asm> { 1292 def _H : sve_fp_3op_p_zds_b<0b01, opc, asm, ZPR16>; 1293 def _S : sve_fp_3op_p_zds_b<0b10, opc, asm, ZPR32>; 1294 def _D : sve_fp_3op_p_zds_b<0b11, opc, asm, ZPR64>; 1295} 1296 1297//===----------------------------------------------------------------------===// 1298// SVE Floating Point Multiply-Add - Indexed Group 1299//===----------------------------------------------------------------------===// 1300 1301class sve_fp_fma_by_indexed_elem<bits<2> sz, bit opc, string asm, 1302 ZPRRegOp zprty1, 1303 ZPRRegOp zprty2, Operand itype> 1304: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty1:$Zn, zprty2:$Zm, itype:$iop), 1305 asm, "\t$Zda, $Zn, $Zm$iop", "", []>, Sched<[]> { 1306 bits<5> Zda; 1307 bits<5> Zn; 1308 let Inst{31-24} = 0b01100100; 1309 let Inst{23-22} = sz; 1310 let Inst{21} = 0b1; 1311 let Inst{15-11} = 0; 1312 let Inst{10} = opc; 1313 let Inst{9-5} = Zn; 1314 let Inst{4-0} = Zda; 1315 1316 let Constraints = "$Zda = $_Zda"; 1317 let DestructiveInstType = Destructive; 1318 let ElementSize = ElementSizeNone; 1319} 1320 1321multiclass sve_fp_fma_by_indexed_elem<bit opc, string asm> { 1322 def _H : sve_fp_fma_by_indexed_elem<{0, ?}, opc, asm, ZPR16, ZPR3b16, VectorIndexH> { 1323 bits<3> Zm; 1324 bits<3> iop; 1325 let Inst{22} = iop{2}; 1326 let Inst{20-19} = iop{1-0}; 1327 let Inst{18-16} = Zm; 1328 } 1329 def _S : sve_fp_fma_by_indexed_elem<0b10, opc, asm, ZPR32, ZPR3b32, VectorIndexS> { 1330 bits<3> Zm; 1331 bits<2> iop; 1332 let Inst{20-19} = iop; 1333 let Inst{18-16} = Zm; 1334 } 1335 def _D : sve_fp_fma_by_indexed_elem<0b11, opc, asm, ZPR64, ZPR4b64, VectorIndexD> { 1336 bits<4> Zm; 1337 bit iop; 1338 let Inst{20} = iop; 1339 let Inst{19-16} = Zm; 1340 } 1341} 1342 1343 1344//===----------------------------------------------------------------------===// 1345// SVE Floating Point Multiply - Indexed Group 1346//===----------------------------------------------------------------------===// 1347 1348class sve_fp_fmul_by_indexed_elem<bits<2> sz, string asm, ZPRRegOp zprty, 1349 ZPRRegOp zprty2, Operand itype> 1350: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty2:$Zm, itype:$iop), 1351 asm, "\t$Zd, $Zn, $Zm$iop", "", []>, Sched<[]> { 1352 bits<5> Zd; 1353 bits<5> Zn; 1354 let Inst{31-24} = 0b01100100; 1355 let Inst{23-22} = sz; 1356 let Inst{21} = 0b1; 1357 let Inst{15-10} = 0b001000; 1358 let Inst{9-5} = Zn; 1359 let Inst{4-0} = Zd; 1360} 1361 1362multiclass sve_fp_fmul_by_indexed_elem<string asm> { 1363 def _H : sve_fp_fmul_by_indexed_elem<{0, ?}, asm, ZPR16, ZPR3b16, VectorIndexH> { 1364 bits<3> Zm; 1365 bits<3> iop; 1366 let Inst{22} = iop{2}; 1367 let Inst{20-19} = iop{1-0}; 1368 let Inst{18-16} = Zm; 1369 } 1370 def _S : sve_fp_fmul_by_indexed_elem<0b10, asm, ZPR32, ZPR3b32, VectorIndexS> { 1371 bits<3> Zm; 1372 bits<2> iop; 1373 let Inst{20-19} = iop; 1374 let Inst{18-16} = Zm; 1375 } 1376 def _D : sve_fp_fmul_by_indexed_elem<0b11, asm, ZPR64, ZPR4b64, VectorIndexD> { 1377 bits<4> Zm; 1378 bit iop; 1379 let Inst{20} = iop; 1380 let Inst{19-16} = Zm; 1381 } 1382} 1383 1384//===----------------------------------------------------------------------===// 1385// SVE Floating Point Complex Multiply-Add Group 1386//===----------------------------------------------------------------------===// 1387 1388class sve_fp_fcmla<bits<2> sz, string asm, ZPRRegOp zprty> 1389: I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm, 1390 complexrotateop:$imm), 1391 asm, "\t$Zda, $Pg/m, $Zn, $Zm, $imm", 1392 "", []>, Sched<[]> { 1393 bits<5> Zda; 1394 bits<3> Pg; 1395 bits<5> Zn; 1396 bits<5> Zm; 1397 bits<2> imm; 1398 let Inst{31-24} = 0b01100100; 1399 let Inst{23-22} = sz; 1400 let Inst{21} = 0; 1401 let Inst{20-16} = Zm; 1402 let Inst{15} = 0; 1403 let Inst{14-13} = imm; 1404 let Inst{12-10} = Pg; 1405 let Inst{9-5} = Zn; 1406 let Inst{4-0} = Zda; 1407 1408 let Constraints = "$Zda = $_Zda"; 1409 let DestructiveInstType = Destructive; 1410 let ElementSize = zprty.ElementSize; 1411} 1412 1413multiclass sve_fp_fcmla<string asm> { 1414 def _H : sve_fp_fcmla<0b01, asm, ZPR16>; 1415 def _S : sve_fp_fcmla<0b10, asm, ZPR32>; 1416 def _D : sve_fp_fcmla<0b11, asm, ZPR64>; 1417} 1418 1419//===----------------------------------------------------------------------===// 1420// SVE Floating Point Complex Multiply-Add - Indexed Group 1421//===----------------------------------------------------------------------===// 1422 1423class sve_fp_fcmla_by_indexed_elem<bits<2> sz, string asm, 1424 ZPRRegOp zprty, 1425 ZPRRegOp zprty2, Operand itype> 1426: I<(outs zprty:$Zda), (ins zprty:$_Zda, zprty:$Zn, zprty2:$Zm, itype:$iop, 1427 complexrotateop:$imm), 1428 asm, "\t$Zda, $Zn, $Zm$iop, $imm", 1429 "", []>, Sched<[]> { 1430 bits<5> Zda; 1431 bits<5> Zn; 1432 bits<2> imm; 1433 let Inst{31-24} = 0b01100100; 1434 let Inst{23-22} = sz; 1435 let Inst{21} = 0b1; 1436 let Inst{15-12} = 0b0001; 1437 let Inst{11-10} = imm; 1438 let Inst{9-5} = Zn; 1439 let Inst{4-0} = Zda; 1440 1441 let Constraints = "$Zda = $_Zda"; 1442 let DestructiveInstType = Destructive; 1443 let ElementSize = ElementSizeNone; 1444} 1445 1446multiclass sve_fp_fcmla_by_indexed_elem<string asm> { 1447 def _H : sve_fp_fcmla_by_indexed_elem<0b10, asm, ZPR16, ZPR3b16, VectorIndexS> { 1448 bits<3> Zm; 1449 bits<2> iop; 1450 let Inst{20-19} = iop; 1451 let Inst{18-16} = Zm; 1452 } 1453 def _S : sve_fp_fcmla_by_indexed_elem<0b11, asm, ZPR32, ZPR4b32, VectorIndexD> { 1454 bits<4> Zm; 1455 bits<1> iop; 1456 let Inst{20} = iop; 1457 let Inst{19-16} = Zm; 1458 } 1459} 1460 1461//===----------------------------------------------------------------------===// 1462// SVE Floating Point Complex Addition Group 1463//===----------------------------------------------------------------------===// 1464 1465class sve_fp_fcadd<bits<2> sz, string asm, ZPRRegOp zprty> 1466: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, 1467 complexrotateopodd:$imm), 1468 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm, $imm", 1469 "", 1470 []>, Sched<[]> { 1471 bits<5> Zdn; 1472 bits<5> Zm; 1473 bits<3> Pg; 1474 bit imm; 1475 let Inst{31-24} = 0b01100100; 1476 let Inst{23-22} = sz; 1477 let Inst{21-17} = 0; 1478 let Inst{16} = imm; 1479 let Inst{15-13} = 0b100; 1480 let Inst{12-10} = Pg; 1481 let Inst{9-5} = Zm; 1482 let Inst{4-0} = Zdn; 1483 1484 let Constraints = "$Zdn = $_Zdn"; 1485 let DestructiveInstType = Destructive; 1486 let ElementSize = zprty.ElementSize; 1487} 1488 1489multiclass sve_fp_fcadd<string asm> { 1490 def _H : sve_fp_fcadd<0b01, asm, ZPR16>; 1491 def _S : sve_fp_fcadd<0b10, asm, ZPR32>; 1492 def _D : sve_fp_fcadd<0b11, asm, ZPR64>; 1493} 1494 1495//===----------------------------------------------------------------------===// 1496// SVE2 Floating Point Convert Group 1497//===----------------------------------------------------------------------===// 1498 1499class sve2_fp_convert_precision<bits<4> opc, string asm, 1500 ZPRRegOp zprty1, ZPRRegOp zprty2> 1501: I<(outs zprty1:$Zd), (ins zprty1:$_Zd, PPR3bAny:$Pg, zprty2:$Zn), 1502 asm, "\t$Zd, $Pg/m, $Zn", 1503 "", 1504 []>, Sched<[]> { 1505 bits<5> Zd; 1506 bits<5> Zn; 1507 bits<3> Pg; 1508 let Inst{31-24} = 0b01100100; 1509 let Inst{23-22} = opc{3-2}; 1510 let Inst{21-18} = 0b0010; 1511 let Inst{17-16} = opc{1-0}; 1512 let Inst{15-13} = 0b101; 1513 let Inst{12-10} = Pg; 1514 let Inst{9-5} = Zn; 1515 let Inst{4-0} = Zd; 1516 1517 let Constraints = "$Zd = $_Zd"; 1518} 1519 1520multiclass sve2_fp_convert_down_narrow<string asm> { 1521 def _StoH : sve2_fp_convert_precision<0b1000, asm, ZPR16, ZPR32>; 1522 def _DtoS : sve2_fp_convert_precision<0b1110, asm, ZPR32, ZPR64>; 1523} 1524 1525multiclass sve2_fp_convert_up_long<string asm> { 1526 def _HtoS : sve2_fp_convert_precision<0b1001, asm, ZPR32, ZPR16>; 1527 def _StoD : sve2_fp_convert_precision<0b1111, asm, ZPR64, ZPR32>; 1528} 1529 1530multiclass sve2_fp_convert_down_odd_rounding<string asm> { 1531 def _DtoS : sve2_fp_convert_precision<0b0010, asm, ZPR32, ZPR64>; 1532} 1533 1534//===----------------------------------------------------------------------===// 1535// SVE2 Floating Point Pairwise Group 1536//===----------------------------------------------------------------------===// 1537 1538class sve2_fp_pairwise_pred<bits<2> sz, bits<3> opc, string asm, 1539 ZPRRegOp zprty> 1540: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), 1541 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", 1542 "", 1543 []>, Sched<[]> { 1544 bits<3> Pg; 1545 bits<5> Zm; 1546 bits<5> Zdn; 1547 let Inst{31-24} = 0b01100100; 1548 let Inst{23-22} = sz; 1549 let Inst{21-19} = 0b010; 1550 let Inst{18-16} = opc; 1551 let Inst{15-13} = 0b100; 1552 let Inst{12-10} = Pg; 1553 let Inst{9-5} = Zm; 1554 let Inst{4-0} = Zdn; 1555 1556 let Constraints = "$Zdn = $_Zdn"; 1557 let DestructiveInstType = Destructive; 1558 let ElementSize = zprty.ElementSize; 1559} 1560 1561multiclass sve2_fp_pairwise_pred<bits<3> opc, string asm> { 1562 def _H : sve2_fp_pairwise_pred<0b01, opc, asm, ZPR16>; 1563 def _S : sve2_fp_pairwise_pred<0b10, opc, asm, ZPR32>; 1564 def _D : sve2_fp_pairwise_pred<0b11, opc, asm, ZPR64>; 1565} 1566 1567//===----------------------------------------------------------------------===// 1568// SVE2 Floating Point Widening Multiply-Add - Indexed Group 1569//===----------------------------------------------------------------------===// 1570 1571class sve2_fp_mla_long_by_indexed_elem<bits<2> opc, string asm> 1572: I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR3b16:$Zm, 1573 VectorIndexH:$iop), 1574 asm, "\t$Zda, $Zn, $Zm$iop", 1575 "", 1576 []>, Sched<[]> { 1577 bits<5> Zda; 1578 bits<5> Zn; 1579 bits<3> Zm; 1580 bits<3> iop; 1581 let Inst{31-21} = 0b01100100101; 1582 let Inst{20-19} = iop{2-1}; 1583 let Inst{18-16} = Zm; 1584 let Inst{15-14} = 0b01; 1585 let Inst{13} = opc{1}; 1586 let Inst{12} = 0b0; 1587 let Inst{11} = iop{0}; 1588 let Inst{10} = opc{0}; 1589 let Inst{9-5} = Zn; 1590 let Inst{4-0} = Zda; 1591 1592 let Constraints = "$Zda = $_Zda"; 1593 let DestructiveInstType = Destructive; 1594 let ElementSize = ElementSizeNone; 1595} 1596 1597//===----------------------------------------------------------------------===// 1598// SVE2 Floating Point Widening Multiply-Add Group 1599//===----------------------------------------------------------------------===// 1600 1601class sve2_fp_mla_long<bits<2> opc, string asm> 1602: I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR16:$Zm), 1603 asm, "\t$Zda, $Zn, $Zm", 1604 "", 1605 []>, Sched<[]> { 1606 bits<5> Zda; 1607 bits<5> Zn; 1608 bits<5> Zm; 1609 let Inst{31-21} = 0b01100100101; 1610 let Inst{20-16} = Zm; 1611 let Inst{15-14} = 0b10; 1612 let Inst{13} = opc{1}; 1613 let Inst{12-11} = 0b00; 1614 let Inst{10} = opc{0}; 1615 let Inst{9-5} = Zn; 1616 let Inst{4-0} = Zda; 1617 1618 let Constraints = "$Zda = $_Zda"; 1619 let DestructiveInstType = Destructive; 1620 let ElementSize = ElementSizeNone; 1621} 1622 1623//===----------------------------------------------------------------------===// 1624// SVE Stack Allocation Group 1625//===----------------------------------------------------------------------===// 1626 1627class sve_int_arith_vl<bit opc, string asm> 1628: I<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, simm6_32b:$imm6), 1629 asm, "\t$Rd, $Rn, $imm6", 1630 "", 1631 []>, Sched<[]> { 1632 bits<5> Rd; 1633 bits<5> Rn; 1634 bits<6> imm6; 1635 let Inst{31-23} = 0b000001000; 1636 let Inst{22} = opc; 1637 let Inst{21} = 0b1; 1638 let Inst{20-16} = Rn; 1639 let Inst{15-11} = 0b01010; 1640 let Inst{10-5} = imm6; 1641 let Inst{4-0} = Rd; 1642} 1643 1644class sve_int_read_vl_a<bit op, bits<5> opc2, string asm> 1645: I<(outs GPR64:$Rd), (ins simm6_32b:$imm6), 1646 asm, "\t$Rd, $imm6", 1647 "", 1648 []>, Sched<[]> { 1649 bits<5> Rd; 1650 bits<6> imm6; 1651 let Inst{31-23} = 0b000001001; 1652 let Inst{22} = op; 1653 let Inst{21} = 0b1; 1654 let Inst{20-16} = opc2{4-0}; 1655 let Inst{15-11} = 0b01010; 1656 let Inst{10-5} = imm6; 1657 let Inst{4-0} = Rd; 1658} 1659 1660//===----------------------------------------------------------------------===// 1661// SVE Permute - In Lane Group 1662//===----------------------------------------------------------------------===// 1663 1664class sve_int_perm_bin_perm_zz<bits<3> opc, bits<2> sz8_64, string asm, 1665 ZPRRegOp zprty> 1666: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), 1667 asm, "\t$Zd, $Zn, $Zm", 1668 "", 1669 []>, Sched<[]> { 1670 bits<5> Zd; 1671 bits<5> Zm; 1672 bits<5> Zn; 1673 let Inst{31-24} = 0b00000101; 1674 let Inst{23-22} = sz8_64; 1675 let Inst{21} = 0b1; 1676 let Inst{20-16} = Zm; 1677 let Inst{15-13} = 0b011; 1678 let Inst{12-10} = opc; 1679 let Inst{9-5} = Zn; 1680 let Inst{4-0} = Zd; 1681} 1682 1683multiclass sve_int_perm_bin_perm_zz<bits<3> opc, string asm> { 1684 def _B : sve_int_perm_bin_perm_zz<opc, 0b00, asm, ZPR8>; 1685 def _H : sve_int_perm_bin_perm_zz<opc, 0b01, asm, ZPR16>; 1686 def _S : sve_int_perm_bin_perm_zz<opc, 0b10, asm, ZPR32>; 1687 def _D : sve_int_perm_bin_perm_zz<opc, 0b11, asm, ZPR64>; 1688} 1689 1690//===----------------------------------------------------------------------===// 1691// SVE Floating Point Unary Operations Group 1692//===----------------------------------------------------------------------===// 1693 1694class sve_fp_2op_p_zd<bits<7> opc, string asm, RegisterOperand i_zprtype, 1695 RegisterOperand o_zprtype, ElementSizeEnum size> 1696: I<(outs o_zprtype:$Zd), (ins i_zprtype:$_Zd, PPR3bAny:$Pg, i_zprtype:$Zn), 1697 asm, "\t$Zd, $Pg/m, $Zn", 1698 "", 1699 []>, Sched<[]> { 1700 bits<3> Pg; 1701 bits<5> Zd; 1702 bits<5> Zn; 1703 let Inst{31-24} = 0b01100101; 1704 let Inst{23-22} = opc{6-5}; 1705 let Inst{21} = 0b0; 1706 let Inst{20-16} = opc{4-0}; 1707 let Inst{15-13} = 0b101; 1708 let Inst{12-10} = Pg; 1709 let Inst{9-5} = Zn; 1710 let Inst{4-0} = Zd; 1711 1712 let Constraints = "$Zd = $_Zd"; 1713 let DestructiveInstType = Destructive; 1714 let ElementSize = size; 1715} 1716 1717multiclass sve_fp_2op_p_zd_HSD<bits<5> opc, string asm> { 1718 def _H : sve_fp_2op_p_zd<{ 0b01, opc }, asm, ZPR16, ZPR16, ElementSizeH>; 1719 def _S : sve_fp_2op_p_zd<{ 0b10, opc }, asm, ZPR32, ZPR32, ElementSizeS>; 1720 def _D : sve_fp_2op_p_zd<{ 0b11, opc }, asm, ZPR64, ZPR64, ElementSizeD>; 1721} 1722 1723multiclass sve2_fp_flogb<string asm> { 1724 def _H : sve_fp_2op_p_zd<0b0011010, asm, ZPR16, ZPR16, ElementSizeH>; 1725 def _S : sve_fp_2op_p_zd<0b0011100, asm, ZPR32, ZPR32, ElementSizeS>; 1726 def _D : sve_fp_2op_p_zd<0b0011110, asm, ZPR64, ZPR64, ElementSizeD>; 1727} 1728 1729//===----------------------------------------------------------------------===// 1730// SVE Floating Point Unary Operations - Unpredicated Group 1731//===----------------------------------------------------------------------===// 1732 1733class sve_fp_2op_u_zd<bits<2> sz, bits<3> opc, string asm, 1734 ZPRRegOp zprty> 1735: I<(outs zprty:$Zd), (ins zprty:$Zn), 1736 asm, "\t$Zd, $Zn", 1737 "", 1738 []>, Sched<[]> { 1739 bits<5> Zd; 1740 bits<5> Zn; 1741 let Inst{31-24} = 0b01100101; 1742 let Inst{23-22} = sz; 1743 let Inst{21-19} = 0b001; 1744 let Inst{18-16} = opc; 1745 let Inst{15-10} = 0b001100; 1746 let Inst{9-5} = Zn; 1747 let Inst{4-0} = Zd; 1748} 1749 1750multiclass sve_fp_2op_u_zd<bits<3> opc, string asm> { 1751 def _H : sve_fp_2op_u_zd<0b01, opc, asm, ZPR16>; 1752 def _S : sve_fp_2op_u_zd<0b10, opc, asm, ZPR32>; 1753 def _D : sve_fp_2op_u_zd<0b11, opc, asm, ZPR64>; 1754} 1755 1756//===----------------------------------------------------------------------===// 1757// SVE Integer Arithmetic - Binary Predicated Group 1758//===----------------------------------------------------------------------===// 1759 1760class sve_int_bin_pred_arit_log<bits<2> sz8_64, bits<2> fmt, bits<3> opc, 1761 string asm, ZPRRegOp zprty> 1762: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), 1763 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> { 1764 bits<3> Pg; 1765 bits<5> Zdn; 1766 bits<5> Zm; 1767 let Inst{31-24} = 0b00000100; 1768 let Inst{23-22} = sz8_64; 1769 let Inst{21} = 0b0; 1770 let Inst{20-19} = fmt; 1771 let Inst{18-16} = opc; 1772 let Inst{15-13} = 0b000; 1773 let Inst{12-10} = Pg; 1774 let Inst{9-5} = Zm; 1775 let Inst{4-0} = Zdn; 1776 1777 let Constraints = "$Zdn = $_Zdn"; 1778 let DestructiveInstType = Destructive; 1779 let ElementSize = zprty.ElementSize; 1780} 1781 1782multiclass sve_int_bin_pred_log<bits<3> opc, string asm> { 1783 def _B : sve_int_bin_pred_arit_log<0b00, 0b11, opc, asm, ZPR8>; 1784 def _H : sve_int_bin_pred_arit_log<0b01, 0b11, opc, asm, ZPR16>; 1785 def _S : sve_int_bin_pred_arit_log<0b10, 0b11, opc, asm, ZPR32>; 1786 def _D : sve_int_bin_pred_arit_log<0b11, 0b11, opc, asm, ZPR64>; 1787} 1788 1789multiclass sve_int_bin_pred_arit_0<bits<3> opc, string asm> { 1790 def _B : sve_int_bin_pred_arit_log<0b00, 0b00, opc, asm, ZPR8>; 1791 def _H : sve_int_bin_pred_arit_log<0b01, 0b00, opc, asm, ZPR16>; 1792 def _S : sve_int_bin_pred_arit_log<0b10, 0b00, opc, asm, ZPR32>; 1793 def _D : sve_int_bin_pred_arit_log<0b11, 0b00, opc, asm, ZPR64>; 1794} 1795 1796multiclass sve_int_bin_pred_arit_1<bits<3> opc, string asm> { 1797 def _B : sve_int_bin_pred_arit_log<0b00, 0b01, opc, asm, ZPR8>; 1798 def _H : sve_int_bin_pred_arit_log<0b01, 0b01, opc, asm, ZPR16>; 1799 def _S : sve_int_bin_pred_arit_log<0b10, 0b01, opc, asm, ZPR32>; 1800 def _D : sve_int_bin_pred_arit_log<0b11, 0b01, opc, asm, ZPR64>; 1801} 1802 1803multiclass sve_int_bin_pred_arit_2<bits<3> opc, string asm> { 1804 def _B : sve_int_bin_pred_arit_log<0b00, 0b10, opc, asm, ZPR8>; 1805 def _H : sve_int_bin_pred_arit_log<0b01, 0b10, opc, asm, ZPR16>; 1806 def _S : sve_int_bin_pred_arit_log<0b10, 0b10, opc, asm, ZPR32>; 1807 def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, ZPR64>; 1808} 1809 1810// Special case for divides which are not defined for 8b/16b elements. 1811multiclass sve_int_bin_pred_arit_2_div<bits<3> opc, string asm> { 1812 def _S : sve_int_bin_pred_arit_log<0b10, 0b10, opc, asm, ZPR32>; 1813 def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, ZPR64>; 1814} 1815 1816//===----------------------------------------------------------------------===// 1817// SVE Integer Multiply-Add Group 1818//===----------------------------------------------------------------------===// 1819 1820class sve_int_mladdsub_vvv_pred<bits<2> sz8_64, bits<1> opc, string asm, 1821 ZPRRegOp zprty> 1822: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za), 1823 asm, "\t$Zdn, $Pg/m, $Zm, $Za", 1824 "", 1825 []>, Sched<[]> { 1826 bits<3> Pg; 1827 bits<5> Zdn; 1828 bits<5> Za; 1829 bits<5> Zm; 1830 let Inst{31-24} = 0b00000100; 1831 let Inst{23-22} = sz8_64; 1832 let Inst{21} = 0b0; 1833 let Inst{20-16} = Zm; 1834 let Inst{15-14} = 0b11; 1835 let Inst{13} = opc; 1836 let Inst{12-10} = Pg; 1837 let Inst{9-5} = Za; 1838 let Inst{4-0} = Zdn; 1839 1840 let Constraints = "$Zdn = $_Zdn"; 1841 let DestructiveInstType = Destructive; 1842 let ElementSize = zprty.ElementSize; 1843} 1844 1845multiclass sve_int_mladdsub_vvv_pred<bits<1> opc, string asm> { 1846 def _B : sve_int_mladdsub_vvv_pred<0b00, opc, asm, ZPR8>; 1847 def _H : sve_int_mladdsub_vvv_pred<0b01, opc, asm, ZPR16>; 1848 def _S : sve_int_mladdsub_vvv_pred<0b10, opc, asm, ZPR32>; 1849 def _D : sve_int_mladdsub_vvv_pred<0b11, opc, asm, ZPR64>; 1850} 1851 1852class sve_int_mlas_vvv_pred<bits<2> sz8_64, bits<1> opc, string asm, 1853 ZPRRegOp zprty> 1854: I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm), 1855 asm, "\t$Zda, $Pg/m, $Zn, $Zm", 1856 "", 1857 []>, Sched<[]> { 1858 bits<3> Pg; 1859 bits<5> Zda; 1860 bits<5> Zm; 1861 bits<5> Zn; 1862 let Inst{31-24} = 0b00000100; 1863 let Inst{23-22} = sz8_64; 1864 let Inst{21} = 0b0; 1865 let Inst{20-16} = Zm; 1866 let Inst{15-14} = 0b01; 1867 let Inst{13} = opc; 1868 let Inst{12-10} = Pg; 1869 let Inst{9-5} = Zn; 1870 let Inst{4-0} = Zda; 1871 1872 let Constraints = "$Zda = $_Zda"; 1873 let DestructiveInstType = Destructive; 1874 let ElementSize = zprty.ElementSize; 1875} 1876 1877multiclass sve_int_mlas_vvv_pred<bits<1> opc, string asm> { 1878 def _B : sve_int_mlas_vvv_pred<0b00, opc, asm, ZPR8>; 1879 def _H : sve_int_mlas_vvv_pred<0b01, opc, asm, ZPR16>; 1880 def _S : sve_int_mlas_vvv_pred<0b10, opc, asm, ZPR32>; 1881 def _D : sve_int_mlas_vvv_pred<0b11, opc, asm, ZPR64>; 1882} 1883 1884//===----------------------------------------------------------------------===// 1885// SVE2 Integer Multiply-Add - Unpredicated Group 1886//===----------------------------------------------------------------------===// 1887 1888class sve2_int_mla<bits<2> sz, bits<5> opc, string asm, 1889 ZPRRegOp zprty1, ZPRRegOp zprty2> 1890: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm), 1891 asm, "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> { 1892 bits<5> Zda; 1893 bits<5> Zn; 1894 bits<5> Zm; 1895 let Inst{31-24} = 0b01000100; 1896 let Inst{23-22} = sz; 1897 let Inst{21} = 0b0; 1898 let Inst{20-16} = Zm; 1899 let Inst{15} = 0b0; 1900 let Inst{14-10} = opc; 1901 let Inst{9-5} = Zn; 1902 let Inst{4-0} = Zda; 1903 1904 let Constraints = "$Zda = $_Zda"; 1905 let DestructiveInstType = Destructive; 1906 let ElementSize = ElementSizeNone; 1907} 1908 1909multiclass sve2_int_mla<bit S, string asm> { 1910 def _B : sve2_int_mla<0b00, { 0b1110, S }, asm, ZPR8, ZPR8>; 1911 def _H : sve2_int_mla<0b01, { 0b1110, S }, asm, ZPR16, ZPR16>; 1912 def _S : sve2_int_mla<0b10, { 0b1110, S }, asm, ZPR32, ZPR32>; 1913 def _D : sve2_int_mla<0b11, { 0b1110, S }, asm, ZPR64, ZPR64>; 1914} 1915 1916multiclass sve2_int_mla_long<bits<5> opc, string asm> { 1917 def _H : sve2_int_mla<0b01, opc, asm, ZPR16, ZPR8>; 1918 def _S : sve2_int_mla<0b10, opc, asm, ZPR32, ZPR16>; 1919 def _D : sve2_int_mla<0b11, opc, asm, ZPR64, ZPR32>; 1920} 1921 1922//===----------------------------------------------------------------------===// 1923// SVE2 Integer Multiply-Add - Indexed Group 1924//===----------------------------------------------------------------------===// 1925 1926class sve2_int_mla_by_indexed_elem<bits<2> sz, bits<6> opc, string asm, 1927 ZPRRegOp zprty1, ZPRRegOp zprty2, 1928 ZPRRegOp zprty3, Operand itype> 1929: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty3:$Zm, itype:$iop), 1930 asm, "\t$Zda, $Zn, $Zm$iop", "", []>, Sched<[]> { 1931 bits<5> Zda; 1932 bits<5> Zn; 1933 let Inst{31-24} = 0b01000100; 1934 let Inst{23-22} = sz; 1935 let Inst{21} = 0b1; 1936 let Inst{15-10} = opc; 1937 let Inst{9-5} = Zn; 1938 let Inst{4-0} = Zda; 1939 1940 let Constraints = "$Zda = $_Zda"; 1941 let DestructiveInstType = Destructive; 1942 let ElementSize = ElementSizeNone; 1943} 1944 1945multiclass sve2_int_mla_by_indexed_elem<bits<2> opc, bit S, string asm> { 1946 def _H : sve2_int_mla_by_indexed_elem<{0, ?}, { 0b000, opc, S }, asm, ZPR16, ZPR16, ZPR3b16, VectorIndexH> { 1947 bits<3> Zm; 1948 bits<3> iop; 1949 let Inst{22} = iop{2}; 1950 let Inst{20-19} = iop{1-0}; 1951 let Inst{18-16} = Zm; 1952 } 1953 def _S : sve2_int_mla_by_indexed_elem<0b10, { 0b000, opc, S }, asm, ZPR32, ZPR32, ZPR3b32, VectorIndexS> { 1954 bits<3> Zm; 1955 bits<2> iop; 1956 let Inst{20-19} = iop; 1957 let Inst{18-16} = Zm; 1958 } 1959 def _D : sve2_int_mla_by_indexed_elem<0b11, { 0b000, opc, S }, asm, ZPR64, ZPR64, ZPR4b64, VectorIndexD> { 1960 bits<4> Zm; 1961 bit iop; 1962 let Inst{20} = iop; 1963 let Inst{19-16} = Zm; 1964 } 1965} 1966 1967//===----------------------------------------------------------------------===// 1968// SVE2 Integer Multiply-Add Long - Indexed Group 1969//===----------------------------------------------------------------------===// 1970 1971multiclass sve2_int_mla_long_by_indexed_elem<bits<4> opc, string asm> { 1972 def _S : sve2_int_mla_by_indexed_elem<0b10, { opc{3}, 0b0, opc{2-1}, ?, opc{0} }, 1973 asm, ZPR32, ZPR16, ZPR3b16, VectorIndexH> { 1974 bits<3> Zm; 1975 bits<3> iop; 1976 let Inst{20-19} = iop{2-1}; 1977 let Inst{18-16} = Zm; 1978 let Inst{11} = iop{0}; 1979 } 1980 def _D : sve2_int_mla_by_indexed_elem<0b11, { opc{3}, 0b0, opc{2-1}, ?, opc{0} }, 1981 asm, ZPR64, ZPR32, ZPR4b32, VectorIndexS> { 1982 bits<4> Zm; 1983 bits<2> iop; 1984 let Inst{20} = iop{1}; 1985 let Inst{19-16} = Zm; 1986 let Inst{11} = iop{0}; 1987 } 1988} 1989 1990//===----------------------------------------------------------------------===// 1991// SVE Integer Dot Product Group 1992//===----------------------------------------------------------------------===// 1993 1994class sve_intx_dot<bit sz, bit U, string asm, ZPRRegOp zprty1, 1995 ZPRRegOp zprty2> 1996: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm), asm, 1997 "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> { 1998 bits<5> Zda; 1999 bits<5> Zn; 2000 bits<5> Zm; 2001 let Inst{31-23} = 0b010001001; 2002 let Inst{22} = sz; 2003 let Inst{21} = 0; 2004 let Inst{20-16} = Zm; 2005 let Inst{15-11} = 0; 2006 let Inst{10} = U; 2007 let Inst{9-5} = Zn; 2008 let Inst{4-0} = Zda; 2009 2010 let Constraints = "$Zda = $_Zda"; 2011 let DestructiveInstType = Destructive; 2012 let ElementSize = zprty1.ElementSize; 2013} 2014 2015multiclass sve_intx_dot<bit opc, string asm> { 2016 def _S : sve_intx_dot<0b0, opc, asm, ZPR32, ZPR8>; 2017 def _D : sve_intx_dot<0b1, opc, asm, ZPR64, ZPR16>; 2018} 2019 2020//===----------------------------------------------------------------------===// 2021// SVE Integer Dot Product Group - Indexed Group 2022//===----------------------------------------------------------------------===// 2023 2024class sve_intx_dot_by_indexed_elem<bit sz, bit U, string asm, 2025 ZPRRegOp zprty1, ZPRRegOp zprty2, 2026 ZPRRegOp zprty3, Operand itype> 2027: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty3:$Zm, itype:$iop), 2028 asm, "\t$Zda, $Zn, $Zm$iop", 2029 "", []>, Sched<[]> { 2030 bits<5> Zda; 2031 bits<5> Zn; 2032 let Inst{31-23} = 0b010001001; 2033 let Inst{22} = sz; 2034 let Inst{21} = 0b1; 2035 let Inst{15-11} = 0; 2036 let Inst{10} = U; 2037 let Inst{9-5} = Zn; 2038 let Inst{4-0} = Zda; 2039 2040 let Constraints = "$Zda = $_Zda"; 2041 let DestructiveInstType = Destructive; 2042 let ElementSize = ElementSizeNone; 2043} 2044 2045multiclass sve_intx_dot_by_indexed_elem<bit opc, string asm> { 2046 def _S : sve_intx_dot_by_indexed_elem<0b0, opc, asm, ZPR32, ZPR8, ZPR3b8, VectorIndexS> { 2047 bits<2> iop; 2048 bits<3> Zm; 2049 let Inst{20-19} = iop; 2050 let Inst{18-16} = Zm; 2051 } 2052 def _D : sve_intx_dot_by_indexed_elem<0b1, opc, asm, ZPR64, ZPR16, ZPR4b16, VectorIndexD> { 2053 bits<1> iop; 2054 bits<4> Zm; 2055 let Inst{20} = iop; 2056 let Inst{19-16} = Zm; 2057 } 2058} 2059 2060//===----------------------------------------------------------------------===// 2061// SVE2 Complex Integer Dot Product Group 2062//===----------------------------------------------------------------------===// 2063 2064class sve2_complex_int_arith<bits<2> sz, bits<4> opc, string asm, 2065 ZPRRegOp zprty1, ZPRRegOp zprty2> 2066: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm, 2067 complexrotateop:$rot), 2068 asm, "\t$Zda, $Zn, $Zm, $rot", "", []>, Sched<[]> { 2069 bits<5> Zda; 2070 bits<5> Zn; 2071 bits<5> Zm; 2072 bits<2> rot; 2073 let Inst{31-24} = 0b01000100; 2074 let Inst{23-22} = sz; 2075 let Inst{21} = 0b0; 2076 let Inst{20-16} = Zm; 2077 let Inst{15-12} = opc; 2078 let Inst{11-10} = rot; 2079 let Inst{9-5} = Zn; 2080 let Inst{4-0} = Zda; 2081 2082 let Constraints = "$Zda = $_Zda"; 2083 let DestructiveInstType = Destructive; 2084 let ElementSize = ElementSizeNone; 2085} 2086 2087multiclass sve2_cintx_dot<string asm> { 2088 def _S : sve2_complex_int_arith<0b10, 0b0001, asm, ZPR32, ZPR8>; 2089 def _D : sve2_complex_int_arith<0b11, 0b0001, asm, ZPR64, ZPR16>; 2090} 2091 2092//===----------------------------------------------------------------------===// 2093// SVE2 Complex Multiply-Add Group 2094//===----------------------------------------------------------------------===// 2095 2096multiclass sve2_int_cmla<bit opc, string asm> { 2097 def _B : sve2_complex_int_arith<0b00, { 0b001, opc }, asm, ZPR8, ZPR8>; 2098 def _H : sve2_complex_int_arith<0b01, { 0b001, opc }, asm, ZPR16, ZPR16>; 2099 def _S : sve2_complex_int_arith<0b10, { 0b001, opc }, asm, ZPR32, ZPR32>; 2100 def _D : sve2_complex_int_arith<0b11, { 0b001, opc }, asm, ZPR64, ZPR64>; 2101} 2102 2103//===----------------------------------------------------------------------===// 2104// SVE2 Complex Integer Dot Product - Indexed Group 2105//===----------------------------------------------------------------------===// 2106 2107class sve2_complex_int_arith_indexed<bits<2> sz, bits<4> opc, string asm, 2108 ZPRRegOp zprty1, ZPRRegOp zprty2, 2109 ZPRRegOp zprty3, Operand itype> 2110: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty3:$Zm, itype:$iop, 2111 complexrotateop:$rot), 2112 asm, "\t$Zda, $Zn, $Zm$iop, $rot", "", []>, Sched<[]> { 2113 bits<5> Zda; 2114 bits<5> Zn; 2115 bits<2> rot; 2116 let Inst{31-24} = 0b01000100; 2117 let Inst{23-22} = sz; 2118 let Inst{21} = 0b1; 2119 let Inst{15-12} = opc; 2120 let Inst{11-10} = rot; 2121 let Inst{9-5} = Zn; 2122 let Inst{4-0} = Zda; 2123 2124 let Constraints = "$Zda = $_Zda"; 2125 let DestructiveInstType = Destructive; 2126 let ElementSize = ElementSizeNone; 2127} 2128 2129multiclass sve2_cintx_dot_by_indexed_elem<string asm> { 2130 def _S : sve2_complex_int_arith_indexed<0b10, 0b0100, asm, ZPR32, ZPR8, ZPR3b8, VectorIndexS> { 2131 bits<2> iop; 2132 bits<3> Zm; 2133 let Inst{20-19} = iop; 2134 let Inst{18-16} = Zm; 2135 } 2136 def _D : sve2_complex_int_arith_indexed<0b11, 0b0100, asm, ZPR64, ZPR16, ZPR4b16, VectorIndexD> { 2137 bit iop; 2138 bits<4> Zm; 2139 let Inst{20} = iop; 2140 let Inst{19-16} = Zm; 2141 } 2142} 2143 2144//===----------------------------------------------------------------------===// 2145// SVE2 Complex Multiply-Add - Indexed Group 2146//===----------------------------------------------------------------------===// 2147 2148multiclass sve2_cmla_by_indexed_elem<bit opc, string asm> { 2149 def _H : sve2_complex_int_arith_indexed<0b10, { 0b011, opc }, asm, ZPR16, ZPR16, ZPR3b16, VectorIndexS> { 2150 bits<2> iop; 2151 bits<3> Zm; 2152 let Inst{20-19} = iop; 2153 let Inst{18-16} = Zm; 2154 } 2155 def _S : sve2_complex_int_arith_indexed<0b11, { 0b011, opc }, asm, ZPR32, ZPR32, ZPR4b32, VectorIndexD> { 2156 bit iop; 2157 bits<4> Zm; 2158 let Inst{20} = iop; 2159 let Inst{19-16} = Zm; 2160 } 2161} 2162 2163//===----------------------------------------------------------------------===// 2164// SVE2 Integer Multiply - Unpredicated Group 2165//===----------------------------------------------------------------------===// 2166 2167class sve2_int_mul<bits<2> sz, bits<3> opc, string asm, ZPRRegOp zprty> 2168: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), 2169 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> { 2170 bits<5> Zd; 2171 bits<5> Zm; 2172 bits<5> Zn; 2173 let Inst{31-24} = 0b00000100; 2174 let Inst{23-22} = sz; 2175 let Inst{21} = 0b1; 2176 let Inst{20-16} = Zm; 2177 let Inst{15-13} = 0b011; 2178 let Inst{12-10} = opc; 2179 let Inst{9-5} = Zn; 2180 let Inst{4-0} = Zd; 2181} 2182 2183multiclass sve2_int_mul<bits<3> opc, string asm> { 2184 def _B : sve2_int_mul<0b00, opc, asm, ZPR8>; 2185 def _H : sve2_int_mul<0b01, opc, asm, ZPR16>; 2186 def _S : sve2_int_mul<0b10, opc, asm, ZPR32>; 2187 def _D : sve2_int_mul<0b11, opc, asm, ZPR64>; 2188} 2189 2190//===----------------------------------------------------------------------===// 2191// SVE2 Integer Multiply - Indexed Group 2192//===----------------------------------------------------------------------===// 2193 2194class sve2_int_mul_by_indexed_elem<bits<2> sz, bits<4> opc, string asm, 2195 ZPRRegOp zprty1, ZPRRegOp zprty2, 2196 ZPRRegOp zprty3, Operand itype> 2197: I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty3:$Zm, itype:$iop), 2198 asm, "\t$Zd, $Zn, $Zm$iop", "", []>, Sched<[]> { 2199 bits<5> Zd; 2200 bits<5> Zn; 2201 let Inst{31-24} = 0b01000100; 2202 let Inst{23-22} = sz; 2203 let Inst{21} = 0b1; 2204 let Inst{15-14} = 0b11; 2205 let Inst{13-10} = opc; 2206 let Inst{9-5} = Zn; 2207 let Inst{4-0} = Zd; 2208} 2209 2210multiclass sve2_int_mul_by_indexed_elem<bits<4> opc, string asm> { 2211 def _H : sve2_int_mul_by_indexed_elem<{0, ?}, opc, asm, ZPR16, ZPR16, ZPR3b16, VectorIndexH> { 2212 bits<3> Zm; 2213 bits<3> iop; 2214 let Inst{22} = iop{2}; 2215 let Inst{20-19} = iop{1-0}; 2216 let Inst{18-16} = Zm; 2217 } 2218 def _S : sve2_int_mul_by_indexed_elem<0b10, opc, asm, ZPR32, ZPR32, ZPR3b32, VectorIndexS> { 2219 bits<3> Zm; 2220 bits<2> iop; 2221 let Inst{20-19} = iop; 2222 let Inst{18-16} = Zm; 2223 } 2224 def _D : sve2_int_mul_by_indexed_elem<0b11, opc, asm, ZPR64, ZPR64, ZPR4b64, VectorIndexD> { 2225 bits<4> Zm; 2226 bit iop; 2227 let Inst{20} = iop; 2228 let Inst{19-16} = Zm; 2229 } 2230} 2231 2232multiclass sve2_int_mul_long_by_indexed_elem<bits<3> opc, string asm> { 2233 def _S : sve2_int_mul_by_indexed_elem<0b10, { opc{2-1}, ?, opc{0} }, asm, 2234 ZPR32, ZPR16, ZPR3b16, VectorIndexH> { 2235 bits<3> Zm; 2236 bits<3> iop; 2237 let Inst{20-19} = iop{2-1}; 2238 let Inst{18-16} = Zm; 2239 let Inst{11} = iop{0}; 2240 } 2241 def _D : sve2_int_mul_by_indexed_elem<0b11, { opc{2-1}, ?, opc{0} }, asm, 2242 ZPR64, ZPR32, ZPR4b32, VectorIndexS> { 2243 bits<4> Zm; 2244 bits<2> iop; 2245 let Inst{20} = iop{1}; 2246 let Inst{19-16} = Zm; 2247 let Inst{11} = iop{0}; 2248 } 2249} 2250 2251//===----------------------------------------------------------------------===// 2252// SVE2 Integer - Predicated Group 2253//===----------------------------------------------------------------------===// 2254 2255class sve2_int_arith_pred<bits<2> sz, bits<6> opc, string asm, 2256 ZPRRegOp zprty> 2257: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), 2258 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> { 2259 bits<3> Pg; 2260 bits<5> Zm; 2261 bits<5> Zdn; 2262 let Inst{31-24} = 0b01000100; 2263 let Inst{23-22} = sz; 2264 let Inst{21} = 0b0; 2265 let Inst{20-16} = opc{5-1}; 2266 let Inst{15-14} = 0b10; 2267 let Inst{13} = opc{0}; 2268 let Inst{12-10} = Pg; 2269 let Inst{9-5} = Zm; 2270 let Inst{4-0} = Zdn; 2271 2272 let Constraints = "$Zdn = $_Zdn"; 2273 let DestructiveInstType = Destructive; 2274 let ElementSize = zprty.ElementSize; 2275} 2276 2277multiclass sve2_int_arith_pred<bits<6> opc, string asm> { 2278 def _B : sve2_int_arith_pred<0b00, opc, asm, ZPR8>; 2279 def _H : sve2_int_arith_pred<0b01, opc, asm, ZPR16>; 2280 def _S : sve2_int_arith_pred<0b10, opc, asm, ZPR32>; 2281 def _D : sve2_int_arith_pred<0b11, opc, asm, ZPR64>; 2282} 2283 2284class sve2_int_sadd_long_accum_pairwise<bits<2> sz, bit U, string asm, 2285 ZPRRegOp zprty1, ZPRRegOp zprty2> 2286: I<(outs zprty1:$Zda), (ins PPR3bAny:$Pg, zprty1:$_Zda, zprty2:$Zn), 2287 asm, "\t$Zda, $Pg/m, $Zn", "", []>, Sched<[]> { 2288 bits<3> Pg; 2289 bits<5> Zn; 2290 bits<5> Zda; 2291 let Inst{31-24} = 0b01000100; 2292 let Inst{23-22} = sz; 2293 let Inst{21-17} = 0b00010; 2294 let Inst{16} = U; 2295 let Inst{15-13} = 0b101; 2296 let Inst{12-10} = Pg; 2297 let Inst{9-5} = Zn; 2298 let Inst{4-0} = Zda; 2299 2300 let Constraints = "$Zda = $_Zda"; 2301 let DestructiveInstType = Destructive; 2302 let ElementSize = zprty1.ElementSize; 2303} 2304 2305multiclass sve2_int_sadd_long_accum_pairwise<bit U, string asm> { 2306 def _H : sve2_int_sadd_long_accum_pairwise<0b01, U, asm, ZPR16, ZPR8>; 2307 def _S : sve2_int_sadd_long_accum_pairwise<0b10, U, asm, ZPR32, ZPR16>; 2308 def _D : sve2_int_sadd_long_accum_pairwise<0b11, U, asm, ZPR64, ZPR32>; 2309} 2310 2311class sve2_int_un_pred_arit<bits<2> sz, bit Q, bits<2> opc, 2312 string asm, ZPRRegOp zprty> 2313: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn), 2314 asm, "\t$Zd, $Pg/m, $Zn", 2315 "", 2316 []>, Sched<[]> { 2317 bits<3> Pg; 2318 bits<5> Zd; 2319 bits<5> Zn; 2320 let Inst{31-24} = 0b01000100; 2321 let Inst{23-22} = sz; 2322 let Inst{21-20} = 0b00; 2323 let Inst{19} = Q; 2324 let Inst{18} = 0b0; 2325 let Inst{17-16} = opc; 2326 let Inst{15-13} = 0b101; 2327 let Inst{12-10} = Pg; 2328 let Inst{9-5} = Zn; 2329 let Inst{4-0} = Zd; 2330 2331 let Constraints = "$Zd = $_Zd"; 2332 let DestructiveInstType = Destructive; 2333 let ElementSize = zprty.ElementSize; 2334} 2335 2336multiclass sve2_int_un_pred_arit_s<bits<3> opc, string asm> { 2337 def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>; 2338} 2339 2340multiclass sve2_int_un_pred_arit<bits<3> opc, string asm> { 2341 def _B : sve2_int_un_pred_arit<0b00, opc{2}, opc{1-0}, asm, ZPR8>; 2342 def _H : sve2_int_un_pred_arit<0b01, opc{2}, opc{1-0}, asm, ZPR16>; 2343 def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>; 2344 def _D : sve2_int_un_pred_arit<0b11, opc{2}, opc{1-0}, asm, ZPR64>; 2345} 2346 2347//===----------------------------------------------------------------------===// 2348// SVE2 Widening Integer Arithmetic Group 2349//===----------------------------------------------------------------------===// 2350 2351class sve2_wide_int_arith<bits<2> sz, bits<5> opc, string asm, 2352 ZPRRegOp zprty1, ZPRRegOp zprty2, ZPRRegOp zprty3> 2353: I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty3:$Zm), 2354 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> { 2355 bits<5> Zd; 2356 bits<5> Zn; 2357 bits<5> Zm; 2358 let Inst{31-24} = 0b01000101; 2359 let Inst{23-22} = sz; 2360 let Inst{21} = 0b0; 2361 let Inst{20-16} = Zm; 2362 let Inst{15} = 0b0; 2363 let Inst{14-10} = opc; 2364 let Inst{9-5} = Zn; 2365 let Inst{4-0} = Zd; 2366} 2367 2368multiclass sve2_wide_int_arith_long<bits<5> opc, string asm> { 2369 def _H : sve2_wide_int_arith<0b01, opc, asm, ZPR16, ZPR8, ZPR8>; 2370 def _S : sve2_wide_int_arith<0b10, opc, asm, ZPR32, ZPR16, ZPR16>; 2371 def _D : sve2_wide_int_arith<0b11, opc, asm, ZPR64, ZPR32, ZPR32>; 2372} 2373 2374multiclass sve2_wide_int_arith_wide<bits<3> opc, string asm> { 2375 def _H : sve2_wide_int_arith<0b01, { 0b10, opc }, asm, ZPR16, ZPR16, ZPR8>; 2376 def _S : sve2_wide_int_arith<0b10, { 0b10, opc }, asm, ZPR32, ZPR32, ZPR16>; 2377 def _D : sve2_wide_int_arith<0b11, { 0b10, opc }, asm, ZPR64, ZPR64, ZPR32>; 2378} 2379 2380multiclass sve2_pmul_long<bits<1> opc, string asm> { 2381 def _H : sve2_wide_int_arith<0b01, {0b1101, opc}, asm, ZPR16, ZPR8, ZPR8>; 2382 def _D : sve2_wide_int_arith<0b11, {0b1101, opc}, asm, ZPR64, ZPR32, ZPR32>; 2383} 2384 2385//===----------------------------------------------------------------------===// 2386// SVE2 Misc Group 2387//===----------------------------------------------------------------------===// 2388 2389class sve2_misc<bits<2> sz, bits<4> opc, string asm, 2390 ZPRRegOp zprty1, ZPRRegOp zprty2> 2391: I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty2:$Zm), 2392 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> { 2393 bits<5> Zd; 2394 bits<5> Zn; 2395 bits<5> Zm; 2396 let Inst{31-24} = 0b01000101; 2397 let Inst{23-22} = sz; 2398 let Inst{21} = 0b0; 2399 let Inst{20-16} = Zm; 2400 let Inst{15-14} = 0b10; 2401 let Inst{13-10} = opc; 2402 let Inst{9-5} = Zn; 2403 let Inst{4-0} = Zd; 2404} 2405 2406multiclass sve2_misc_bitwise<bits<4> opc, string asm> { 2407 def _B : sve2_misc<0b00, opc, asm, ZPR8, ZPR8>; 2408 def _H : sve2_misc<0b01, opc, asm, ZPR16, ZPR16>; 2409 def _S : sve2_misc<0b10, opc, asm, ZPR32, ZPR32>; 2410 def _D : sve2_misc<0b11, opc, asm, ZPR64, ZPR64>; 2411} 2412 2413multiclass sve2_misc_int_addsub_long_interleaved<bits<2> opc, string asm> { 2414 def _H : sve2_misc<0b01, { 0b00, opc }, asm, ZPR16, ZPR8>; 2415 def _S : sve2_misc<0b10, { 0b00, opc }, asm, ZPR32, ZPR16>; 2416 def _D : sve2_misc<0b11, { 0b00, opc }, asm, ZPR64, ZPR32>; 2417} 2418 2419class sve2_bitwise_xor_interleaved<bits<2> sz, bits<1> opc, string asm, 2420 ZPRRegOp zprty1, ZPRRegOp zprty2> 2421: I<(outs zprty1:$Zd), (ins zprty1:$_Zd, zprty2:$Zn, zprty2:$Zm), 2422 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> { 2423 bits<5> Zd; 2424 bits<5> Zn; 2425 bits<5> Zm; 2426 let Inst{31-24} = 0b01000101; 2427 let Inst{23-22} = sz; 2428 let Inst{21} = 0b0; 2429 let Inst{20-16} = Zm; 2430 let Inst{15-11} = 0b10010; 2431 let Inst{10} = opc; 2432 let Inst{9-5} = Zn; 2433 let Inst{4-0} = Zd; 2434 2435 let Constraints = "$Zd = $_Zd"; 2436 let DestructiveInstType = Destructive; 2437 let ElementSize = ElementSizeNone; 2438} 2439 2440multiclass sve2_bitwise_xor_interleaved<bit opc, string asm> { 2441 def _B : sve2_bitwise_xor_interleaved<0b00, opc, asm, ZPR8, ZPR8>; 2442 def _H : sve2_bitwise_xor_interleaved<0b01, opc, asm, ZPR16, ZPR16>; 2443 def _S : sve2_bitwise_xor_interleaved<0b10, opc, asm, ZPR32, ZPR32>; 2444 def _D : sve2_bitwise_xor_interleaved<0b11, opc, asm, ZPR64, ZPR64>; 2445} 2446 2447class sve2_bitwise_shift_left_long<bits<3> tsz8_64, bits<2> opc, string asm, 2448 ZPRRegOp zprty1, ZPRRegOp zprty2, 2449 Operand immtype> 2450: I<(outs zprty1:$Zd), (ins zprty2:$Zn, immtype:$imm), 2451 asm, "\t$Zd, $Zn, $imm", 2452 "", []>, Sched<[]> { 2453 bits<5> Zd; 2454 bits<5> Zn; 2455 bits<5> imm; 2456 let Inst{31-23} = 0b010001010; 2457 let Inst{22} = tsz8_64{2}; 2458 let Inst{21} = 0b0; 2459 let Inst{20-19} = tsz8_64{1-0}; 2460 let Inst{18-16} = imm{2-0}; // imm3 2461 let Inst{15-12} = 0b1010; 2462 let Inst{11-10} = opc; 2463 let Inst{9-5} = Zn; 2464 let Inst{4-0} = Zd; 2465} 2466 2467multiclass sve2_bitwise_shift_left_long<bits<2> opc, string asm> { 2468 def _H : sve2_bitwise_shift_left_long<{0,0,1}, opc, asm, 2469 ZPR16, ZPR8, vecshiftL8>; 2470 def _S : sve2_bitwise_shift_left_long<{0,1,?}, opc, asm, 2471 ZPR32, ZPR16, vecshiftL16> { 2472 let Inst{19} = imm{3}; 2473 } 2474 def _D : sve2_bitwise_shift_left_long<{1,?,?}, opc, asm, 2475 ZPR64, ZPR32, vecshiftL32> { 2476 let Inst{20-19} = imm{4-3}; 2477 } 2478} 2479 2480//===----------------------------------------------------------------------===// 2481// SVE2 Accumulate Group 2482//===----------------------------------------------------------------------===// 2483 2484class sve2_int_bin_shift_imm<bits<4> tsz8_64, bit opc, string asm, 2485 ZPRRegOp zprty, Operand immtype> 2486: I<(outs zprty:$Zd), (ins zprty:$_Zd, zprty:$Zn, immtype:$imm), 2487 asm, "\t$Zd, $Zn, $imm", 2488 "", []>, Sched<[]> { 2489 bits<5> Zd; 2490 bits<5> Zn; 2491 bits<6> imm; 2492 let Inst{31-24} = 0b01000101; 2493 let Inst{23-22} = tsz8_64{3-2}; 2494 let Inst{21} = 0b0; 2495 let Inst{20-19} = tsz8_64{1-0}; 2496 let Inst{18-16} = imm{2-0}; // imm3 2497 let Inst{15-11} = 0b11110; 2498 let Inst{10} = opc; 2499 let Inst{9-5} = Zn; 2500 let Inst{4-0} = Zd; 2501 2502 let Constraints = "$Zd = $_Zd"; 2503} 2504 2505multiclass sve2_int_bin_shift_imm_left<bit opc, string asm> { 2506 def _B : sve2_int_bin_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>; 2507 def _H : sve2_int_bin_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> { 2508 let Inst{19} = imm{3}; 2509 } 2510 def _S : sve2_int_bin_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> { 2511 let Inst{20-19} = imm{4-3}; 2512 } 2513 def _D : sve2_int_bin_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> { 2514 let Inst{22} = imm{5}; 2515 let Inst{20-19} = imm{4-3}; 2516 } 2517} 2518 2519multiclass sve2_int_bin_shift_imm_right<bit opc, string asm> { 2520 def _B : sve2_int_bin_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>; 2521 def _H : sve2_int_bin_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> { 2522 let Inst{19} = imm{3}; 2523 } 2524 def _S : sve2_int_bin_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> { 2525 let Inst{20-19} = imm{4-3}; 2526 } 2527 def _D : sve2_int_bin_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> { 2528 let Inst{22} = imm{5}; 2529 let Inst{20-19} = imm{4-3}; 2530 } 2531} 2532 2533class sve2_int_bin_accum_shift_imm<bits<4> tsz8_64, bits<2> opc, string asm, 2534 ZPRRegOp zprty, Operand immtype> 2535: I<(outs zprty:$Zda), (ins zprty:$_Zda, zprty:$Zn, immtype:$imm), 2536 asm, "\t$Zda, $Zn, $imm", 2537 "", []>, Sched<[]> { 2538 bits<5> Zda; 2539 bits<5> Zn; 2540 bits<6> imm; 2541 let Inst{31-24} = 0b01000101; 2542 let Inst{23-22} = tsz8_64{3-2}; 2543 let Inst{21} = 0b0; 2544 let Inst{20-19} = tsz8_64{1-0}; 2545 let Inst{18-16} = imm{2-0}; // imm3 2546 let Inst{15-12} = 0b1110; 2547 let Inst{11-10} = opc; 2548 let Inst{9-5} = Zn; 2549 let Inst{4-0} = Zda; 2550 2551 let Constraints = "$Zda = $_Zda"; 2552 let DestructiveInstType = Destructive; 2553 let ElementSize = ElementSizeNone; 2554} 2555 2556multiclass sve2_int_bin_accum_shift_imm_right<bits<2> opc, string asm> { 2557 def _B : sve2_int_bin_accum_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>; 2558 def _H : sve2_int_bin_accum_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> { 2559 let Inst{19} = imm{3}; 2560 } 2561 def _S : sve2_int_bin_accum_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> { 2562 let Inst{20-19} = imm{4-3}; 2563 } 2564 def _D : sve2_int_bin_accum_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> { 2565 let Inst{22} = imm{5}; 2566 let Inst{20-19} = imm{4-3}; 2567 } 2568} 2569 2570class sve2_int_cadd<bits<2> sz, bit opc, string asm, ZPRRegOp zprty> 2571: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, complexrotateopodd:$rot), 2572 asm, "\t$Zdn, $_Zdn, $Zm, $rot", "", []>, Sched<[]> { 2573 bits<5> Zdn; 2574 bits<5> Zm; 2575 bit rot; 2576 let Inst{31-24} = 0b01000101; 2577 let Inst{23-22} = sz; 2578 let Inst{21-17} = 0b00000; 2579 let Inst{16} = opc; 2580 let Inst{15-11} = 0b11011; 2581 let Inst{10} = rot; 2582 let Inst{9-5} = Zm; 2583 let Inst{4-0} = Zdn; 2584 2585 let Constraints = "$Zdn = $_Zdn"; 2586 let DestructiveInstType = Destructive; 2587 let ElementSize = ElementSizeNone; 2588} 2589 2590multiclass sve2_int_cadd<bit opc, string asm> { 2591 def _B : sve2_int_cadd<0b00, opc, asm, ZPR8>; 2592 def _H : sve2_int_cadd<0b01, opc, asm, ZPR16>; 2593 def _S : sve2_int_cadd<0b10, opc, asm, ZPR32>; 2594 def _D : sve2_int_cadd<0b11, opc, asm, ZPR64>; 2595} 2596 2597class sve2_int_absdiff_accum<bits<2> sz, bits<4> opc, string asm, 2598 ZPRRegOp zprty1, ZPRRegOp zprty2> 2599: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm), 2600 asm, "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> { 2601 bits<5> Zda; 2602 bits<5> Zn; 2603 bits<5> Zm; 2604 let Inst{31-24} = 0b01000101; 2605 let Inst{23-22} = sz; 2606 let Inst{21} = 0b0; 2607 let Inst{20-16} = Zm; 2608 let Inst{15-14} = 0b11; 2609 let Inst{13-10} = opc; 2610 let Inst{9-5} = Zn; 2611 let Inst{4-0} = Zda; 2612 2613 let Constraints = "$Zda = $_Zda"; 2614 let DestructiveInstType = Destructive; 2615 let ElementSize = ElementSizeNone; 2616} 2617 2618multiclass sve2_int_absdiff_accum<bit opc, string asm> { 2619 def _B : sve2_int_absdiff_accum<0b00, { 0b111, opc }, asm, ZPR8, ZPR8>; 2620 def _H : sve2_int_absdiff_accum<0b01, { 0b111, opc }, asm, ZPR16, ZPR16>; 2621 def _S : sve2_int_absdiff_accum<0b10, { 0b111, opc }, asm, ZPR32, ZPR32>; 2622 def _D : sve2_int_absdiff_accum<0b11, { 0b111, opc }, asm, ZPR64, ZPR64>; 2623} 2624 2625multiclass sve2_int_absdiff_accum_long<bits<2> opc, string asm> { 2626 def _H : sve2_int_absdiff_accum<0b01, { 0b00, opc }, asm, ZPR16, ZPR8>; 2627 def _S : sve2_int_absdiff_accum<0b10, { 0b00, opc }, asm, ZPR32, ZPR16>; 2628 def _D : sve2_int_absdiff_accum<0b11, { 0b00, opc }, asm, ZPR64, ZPR32>; 2629} 2630 2631multiclass sve2_int_addsub_long_carry<bits<2> opc, string asm> { 2632 def _S : sve2_int_absdiff_accum<{ opc{1}, 0b0 }, { 0b010, opc{0} }, asm, 2633 ZPR32, ZPR32>; 2634 def _D : sve2_int_absdiff_accum<{ opc{1}, 0b1 }, { 0b010, opc{0} }, asm, 2635 ZPR64, ZPR64>; 2636} 2637 2638//===----------------------------------------------------------------------===// 2639// SVE2 Narrowing Group 2640//===----------------------------------------------------------------------===// 2641 2642class sve2_int_bin_shift_imm_narrow_bottom<bits<3> tsz8_64, bits<3> opc, 2643 string asm, ZPRRegOp zprty1, 2644 ZPRRegOp zprty2, Operand immtype> 2645: I<(outs zprty1:$Zd), (ins zprty2:$Zn, immtype:$imm), 2646 asm, "\t$Zd, $Zn, $imm", 2647 "", []>, Sched<[]> { 2648 bits<5> Zd; 2649 bits<5> Zn; 2650 bits<5> imm; 2651 let Inst{31-23} = 0b010001010; 2652 let Inst{22} = tsz8_64{2}; 2653 let Inst{21} = 0b1; 2654 let Inst{20-19} = tsz8_64{1-0}; 2655 let Inst{18-16} = imm{2-0}; // imm3 2656 let Inst{15-14} = 0b00; 2657 let Inst{13-11} = opc; 2658 let Inst{10} = 0b0; 2659 let Inst{9-5} = Zn; 2660 let Inst{4-0} = Zd; 2661} 2662 2663multiclass sve2_int_bin_shift_imm_right_narrow_bottom<bits<3> opc, string asm> { 2664 def _B : sve2_int_bin_shift_imm_narrow_bottom<{0,0,1}, opc, asm, ZPR8, ZPR16, 2665 vecshiftR8>; 2666 def _H : sve2_int_bin_shift_imm_narrow_bottom<{0,1,?}, opc, asm, ZPR16, ZPR32, 2667 vecshiftR16> { 2668 let Inst{19} = imm{3}; 2669 } 2670 def _S : sve2_int_bin_shift_imm_narrow_bottom<{1,?,?}, opc, asm, ZPR32, ZPR64, 2671 vecshiftR32> { 2672 let Inst{20-19} = imm{4-3}; 2673 } 2674} 2675 2676class sve2_int_bin_shift_imm_narrow_top<bits<3> tsz8_64, bits<3> opc, 2677 string asm, ZPRRegOp zprty1, 2678 ZPRRegOp zprty2, Operand immtype> 2679: I<(outs zprty1:$Zd), (ins zprty1:$_Zd, zprty2:$Zn, immtype:$imm), 2680 asm, "\t$Zd, $Zn, $imm", 2681 "", []>, Sched<[]> { 2682 bits<5> Zd; 2683 bits<5> Zn; 2684 bits<5> imm; 2685 let Inst{31-23} = 0b010001010; 2686 let Inst{22} = tsz8_64{2}; 2687 let Inst{21} = 0b1; 2688 let Inst{20-19} = tsz8_64{1-0}; 2689 let Inst{18-16} = imm{2-0}; // imm3 2690 let Inst{15-14} = 0b00; 2691 let Inst{13-11} = opc; 2692 let Inst{10} = 0b1; 2693 let Inst{9-5} = Zn; 2694 let Inst{4-0} = Zd; 2695 2696 let Constraints = "$Zd = $_Zd"; 2697} 2698 2699multiclass sve2_int_bin_shift_imm_right_narrow_top<bits<3> opc, string asm> { 2700 def _B : sve2_int_bin_shift_imm_narrow_top<{0,0,1}, opc, asm, ZPR8, ZPR16, 2701 vecshiftR8>; 2702 def _H : sve2_int_bin_shift_imm_narrow_top<{0,1,?}, opc, asm, ZPR16, ZPR32, 2703 vecshiftR16> { 2704 let Inst{19} = imm{3}; 2705 } 2706 def _S : sve2_int_bin_shift_imm_narrow_top<{1,?,?}, opc, asm, ZPR32, ZPR64, 2707 vecshiftR32> { 2708 let Inst{20-19} = imm{4-3}; 2709 } 2710} 2711 2712class sve2_int_addsub_narrow_high_bottom<bits<2> sz, bits<2> opc, string asm, 2713 ZPRRegOp zprty1, ZPRRegOp zprty2> 2714: I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty2:$Zm), 2715 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> { 2716 bits<5> Zd; 2717 bits<5> Zn; 2718 bits<5> Zm; 2719 let Inst{31-24} = 0b01000101; 2720 let Inst{23-22} = sz; 2721 let Inst{21} = 0b1; 2722 let Inst{20-16} = Zm; 2723 let Inst{15-13} = 0b011; 2724 let Inst{12-11} = opc; // S, R 2725 let Inst{10} = 0b0; // Top 2726 let Inst{9-5} = Zn; 2727 let Inst{4-0} = Zd; 2728} 2729 2730multiclass sve2_int_addsub_narrow_high_bottom<bits<2> opc, string asm> { 2731 def _B : sve2_int_addsub_narrow_high_bottom<0b01, opc, asm, ZPR8, ZPR16>; 2732 def _H : sve2_int_addsub_narrow_high_bottom<0b10, opc, asm, ZPR16, ZPR32>; 2733 def _S : sve2_int_addsub_narrow_high_bottom<0b11, opc, asm, ZPR32, ZPR64>; 2734} 2735 2736class sve2_int_addsub_narrow_high_top<bits<2> sz, bits<2> opc, string asm, 2737 ZPRRegOp zprty1, ZPRRegOp zprty2> 2738: I<(outs zprty1:$Zd), (ins zprty1:$_Zd, zprty2:$Zn, zprty2:$Zm), 2739 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> { 2740 bits<5> Zd; 2741 bits<5> Zn; 2742 bits<5> Zm; 2743 let Inst{31-24} = 0b01000101; 2744 let Inst{23-22} = sz; 2745 let Inst{21} = 0b1; 2746 let Inst{20-16} = Zm; 2747 let Inst{15-13} = 0b011; 2748 let Inst{12-11} = opc; // S, R 2749 let Inst{10} = 0b1; // Top 2750 let Inst{9-5} = Zn; 2751 let Inst{4-0} = Zd; 2752 2753 let Constraints = "$Zd = $_Zd"; 2754} 2755 2756multiclass sve2_int_addsub_narrow_high_top<bits<2> opc, string asm> { 2757 def _B : sve2_int_addsub_narrow_high_top<0b01, opc, asm, ZPR8, ZPR16>; 2758 def _H : sve2_int_addsub_narrow_high_top<0b10, opc, asm, ZPR16, ZPR32>; 2759 def _S : sve2_int_addsub_narrow_high_top<0b11, opc, asm, ZPR32, ZPR64>; 2760} 2761 2762class sve2_int_sat_extract_narrow_bottom<bits<3> tsz8_64, bits<2> opc, string asm, 2763 ZPRRegOp zprty1, ZPRRegOp zprty2> 2764: I<(outs zprty1:$Zd), (ins zprty2:$Zn), 2765 asm, "\t$Zd, $Zn", "", []>, Sched<[]> { 2766 bits<5> Zd; 2767 bits<5> Zn; 2768 let Inst{31-23} = 0b010001010; 2769 let Inst{22} = tsz8_64{2}; 2770 let Inst{21} = 0b1; 2771 let Inst{20-19} = tsz8_64{1-0}; 2772 let Inst{18-13} = 0b000010; 2773 let Inst{12-11} = opc; 2774 let Inst{10} = 0b0; 2775 let Inst{9-5} = Zn; 2776 let Inst{4-0} = Zd; 2777} 2778 2779multiclass sve2_int_sat_extract_narrow_bottom<bits<2> opc, string asm> { 2780 def _B : sve2_int_sat_extract_narrow_bottom<0b001, opc, asm, ZPR8, ZPR16>; 2781 def _H : sve2_int_sat_extract_narrow_bottom<0b010, opc, asm, ZPR16, ZPR32>; 2782 def _S : sve2_int_sat_extract_narrow_bottom<0b100, opc, asm, ZPR32, ZPR64>; 2783} 2784 2785class sve2_int_sat_extract_narrow_top<bits<3> tsz8_64, bits<2> opc, string asm, 2786 ZPRRegOp zprty1, ZPRRegOp zprty2> 2787: I<(outs zprty1:$Zd), (ins zprty1:$_Zd, zprty2:$Zn), 2788 asm, "\t$Zd, $Zn", "", []>, Sched<[]> { 2789 bits<5> Zd; 2790 bits<5> Zn; 2791 let Inst{31-23} = 0b010001010; 2792 let Inst{22} = tsz8_64{2}; 2793 let Inst{21} = 0b1; 2794 let Inst{20-19} = tsz8_64{1-0}; 2795 let Inst{18-13} = 0b000010; 2796 let Inst{12-11} = opc; 2797 let Inst{10} = 0b1; 2798 let Inst{9-5} = Zn; 2799 let Inst{4-0} = Zd; 2800 2801 let Constraints = "$Zd = $_Zd"; 2802} 2803 2804multiclass sve2_int_sat_extract_narrow_top<bits<2> opc, string asm> { 2805 def _B : sve2_int_sat_extract_narrow_top<0b001, opc, asm, ZPR8, ZPR16>; 2806 def _H : sve2_int_sat_extract_narrow_top<0b010, opc, asm, ZPR16, ZPR32>; 2807 def _S : sve2_int_sat_extract_narrow_top<0b100, opc, asm, ZPR32, ZPR64>; 2808} 2809 2810//===----------------------------------------------------------------------===// 2811// SVE Integer Arithmetic - Unary Predicated Group 2812//===----------------------------------------------------------------------===// 2813 2814class sve_int_un_pred_arit<bits<2> sz8_64, bits<4> opc, 2815 string asm, ZPRRegOp zprty> 2816: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn), 2817 asm, "\t$Zd, $Pg/m, $Zn", 2818 "", 2819 []>, Sched<[]> { 2820 bits<3> Pg; 2821 bits<5> Zd; 2822 bits<5> Zn; 2823 let Inst{31-24} = 0b00000100; 2824 let Inst{23-22} = sz8_64; 2825 let Inst{21-20} = 0b01; 2826 let Inst{19} = opc{0}; 2827 let Inst{18-16} = opc{3-1}; 2828 let Inst{15-13} = 0b101; 2829 let Inst{12-10} = Pg; 2830 let Inst{9-5} = Zn; 2831 let Inst{4-0} = Zd; 2832 2833 let Constraints = "$Zd = $_Zd"; 2834 let DestructiveInstType = Destructive; 2835 let ElementSize = zprty.ElementSize; 2836} 2837 2838multiclass sve_int_un_pred_arit_0<bits<3> opc, string asm> { 2839 def _B : sve_int_un_pred_arit<0b00, { opc, 0b0 }, asm, ZPR8>; 2840 def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>; 2841 def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>; 2842 def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>; 2843} 2844 2845multiclass sve_int_un_pred_arit_0_h<bits<3> opc, string asm> { 2846 def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>; 2847 def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>; 2848 def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>; 2849} 2850 2851multiclass sve_int_un_pred_arit_0_w<bits<3> opc, string asm> { 2852 def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>; 2853 def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>; 2854} 2855 2856multiclass sve_int_un_pred_arit_0_d<bits<3> opc, string asm> { 2857 def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>; 2858} 2859 2860multiclass sve_int_un_pred_arit_1<bits<3> opc, string asm> { 2861 def _B : sve_int_un_pred_arit<0b00, { opc, 0b1 }, asm, ZPR8>; 2862 def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>; 2863 def _S : sve_int_un_pred_arit<0b10, { opc, 0b1 }, asm, ZPR32>; 2864 def _D : sve_int_un_pred_arit<0b11, { opc, 0b1 }, asm, ZPR64>; 2865} 2866 2867multiclass sve_int_un_pred_arit_1_fp<bits<3> opc, string asm> { 2868 def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>; 2869 def _S : sve_int_un_pred_arit<0b10, { opc, 0b1 }, asm, ZPR32>; 2870 def _D : sve_int_un_pred_arit<0b11, { opc, 0b1 }, asm, ZPR64>; 2871} 2872 2873//===----------------------------------------------------------------------===// 2874// SVE Integer Wide Immediate - Unpredicated Group 2875//===----------------------------------------------------------------------===// 2876class sve_int_dup_imm<bits<2> sz8_64, string asm, 2877 ZPRRegOp zprty, Operand immtype> 2878: I<(outs zprty:$Zd), (ins immtype:$imm), 2879 asm, "\t$Zd, $imm", 2880 "", 2881 []>, Sched<[]> { 2882 bits<5> Zd; 2883 bits<9> imm; 2884 let Inst{31-24} = 0b00100101; 2885 let Inst{23-22} = sz8_64; 2886 let Inst{21-14} = 0b11100011; 2887 let Inst{13} = imm{8}; // sh 2888 let Inst{12-5} = imm{7-0}; // imm8 2889 let Inst{4-0} = Zd; 2890 2891 let isReMaterializable = 1; 2892} 2893 2894multiclass sve_int_dup_imm<string asm> { 2895 def _B : sve_int_dup_imm<0b00, asm, ZPR8, cpy_imm8_opt_lsl_i8>; 2896 def _H : sve_int_dup_imm<0b01, asm, ZPR16, cpy_imm8_opt_lsl_i16>; 2897 def _S : sve_int_dup_imm<0b10, asm, ZPR32, cpy_imm8_opt_lsl_i32>; 2898 def _D : sve_int_dup_imm<0b11, asm, ZPR64, cpy_imm8_opt_lsl_i64>; 2899 2900 def : InstAlias<"mov $Zd, $imm", 2901 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, cpy_imm8_opt_lsl_i8:$imm), 1>; 2902 def : InstAlias<"mov $Zd, $imm", 2903 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, cpy_imm8_opt_lsl_i16:$imm), 1>; 2904 def : InstAlias<"mov $Zd, $imm", 2905 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, cpy_imm8_opt_lsl_i32:$imm), 1>; 2906 def : InstAlias<"mov $Zd, $imm", 2907 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, cpy_imm8_opt_lsl_i64:$imm), 1>; 2908 2909 def : InstAlias<"fmov $Zd, #0.0", 2910 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, 0, 0), 1>; 2911 def : InstAlias<"fmov $Zd, #0.0", 2912 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, 0, 0), 1>; 2913 def : InstAlias<"fmov $Zd, #0.0", 2914 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, 0, 0), 1>; 2915} 2916 2917class sve_int_dup_fpimm<bits<2> sz8_64, Operand fpimmtype, 2918 string asm, ZPRRegOp zprty> 2919: I<(outs zprty:$Zd), (ins fpimmtype:$imm8), 2920 asm, "\t$Zd, $imm8", 2921 "", 2922 []>, Sched<[]> { 2923 bits<5> Zd; 2924 bits<8> imm8; 2925 let Inst{31-24} = 0b00100101; 2926 let Inst{23-22} = sz8_64; 2927 let Inst{21-14} = 0b11100111; 2928 let Inst{13} = 0b0; 2929 let Inst{12-5} = imm8; 2930 let Inst{4-0} = Zd; 2931 2932 let isReMaterializable = 1; 2933} 2934 2935multiclass sve_int_dup_fpimm<string asm> { 2936 def _H : sve_int_dup_fpimm<0b01, fpimm16, asm, ZPR16>; 2937 def _S : sve_int_dup_fpimm<0b10, fpimm32, asm, ZPR32>; 2938 def _D : sve_int_dup_fpimm<0b11, fpimm64, asm, ZPR64>; 2939 2940 def : InstAlias<"fmov $Zd, $imm8", 2941 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, fpimm16:$imm8), 1>; 2942 def : InstAlias<"fmov $Zd, $imm8", 2943 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, fpimm32:$imm8), 1>; 2944 def : InstAlias<"fmov $Zd, $imm8", 2945 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, fpimm64:$imm8), 1>; 2946} 2947 2948class sve_int_arith_imm0<bits<2> sz8_64, bits<3> opc, string asm, 2949 ZPRRegOp zprty, Operand immtype> 2950: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, immtype:$imm), 2951 asm, "\t$Zdn, $_Zdn, $imm", 2952 "", 2953 []>, Sched<[]> { 2954 bits<5> Zdn; 2955 bits<9> imm; 2956 let Inst{31-24} = 0b00100101; 2957 let Inst{23-22} = sz8_64; 2958 let Inst{21-19} = 0b100; 2959 let Inst{18-16} = opc; 2960 let Inst{15-14} = 0b11; 2961 let Inst{13} = imm{8}; // sh 2962 let Inst{12-5} = imm{7-0}; // imm8 2963 let Inst{4-0} = Zdn; 2964 2965 let Constraints = "$Zdn = $_Zdn"; 2966 let DestructiveInstType = Destructive; 2967 let ElementSize = ElementSizeNone; 2968} 2969 2970multiclass sve_int_arith_imm0<bits<3> opc, string asm> { 2971 def _B : sve_int_arith_imm0<0b00, opc, asm, ZPR8, addsub_imm8_opt_lsl_i8>; 2972 def _H : sve_int_arith_imm0<0b01, opc, asm, ZPR16, addsub_imm8_opt_lsl_i16>; 2973 def _S : sve_int_arith_imm0<0b10, opc, asm, ZPR32, addsub_imm8_opt_lsl_i32>; 2974 def _D : sve_int_arith_imm0<0b11, opc, asm, ZPR64, addsub_imm8_opt_lsl_i64>; 2975} 2976 2977class sve_int_arith_imm<bits<2> sz8_64, bits<6> opc, string asm, 2978 ZPRRegOp zprty, Operand immtype> 2979: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, immtype:$imm), 2980 asm, "\t$Zdn, $_Zdn, $imm", 2981 "", 2982 []>, Sched<[]> { 2983 bits<5> Zdn; 2984 bits<8> imm; 2985 let Inst{31-24} = 0b00100101; 2986 let Inst{23-22} = sz8_64; 2987 let Inst{21-16} = opc; 2988 let Inst{15-13} = 0b110; 2989 let Inst{12-5} = imm; 2990 let Inst{4-0} = Zdn; 2991 2992 let Constraints = "$Zdn = $_Zdn"; 2993 let DestructiveInstType = Destructive; 2994 let ElementSize = ElementSizeNone; 2995} 2996 2997multiclass sve_int_arith_imm1<bits<2> opc, string asm, Operand immtype> { 2998 def _B : sve_int_arith_imm<0b00, { 0b1010, opc }, asm, ZPR8, immtype>; 2999 def _H : sve_int_arith_imm<0b01, { 0b1010, opc }, asm, ZPR16, immtype>; 3000 def _S : sve_int_arith_imm<0b10, { 0b1010, opc }, asm, ZPR32, immtype>; 3001 def _D : sve_int_arith_imm<0b11, { 0b1010, opc }, asm, ZPR64, immtype>; 3002} 3003 3004multiclass sve_int_arith_imm2<string asm> { 3005 def _B : sve_int_arith_imm<0b00, 0b110000, asm, ZPR8, simm8>; 3006 def _H : sve_int_arith_imm<0b01, 0b110000, asm, ZPR16, simm8>; 3007 def _S : sve_int_arith_imm<0b10, 0b110000, asm, ZPR32, simm8>; 3008 def _D : sve_int_arith_imm<0b11, 0b110000, asm, ZPR64, simm8>; 3009} 3010 3011//===----------------------------------------------------------------------===// 3012// SVE Bitwise Logical - Unpredicated Group 3013//===----------------------------------------------------------------------===// 3014 3015class sve_int_bin_cons_log<bits<2> opc, string asm> 3016: I<(outs ZPR64:$Zd), (ins ZPR64:$Zn, ZPR64:$Zm), 3017 asm, "\t$Zd, $Zn, $Zm", 3018 "", 3019 []>, Sched<[]> { 3020 bits<5> Zd; 3021 bits<5> Zm; 3022 bits<5> Zn; 3023 let Inst{31-24} = 0b00000100; 3024 let Inst{23-22} = opc{1-0}; 3025 let Inst{21} = 0b1; 3026 let Inst{20-16} = Zm; 3027 let Inst{15-10} = 0b001100; 3028 let Inst{9-5} = Zn; 3029 let Inst{4-0} = Zd; 3030} 3031 3032multiclass sve_int_bin_cons_log<bits<2> opc, string asm> { 3033 def NAME : sve_int_bin_cons_log<opc, asm>; 3034 3035 def : InstAlias<asm # "\t$Zd, $Zn, $Zm", 3036 (!cast<Instruction>(NAME) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 1>; 3037 def : InstAlias<asm # "\t$Zd, $Zn, $Zm", 3038 (!cast<Instruction>(NAME) ZPR16:$Zd, ZPR16:$Zn, ZPR16:$Zm), 1>; 3039 def : InstAlias<asm # "\t$Zd, $Zn, $Zm", 3040 (!cast<Instruction>(NAME) ZPR32:$Zd, ZPR32:$Zn, ZPR32:$Zm), 1>; 3041} 3042 3043class sve2_int_bitwise_ternary_op_d<bits<3> opc, string asm> 3044: I<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, ZPR64:$Zm, ZPR64:$Zk), 3045 asm, "\t$Zdn, $_Zdn, $Zm, $Zk", 3046 "", 3047 []>, Sched<[]> { 3048 bits<5> Zdn; 3049 bits<5> Zk; 3050 bits<5> Zm; 3051 let Inst{31-24} = 0b00000100; 3052 let Inst{23-22} = opc{2-1}; 3053 let Inst{21} = 0b1; 3054 let Inst{20-16} = Zm; 3055 let Inst{15-11} = 0b00111; 3056 let Inst{10} = opc{0}; 3057 let Inst{9-5} = Zk; 3058 let Inst{4-0} = Zdn; 3059 3060 let Constraints = "$Zdn = $_Zdn"; 3061 let DestructiveInstType = Destructive; 3062 let ElementSize = ElementSizeNone; 3063} 3064 3065multiclass sve2_int_bitwise_ternary_op<bits<3> opc, string asm> { 3066 def NAME : sve2_int_bitwise_ternary_op_d<opc, asm>; 3067 3068 def : InstAlias<asm # "\t$Zdn, $Zdn, $Zm, $Zk", 3069 (!cast<Instruction>(NAME) ZPR8:$Zdn, ZPR8:$Zm, ZPR8:$Zk), 1>; 3070 def : InstAlias<asm # "\t$Zdn, $Zdn, $Zm, $Zk", 3071 (!cast<Instruction>(NAME) ZPR16:$Zdn, ZPR16:$Zm, ZPR16:$Zk), 1>; 3072 def : InstAlias<asm # "\t$Zdn, $Zdn, $Zm, $Zk", 3073 (!cast<Instruction>(NAME) ZPR32:$Zdn, ZPR32:$Zm, ZPR32:$Zk), 1>; 3074} 3075 3076class sve2_int_rotate_right_imm<bits<4> tsz8_64, string asm, 3077 ZPRRegOp zprty, Operand immtype> 3078: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, immtype:$imm), 3079 asm, "\t$Zdn, $_Zdn, $Zm, $imm", 3080 "", 3081 []>, Sched<[]> { 3082 bits<5> Zdn; 3083 bits<5> Zm; 3084 bits<6> imm; 3085 let Inst{31-24} = 0b00000100; 3086 let Inst{23-22} = tsz8_64{3-2}; 3087 let Inst{21} = 0b1; 3088 let Inst{20-19} = tsz8_64{1-0}; 3089 let Inst{18-16} = imm{2-0}; // imm3 3090 let Inst{15-10} = 0b001101; 3091 let Inst{9-5} = Zm; 3092 let Inst{4-0} = Zdn; 3093 3094 let Constraints = "$Zdn = $_Zdn"; 3095 let DestructiveInstType = Destructive; 3096 let ElementSize = ElementSizeNone; 3097} 3098 3099multiclass sve2_int_rotate_right_imm<string asm> { 3100 def _B : sve2_int_rotate_right_imm<{0,0,0,1}, asm, ZPR8, vecshiftR8>; 3101 def _H : sve2_int_rotate_right_imm<{0,0,1,?}, asm, ZPR16, vecshiftR16> { 3102 let Inst{19} = imm{3}; 3103 } 3104 def _S : sve2_int_rotate_right_imm<{0,1,?,?}, asm, ZPR32, vecshiftR32> { 3105 let Inst{20-19} = imm{4-3}; 3106 } 3107 def _D : sve2_int_rotate_right_imm<{1,?,?,?}, asm, ZPR64, vecshiftR64> { 3108 let Inst{22} = imm{5}; 3109 let Inst{20-19} = imm{4-3}; 3110 } 3111} 3112 3113//===----------------------------------------------------------------------===// 3114// SVE Integer Wide Immediate - Predicated Group 3115//===----------------------------------------------------------------------===// 3116 3117class sve_int_dup_fpimm_pred<bits<2> sz, Operand fpimmtype, 3118 string asm, ZPRRegOp zprty> 3119: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPRAny:$Pg, fpimmtype:$imm8), 3120 asm, "\t$Zd, $Pg/m, $imm8", 3121 "", 3122 []>, Sched<[]> { 3123 bits<4> Pg; 3124 bits<5> Zd; 3125 bits<8> imm8; 3126 let Inst{31-24} = 0b00000101; 3127 let Inst{23-22} = sz; 3128 let Inst{21-20} = 0b01; 3129 let Inst{19-16} = Pg; 3130 let Inst{15-13} = 0b110; 3131 let Inst{12-5} = imm8; 3132 let Inst{4-0} = Zd; 3133 3134 let Constraints = "$Zd = $_Zd"; 3135 let DestructiveInstType = Destructive; 3136 let ElementSize = zprty.ElementSize; 3137} 3138 3139multiclass sve_int_dup_fpimm_pred<string asm> { 3140 def _H : sve_int_dup_fpimm_pred<0b01, fpimm16, asm, ZPR16>; 3141 def _S : sve_int_dup_fpimm_pred<0b10, fpimm32, asm, ZPR32>; 3142 def _D : sve_int_dup_fpimm_pred<0b11, fpimm64, asm, ZPR64>; 3143 3144 def : InstAlias<"fmov $Zd, $Pg/m, $imm8", 3145 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, fpimm16:$imm8), 1>; 3146 def : InstAlias<"fmov $Zd, $Pg/m, $imm8", 3147 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, fpimm32:$imm8), 1>; 3148 def : InstAlias<"fmov $Zd, $Pg/m, $imm8", 3149 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, fpimm64:$imm8), 1>; 3150} 3151 3152class sve_int_dup_imm_pred<bits<2> sz8_64, bit m, string asm, 3153 ZPRRegOp zprty, string pred_qual, dag iops> 3154: I<(outs zprty:$Zd), iops, 3155 asm, "\t$Zd, $Pg"#pred_qual#", $imm", 3156 "", []>, Sched<[]> { 3157 bits<5> Zd; 3158 bits<4> Pg; 3159 bits<9> imm; 3160 let Inst{31-24} = 0b00000101; 3161 let Inst{23-22} = sz8_64; 3162 let Inst{21-20} = 0b01; 3163 let Inst{19-16} = Pg; 3164 let Inst{15} = 0b0; 3165 let Inst{14} = m; 3166 let Inst{13} = imm{8}; // sh 3167 let Inst{12-5} = imm{7-0}; // imm8 3168 let Inst{4-0} = Zd; 3169 3170 let DestructiveInstType = Destructive; 3171 let ElementSize = zprty.ElementSize; 3172} 3173 3174multiclass sve_int_dup_imm_pred_merge<string asm> { 3175 let Constraints = "$Zd = $_Zd" in { 3176 def _B : sve_int_dup_imm_pred<0b00, 1, asm, ZPR8, "/m", (ins ZPR8:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm)>; 3177 def _H : sve_int_dup_imm_pred<0b01, 1, asm, ZPR16, "/m", (ins ZPR16:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm)>; 3178 def _S : sve_int_dup_imm_pred<0b10, 1, asm, ZPR32, "/m", (ins ZPR32:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm)>; 3179 def _D : sve_int_dup_imm_pred<0b11, 1, asm, ZPR64, "/m", (ins ZPR64:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm)>; 3180 } 3181 3182 def : InstAlias<"mov $Zd, $Pg/m, $imm", 3183 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm), 1>; 3184 def : InstAlias<"mov $Zd, $Pg/m, $imm", 3185 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm), 1>; 3186 def : InstAlias<"mov $Zd, $Pg/m, $imm", 3187 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm), 1>; 3188 def : InstAlias<"mov $Zd, $Pg/m, $imm", 3189 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm), 1>; 3190 3191 def : InstAlias<"fmov $Zd, $Pg/m, #0.0", 3192 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, 0, 0), 0>; 3193 def : InstAlias<"fmov $Zd, $Pg/m, #0.0", 3194 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, 0, 0), 0>; 3195 def : InstAlias<"fmov $Zd, $Pg/m, #0.0", 3196 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, 0, 0), 0>; 3197} 3198 3199multiclass sve_int_dup_imm_pred_zero<string asm> { 3200 def _B : sve_int_dup_imm_pred<0b00, 0, asm, ZPR8, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm)>; 3201 def _H : sve_int_dup_imm_pred<0b01, 0, asm, ZPR16, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm)>; 3202 def _S : sve_int_dup_imm_pred<0b10, 0, asm, ZPR32, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm)>; 3203 def _D : sve_int_dup_imm_pred<0b11, 0, asm, ZPR64, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm)>; 3204 3205 def : InstAlias<"mov $Zd, $Pg/z, $imm", 3206 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm), 1>; 3207 def : InstAlias<"mov $Zd, $Pg/z, $imm", 3208 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm), 1>; 3209 def : InstAlias<"mov $Zd, $Pg/z, $imm", 3210 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm), 1>; 3211 def : InstAlias<"mov $Zd, $Pg/z, $imm", 3212 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm), 1>; 3213} 3214 3215//===----------------------------------------------------------------------===// 3216// SVE Integer Compare - Vectors Group 3217//===----------------------------------------------------------------------===// 3218 3219class sve_int_cmp<bit cmp_1, bits<2> sz8_64, bits<3> opc, string asm, 3220 PPRRegOp pprty, ZPRRegOp zprty1, ZPRRegOp zprty2> 3221: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty1:$Zn, zprty2:$Zm), 3222 asm, "\t$Pd, $Pg/z, $Zn, $Zm", 3223 "", 3224 []>, Sched<[]> { 3225 bits<4> Pd; 3226 bits<3> Pg; 3227 bits<5> Zm; 3228 bits<5> Zn; 3229 let Inst{31-24} = 0b00100100; 3230 let Inst{23-22} = sz8_64; 3231 let Inst{21} = 0b0; 3232 let Inst{20-16} = Zm; 3233 let Inst{15} = opc{2}; 3234 let Inst{14} = cmp_1; 3235 let Inst{13} = opc{1}; 3236 let Inst{12-10} = Pg; 3237 let Inst{9-5} = Zn; 3238 let Inst{4} = opc{0}; 3239 let Inst{3-0} = Pd; 3240 3241 let Defs = [NZCV]; 3242} 3243 3244multiclass sve_int_cmp_0<bits<3> opc, string asm> { 3245 def _B : sve_int_cmp<0b0, 0b00, opc, asm, PPR8, ZPR8, ZPR8>; 3246 def _H : sve_int_cmp<0b0, 0b01, opc, asm, PPR16, ZPR16, ZPR16>; 3247 def _S : sve_int_cmp<0b0, 0b10, opc, asm, PPR32, ZPR32, ZPR32>; 3248 def _D : sve_int_cmp<0b0, 0b11, opc, asm, PPR64, ZPR64, ZPR64>; 3249} 3250 3251multiclass sve_int_cmp_0_wide<bits<3> opc, string asm> { 3252 def _B : sve_int_cmp<0b0, 0b00, opc, asm, PPR8, ZPR8, ZPR64>; 3253 def _H : sve_int_cmp<0b0, 0b01, opc, asm, PPR16, ZPR16, ZPR64>; 3254 def _S : sve_int_cmp<0b0, 0b10, opc, asm, PPR32, ZPR32, ZPR64>; 3255} 3256 3257multiclass sve_int_cmp_1_wide<bits<3> opc, string asm> { 3258 def _B : sve_int_cmp<0b1, 0b00, opc, asm, PPR8, ZPR8, ZPR64>; 3259 def _H : sve_int_cmp<0b1, 0b01, opc, asm, PPR16, ZPR16, ZPR64>; 3260 def _S : sve_int_cmp<0b1, 0b10, opc, asm, PPR32, ZPR32, ZPR64>; 3261} 3262 3263 3264//===----------------------------------------------------------------------===// 3265// SVE Integer Compare - Signed Immediate Group 3266//===----------------------------------------------------------------------===// 3267 3268class sve_int_scmp_vi<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty, 3269 ZPRRegOp zprty, 3270 Operand immtype> 3271: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm5), 3272 asm, "\t$Pd, $Pg/z, $Zn, $imm5", 3273 "", 3274 []>, Sched<[]> { 3275 bits<4> Pd; 3276 bits<3> Pg; 3277 bits<5> Zn; 3278 bits<5> imm5; 3279 let Inst{31-24} = 0b00100101; 3280 let Inst{23-22} = sz8_64; 3281 let Inst{21} = 0b0; 3282 let Inst{20-16} = imm5; 3283 let Inst{15} = opc{2}; 3284 let Inst{14} = 0b0; 3285 let Inst{13} = opc{1}; 3286 let Inst{12-10} = Pg; 3287 let Inst{9-5} = Zn; 3288 let Inst{4} = opc{0}; 3289 let Inst{3-0} = Pd; 3290 3291 let Defs = [NZCV]; 3292} 3293 3294multiclass sve_int_scmp_vi<bits<3> opc, string asm> { 3295 def _B : sve_int_scmp_vi<0b00, opc, asm, PPR8, ZPR8, simm5_32b>; 3296 def _H : sve_int_scmp_vi<0b01, opc, asm, PPR16, ZPR16, simm5_32b>; 3297 def _S : sve_int_scmp_vi<0b10, opc, asm, PPR32, ZPR32, simm5_32b>; 3298 def _D : sve_int_scmp_vi<0b11, opc, asm, PPR64, ZPR64, simm5_64b>; 3299} 3300 3301 3302//===----------------------------------------------------------------------===// 3303// SVE Integer Compare - Unsigned Immediate Group 3304//===----------------------------------------------------------------------===// 3305 3306class sve_int_ucmp_vi<bits<2> sz8_64, bits<2> opc, string asm, PPRRegOp pprty, 3307 ZPRRegOp zprty, Operand immtype> 3308: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm7), 3309 asm, "\t$Pd, $Pg/z, $Zn, $imm7", 3310 "", 3311 []>, Sched<[]> { 3312 bits<4> Pd; 3313 bits<3> Pg; 3314 bits<5> Zn; 3315 bits<7> imm7; 3316 let Inst{31-24} = 0b00100100; 3317 let Inst{23-22} = sz8_64; 3318 let Inst{21} = 1; 3319 let Inst{20-14} = imm7; 3320 let Inst{13} = opc{1}; 3321 let Inst{12-10} = Pg; 3322 let Inst{9-5} = Zn; 3323 let Inst{4} = opc{0}; 3324 let Inst{3-0} = Pd; 3325 3326 let Defs = [NZCV]; 3327} 3328 3329multiclass sve_int_ucmp_vi<bits<2> opc, string asm> { 3330 def _B : sve_int_ucmp_vi<0b00, opc, asm, PPR8, ZPR8, imm0_127>; 3331 def _H : sve_int_ucmp_vi<0b01, opc, asm, PPR16, ZPR16, imm0_127>; 3332 def _S : sve_int_ucmp_vi<0b10, opc, asm, PPR32, ZPR32, imm0_127>; 3333 def _D : sve_int_ucmp_vi<0b11, opc, asm, PPR64, ZPR64, imm0_127>; 3334} 3335 3336 3337//===----------------------------------------------------------------------===// 3338// SVE Integer Compare - Scalars Group 3339//===----------------------------------------------------------------------===// 3340 3341class sve_int_cterm<bit sz, bit opc, string asm, RegisterClass rt> 3342: I<(outs), (ins rt:$Rn, rt:$Rm), 3343 asm, "\t$Rn, $Rm", 3344 "", 3345 []>, Sched<[]> { 3346 bits<5> Rm; 3347 bits<5> Rn; 3348 let Inst{31-23} = 0b001001011; 3349 let Inst{22} = sz; 3350 let Inst{21} = 0b1; 3351 let Inst{20-16} = Rm; 3352 let Inst{15-10} = 0b001000; 3353 let Inst{9-5} = Rn; 3354 let Inst{4} = opc; 3355 let Inst{3-0} = 0b0000; 3356 3357 let Defs = [NZCV]; 3358} 3359 3360class sve_int_while_rr<bits<2> sz8_64, bits<4> opc, string asm, 3361 RegisterClass gprty, PPRRegOp pprty> 3362: I<(outs pprty:$Pd), (ins gprty:$Rn, gprty:$Rm), 3363 asm, "\t$Pd, $Rn, $Rm", 3364 "", []>, Sched<[]> { 3365 bits<4> Pd; 3366 bits<5> Rm; 3367 bits<5> Rn; 3368 let Inst{31-24} = 0b00100101; 3369 let Inst{23-22} = sz8_64; 3370 let Inst{21} = 0b1; 3371 let Inst{20-16} = Rm; 3372 let Inst{15-13} = 0b000; 3373 let Inst{12-10} = opc{3-1}; 3374 let Inst{9-5} = Rn; 3375 let Inst{4} = opc{0}; 3376 let Inst{3-0} = Pd; 3377 3378 let Defs = [NZCV]; 3379} 3380 3381multiclass sve_int_while4_rr<bits<3> opc, string asm> { 3382 def _B : sve_int_while_rr<0b00, { 0, opc }, asm, GPR32, PPR8>; 3383 def _H : sve_int_while_rr<0b01, { 0, opc }, asm, GPR32, PPR16>; 3384 def _S : sve_int_while_rr<0b10, { 0, opc }, asm, GPR32, PPR32>; 3385 def _D : sve_int_while_rr<0b11, { 0, opc }, asm, GPR32, PPR64>; 3386} 3387 3388multiclass sve_int_while8_rr<bits<3> opc, string asm> { 3389 def _B : sve_int_while_rr<0b00, { 1, opc }, asm, GPR64, PPR8>; 3390 def _H : sve_int_while_rr<0b01, { 1, opc }, asm, GPR64, PPR16>; 3391 def _S : sve_int_while_rr<0b10, { 1, opc }, asm, GPR64, PPR32>; 3392 def _D : sve_int_while_rr<0b11, { 1, opc }, asm, GPR64, PPR64>; 3393} 3394 3395class sve2_int_while_rr<bits<2> sz8_64, bits<1> rw, string asm, 3396 PPRRegOp pprty> 3397: I<(outs pprty:$Pd), (ins GPR64:$Rn, GPR64:$Rm), 3398 asm, "\t$Pd, $Rn, $Rm", 3399 "", []>, Sched<[]> { 3400 bits<4> Pd; 3401 bits<5> Rm; 3402 bits<5> Rn; 3403 let Inst{31-24} = 0b00100101; 3404 let Inst{23-22} = sz8_64; 3405 let Inst{21} = 0b1; 3406 let Inst{20-16} = Rm; 3407 let Inst{15-10} = 0b001100; 3408 let Inst{9-5} = Rn; 3409 let Inst{4} = rw; 3410 let Inst{3-0} = Pd; 3411 3412 let Defs = [NZCV]; 3413} 3414 3415multiclass sve2_int_while_rr<bits<1> rw, string asm> { 3416 def _B : sve2_int_while_rr<0b00, rw, asm, PPR8>; 3417 def _H : sve2_int_while_rr<0b01, rw, asm, PPR16>; 3418 def _S : sve2_int_while_rr<0b10, rw, asm, PPR32>; 3419 def _D : sve2_int_while_rr<0b11, rw, asm, PPR64>; 3420} 3421 3422//===----------------------------------------------------------------------===// 3423// SVE Floating Point Fast Reduction Group 3424//===----------------------------------------------------------------------===// 3425 3426class sve_fp_fast_red<bits<2> sz, bits<3> opc, string asm, 3427 ZPRRegOp zprty, RegisterClass dstRegClass> 3428: I<(outs dstRegClass:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn), 3429 asm, "\t$Vd, $Pg, $Zn", 3430 "", 3431 []>, Sched<[]> { 3432 bits<5> Zn; 3433 bits<5> Vd; 3434 bits<3> Pg; 3435 let Inst{31-24} = 0b01100101; 3436 let Inst{23-22} = sz; 3437 let Inst{21-19} = 0b000; 3438 let Inst{18-16} = opc; 3439 let Inst{15-13} = 0b001; 3440 let Inst{12-10} = Pg; 3441 let Inst{9-5} = Zn; 3442 let Inst{4-0} = Vd; 3443} 3444 3445multiclass sve_fp_fast_red<bits<3> opc, string asm> { 3446 def _H : sve_fp_fast_red<0b01, opc, asm, ZPR16, FPR16>; 3447 def _S : sve_fp_fast_red<0b10, opc, asm, ZPR32, FPR32>; 3448 def _D : sve_fp_fast_red<0b11, opc, asm, ZPR64, FPR64>; 3449} 3450 3451 3452//===----------------------------------------------------------------------===// 3453// SVE Floating Point Accumulating Reduction Group 3454//===----------------------------------------------------------------------===// 3455 3456class sve_fp_2op_p_vd<bits<2> sz, bits<3> opc, string asm, 3457 ZPRRegOp zprty, RegisterClass dstRegClass> 3458: I<(outs dstRegClass:$Vdn), (ins PPR3bAny:$Pg, dstRegClass:$_Vdn, zprty:$Zm), 3459 asm, "\t$Vdn, $Pg, $_Vdn, $Zm", 3460 "", 3461 []>, 3462 Sched<[]> { 3463 bits<3> Pg; 3464 bits<5> Vdn; 3465 bits<5> Zm; 3466 let Inst{31-24} = 0b01100101; 3467 let Inst{23-22} = sz; 3468 let Inst{21-19} = 0b011; 3469 let Inst{18-16} = opc; 3470 let Inst{15-13} = 0b001; 3471 let Inst{12-10} = Pg; 3472 let Inst{9-5} = Zm; 3473 let Inst{4-0} = Vdn; 3474 3475 let Constraints = "$Vdn = $_Vdn"; 3476} 3477 3478multiclass sve_fp_2op_p_vd<bits<3> opc, string asm> { 3479 def _H : sve_fp_2op_p_vd<0b01, opc, asm, ZPR16, FPR16>; 3480 def _S : sve_fp_2op_p_vd<0b10, opc, asm, ZPR32, FPR32>; 3481 def _D : sve_fp_2op_p_vd<0b11, opc, asm, ZPR64, FPR64>; 3482} 3483 3484//===----------------------------------------------------------------------===// 3485// SVE Floating Point Compare - Vectors Group 3486//===----------------------------------------------------------------------===// 3487 3488class sve_fp_3op_p_pd<bits<2> sz, bits<3> opc, string asm, PPRRegOp pprty, 3489 ZPRRegOp zprty> 3490: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm), 3491 asm, "\t$Pd, $Pg/z, $Zn, $Zm", 3492 "", 3493 []>, Sched<[]> { 3494 bits<4> Pd; 3495 bits<3> Pg; 3496 bits<5> Zm; 3497 bits<5> Zn; 3498 let Inst{31-24} = 0b01100101; 3499 let Inst{23-22} = sz; 3500 let Inst{21} = 0b0; 3501 let Inst{20-16} = Zm; 3502 let Inst{15} = opc{2}; 3503 let Inst{14} = 0b1; 3504 let Inst{13} = opc{1}; 3505 let Inst{12-10} = Pg; 3506 let Inst{9-5} = Zn; 3507 let Inst{4} = opc{0}; 3508 let Inst{3-0} = Pd; 3509} 3510 3511multiclass sve_fp_3op_p_pd<bits<3> opc, string asm> { 3512 def _H : sve_fp_3op_p_pd<0b01, opc, asm, PPR16, ZPR16>; 3513 def _S : sve_fp_3op_p_pd<0b10, opc, asm, PPR32, ZPR32>; 3514 def _D : sve_fp_3op_p_pd<0b11, opc, asm, PPR64, ZPR64>; 3515} 3516 3517 3518//===----------------------------------------------------------------------===// 3519// SVE Floating Point Compare - with Zero Group 3520//===----------------------------------------------------------------------===// 3521 3522class sve_fp_2op_p_pd<bits<2> sz, bits<3> opc, string asm, PPRRegOp pprty, 3523 ZPRRegOp zprty> 3524: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn), 3525 asm, "\t$Pd, $Pg/z, $Zn, #0.0", 3526 "", 3527 []>, Sched<[]> { 3528 bits<4> Pd; 3529 bits<3> Pg; 3530 bits<5> Zn; 3531 let Inst{31-24} = 0b01100101; 3532 let Inst{23-22} = sz; 3533 let Inst{21-18} = 0b0100; 3534 let Inst{17-16} = opc{2-1}; 3535 let Inst{15-13} = 0b001; 3536 let Inst{12-10} = Pg; 3537 let Inst{9-5} = Zn; 3538 let Inst{4} = opc{0}; 3539 let Inst{3-0} = Pd; 3540} 3541 3542multiclass sve_fp_2op_p_pd<bits<3> opc, string asm> { 3543 def _H : sve_fp_2op_p_pd<0b01, opc, asm, PPR16, ZPR16>; 3544 def _S : sve_fp_2op_p_pd<0b10, opc, asm, PPR32, ZPR32>; 3545 def _D : sve_fp_2op_p_pd<0b11, opc, asm, PPR64, ZPR64>; 3546} 3547 3548 3549//===----------------------------------------------------------------------===// 3550//SVE Index Generation Group 3551//===----------------------------------------------------------------------===// 3552 3553class sve_int_index_ii<bits<2> sz8_64, string asm, ZPRRegOp zprty, 3554 Operand imm_ty> 3555: I<(outs zprty:$Zd), (ins imm_ty:$imm5, imm_ty:$imm5b), 3556 asm, "\t$Zd, $imm5, $imm5b", 3557 "", []>, Sched<[]> { 3558 bits<5> Zd; 3559 bits<5> imm5; 3560 bits<5> imm5b; 3561 let Inst{31-24} = 0b00000100; 3562 let Inst{23-22} = sz8_64; 3563 let Inst{21} = 0b1; 3564 let Inst{20-16} = imm5b; 3565 let Inst{15-10} = 0b010000; 3566 let Inst{9-5} = imm5; 3567 let Inst{4-0} = Zd; 3568} 3569 3570multiclass sve_int_index_ii<string asm> { 3571 def _B : sve_int_index_ii<0b00, asm, ZPR8, simm5_32b>; 3572 def _H : sve_int_index_ii<0b01, asm, ZPR16, simm5_32b>; 3573 def _S : sve_int_index_ii<0b10, asm, ZPR32, simm5_32b>; 3574 def _D : sve_int_index_ii<0b11, asm, ZPR64, simm5_64b>; 3575} 3576 3577class sve_int_index_ir<bits<2> sz8_64, string asm, ZPRRegOp zprty, 3578 RegisterClass srcRegType, Operand imm_ty> 3579: I<(outs zprty:$Zd), (ins imm_ty:$imm5, srcRegType:$Rm), 3580 asm, "\t$Zd, $imm5, $Rm", 3581 "", []>, Sched<[]> { 3582 bits<5> Rm; 3583 bits<5> Zd; 3584 bits<5> imm5; 3585 let Inst{31-24} = 0b00000100; 3586 let Inst{23-22} = sz8_64; 3587 let Inst{21} = 0b1; 3588 let Inst{20-16} = Rm; 3589 let Inst{15-10} = 0b010010; 3590 let Inst{9-5} = imm5; 3591 let Inst{4-0} = Zd; 3592} 3593 3594multiclass sve_int_index_ir<string asm> { 3595 def _B : sve_int_index_ir<0b00, asm, ZPR8, GPR32, simm5_32b>; 3596 def _H : sve_int_index_ir<0b01, asm, ZPR16, GPR32, simm5_32b>; 3597 def _S : sve_int_index_ir<0b10, asm, ZPR32, GPR32, simm5_32b>; 3598 def _D : sve_int_index_ir<0b11, asm, ZPR64, GPR64, simm5_64b>; 3599} 3600 3601class sve_int_index_ri<bits<2> sz8_64, string asm, ZPRRegOp zprty, 3602 RegisterClass srcRegType, Operand imm_ty> 3603: I<(outs zprty:$Zd), (ins srcRegType:$Rn, imm_ty:$imm5), 3604 asm, "\t$Zd, $Rn, $imm5", 3605 "", []>, Sched<[]> { 3606 bits<5> Rn; 3607 bits<5> Zd; 3608 bits<5> imm5; 3609 let Inst{31-24} = 0b00000100; 3610 let Inst{23-22} = sz8_64; 3611 let Inst{21} = 0b1; 3612 let Inst{20-16} = imm5; 3613 let Inst{15-10} = 0b010001; 3614 let Inst{9-5} = Rn; 3615 let Inst{4-0} = Zd; 3616} 3617 3618multiclass sve_int_index_ri<string asm> { 3619 def _B : sve_int_index_ri<0b00, asm, ZPR8, GPR32, simm5_32b>; 3620 def _H : sve_int_index_ri<0b01, asm, ZPR16, GPR32, simm5_32b>; 3621 def _S : sve_int_index_ri<0b10, asm, ZPR32, GPR32, simm5_32b>; 3622 def _D : sve_int_index_ri<0b11, asm, ZPR64, GPR64, simm5_64b>; 3623} 3624 3625class sve_int_index_rr<bits<2> sz8_64, string asm, ZPRRegOp zprty, 3626 RegisterClass srcRegType> 3627: I<(outs zprty:$Zd), (ins srcRegType:$Rn, srcRegType:$Rm), 3628 asm, "\t$Zd, $Rn, $Rm", 3629 "", []>, Sched<[]> { 3630 bits<5> Zd; 3631 bits<5> Rm; 3632 bits<5> Rn; 3633 let Inst{31-24} = 0b00000100; 3634 let Inst{23-22} = sz8_64; 3635 let Inst{21} = 0b1; 3636 let Inst{20-16} = Rm; 3637 let Inst{15-10} = 0b010011; 3638 let Inst{9-5} = Rn; 3639 let Inst{4-0} = Zd; 3640} 3641 3642multiclass sve_int_index_rr<string asm> { 3643 def _B : sve_int_index_rr<0b00, asm, ZPR8, GPR32>; 3644 def _H : sve_int_index_rr<0b01, asm, ZPR16, GPR32>; 3645 def _S : sve_int_index_rr<0b10, asm, ZPR32, GPR32>; 3646 def _D : sve_int_index_rr<0b11, asm, ZPR64, GPR64>; 3647} 3648// 3649//===----------------------------------------------------------------------===// 3650// SVE Bitwise Shift - Predicated Group 3651//===----------------------------------------------------------------------===// 3652class sve_int_bin_pred_shift_imm<bits<4> tsz8_64, bits<4> opc, string asm, 3653 ZPRRegOp zprty, Operand immtype, 3654 ElementSizeEnum size> 3655: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, immtype:$imm), 3656 asm, "\t$Zdn, $Pg/m, $_Zdn, $imm", 3657 "", 3658 []>, Sched<[]> { 3659 bits<3> Pg; 3660 bits<5> Zdn; 3661 bits<6> imm; 3662 let Inst{31-24} = 0b00000100; 3663 let Inst{23-22} = tsz8_64{3-2}; 3664 let Inst{21-20} = 0b00; 3665 let Inst{19-16} = opc; 3666 let Inst{15-13} = 0b100; 3667 let Inst{12-10} = Pg; 3668 let Inst{9-8} = tsz8_64{1-0}; 3669 let Inst{7-5} = imm{2-0}; // imm3 3670 let Inst{4-0} = Zdn; 3671 3672 let Constraints = "$Zdn = $_Zdn"; 3673 let DestructiveInstType = Destructive; 3674 let ElementSize = size; 3675} 3676 3677multiclass sve_int_bin_pred_shift_imm_left<bits<4> opc, string asm> { 3678 def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8, 3679 ElementSizeB>; 3680 def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16, 3681 ElementSizeH> { 3682 let Inst{8} = imm{3}; 3683 } 3684 def _S : sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32, 3685 ElementSizeS> { 3686 let Inst{9-8} = imm{4-3}; 3687 } 3688 def _D : sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64, 3689 ElementSizeD> { 3690 let Inst{22} = imm{5}; 3691 let Inst{9-8} = imm{4-3}; 3692 } 3693} 3694 3695multiclass sve_int_bin_pred_shift_imm_right<bits<4> opc, string asm> { 3696 def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8, 3697 ElementSizeB>; 3698 def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16, 3699 ElementSizeH> { 3700 let Inst{8} = imm{3}; 3701 } 3702 def _S : sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32, 3703 ElementSizeS> { 3704 let Inst{9-8} = imm{4-3}; 3705 } 3706 def _D : sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64, 3707 ElementSizeD> { 3708 let Inst{22} = imm{5}; 3709 let Inst{9-8} = imm{4-3}; 3710 } 3711} 3712 3713class sve_int_bin_pred_shift<bits<2> sz8_64, bit wide, bits<3> opc, 3714 string asm, ZPRRegOp zprty, ZPRRegOp zprty2> 3715: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty2:$Zm), 3716 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", 3717 "", 3718 []>, Sched<[]> { 3719 bits<3> Pg; 3720 bits<5> Zdn; 3721 bits<5> Zm; 3722 let Inst{31-24} = 0b00000100; 3723 let Inst{23-22} = sz8_64; 3724 let Inst{21-20} = 0b01; 3725 let Inst{19} = wide; 3726 let Inst{18-16} = opc; 3727 let Inst{15-13} = 0b100; 3728 let Inst{12-10} = Pg; 3729 let Inst{9-5} = Zm; 3730 let Inst{4-0} = Zdn; 3731 3732 let Constraints = "$Zdn = $_Zdn"; 3733 let DestructiveInstType = Destructive; 3734 let ElementSize = zprty.ElementSize; 3735} 3736 3737multiclass sve_int_bin_pred_shift<bits<3> opc, string asm> { 3738 def _B : sve_int_bin_pred_shift<0b00, 0b0, opc, asm, ZPR8, ZPR8>; 3739 def _H : sve_int_bin_pred_shift<0b01, 0b0, opc, asm, ZPR16, ZPR16>; 3740 def _S : sve_int_bin_pred_shift<0b10, 0b0, opc, asm, ZPR32, ZPR32>; 3741 def _D : sve_int_bin_pred_shift<0b11, 0b0, opc, asm, ZPR64, ZPR64>; 3742} 3743 3744multiclass sve_int_bin_pred_shift_wide<bits<3> opc, string asm> { 3745 def _B : sve_int_bin_pred_shift<0b00, 0b1, opc, asm, ZPR8, ZPR64>; 3746 def _H : sve_int_bin_pred_shift<0b01, 0b1, opc, asm, ZPR16, ZPR64>; 3747 def _S : sve_int_bin_pred_shift<0b10, 0b1, opc, asm, ZPR32, ZPR64>; 3748} 3749 3750//===----------------------------------------------------------------------===// 3751// SVE Shift - Unpredicated Group 3752//===----------------------------------------------------------------------===// 3753 3754class sve_int_bin_cons_shift_wide<bits<2> sz8_64, bits<2> opc, string asm, 3755 ZPRRegOp zprty> 3756: I<(outs zprty:$Zd), (ins zprty:$Zn, ZPR64:$Zm), 3757 asm, "\t$Zd, $Zn, $Zm", 3758 "", 3759 []>, Sched<[]> { 3760 bits<5> Zd; 3761 bits<5> Zm; 3762 bits<5> Zn; 3763 let Inst{31-24} = 0b00000100; 3764 let Inst{23-22} = sz8_64; 3765 let Inst{21} = 0b1; 3766 let Inst{20-16} = Zm; 3767 let Inst{15-12} = 0b1000; 3768 let Inst{11-10} = opc; 3769 let Inst{9-5} = Zn; 3770 let Inst{4-0} = Zd; 3771} 3772 3773multiclass sve_int_bin_cons_shift_wide<bits<2> opc, string asm> { 3774 def _B : sve_int_bin_cons_shift_wide<0b00, opc, asm, ZPR8>; 3775 def _H : sve_int_bin_cons_shift_wide<0b01, opc, asm, ZPR16>; 3776 def _S : sve_int_bin_cons_shift_wide<0b10, opc, asm, ZPR32>; 3777} 3778 3779class sve_int_bin_cons_shift_imm<bits<4> tsz8_64, bits<2> opc, string asm, 3780 ZPRRegOp zprty, Operand immtype> 3781: I<(outs zprty:$Zd), (ins zprty:$Zn, immtype:$imm), 3782 asm, "\t$Zd, $Zn, $imm", 3783 "", []>, Sched<[]> { 3784 bits<5> Zd; 3785 bits<5> Zn; 3786 bits<6> imm; 3787 let Inst{31-24} = 0b00000100; 3788 let Inst{23-22} = tsz8_64{3-2}; 3789 let Inst{21} = 0b1; 3790 let Inst{20-19} = tsz8_64{1-0}; 3791 let Inst{18-16} = imm{2-0}; // imm3 3792 let Inst{15-12} = 0b1001; 3793 let Inst{11-10} = opc; 3794 let Inst{9-5} = Zn; 3795 let Inst{4-0} = Zd; 3796} 3797 3798multiclass sve_int_bin_cons_shift_imm_left<bits<2> opc, string asm> { 3799 def _B : sve_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>; 3800 def _H : sve_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> { 3801 let Inst{19} = imm{3}; 3802 } 3803 def _S : sve_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> { 3804 let Inst{20-19} = imm{4-3}; 3805 } 3806 def _D : sve_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> { 3807 let Inst{22} = imm{5}; 3808 let Inst{20-19} = imm{4-3}; 3809 } 3810} 3811 3812multiclass sve_int_bin_cons_shift_imm_right<bits<2> opc, string asm> { 3813 def _B : sve_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>; 3814 def _H : sve_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> { 3815 let Inst{19} = imm{3}; 3816 } 3817 def _S : sve_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> { 3818 let Inst{20-19} = imm{4-3}; 3819 } 3820 def _D : sve_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> { 3821 let Inst{22} = imm{5}; 3822 let Inst{20-19} = imm{4-3}; 3823 } 3824} 3825//===----------------------------------------------------------------------===// 3826// SVE Memory - Store Group 3827//===----------------------------------------------------------------------===// 3828 3829class sve_mem_cst_si<bits<2> msz, bits<2> esz, string asm, 3830 RegisterOperand VecList> 3831: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 3832 asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]", 3833 "", 3834 []>, Sched<[]> { 3835 bits<3> Pg; 3836 bits<5> Rn; 3837 bits<5> Zt; 3838 bits<4> imm4; 3839 let Inst{31-25} = 0b1110010; 3840 let Inst{24-23} = msz; 3841 let Inst{22-21} = esz; 3842 let Inst{20} = 0; 3843 let Inst{19-16} = imm4; 3844 let Inst{15-13} = 0b111; 3845 let Inst{12-10} = Pg; 3846 let Inst{9-5} = Rn; 3847 let Inst{4-0} = Zt; 3848 3849 let mayStore = 1; 3850} 3851 3852multiclass sve_mem_cst_si<bits<2> msz, bits<2> esz, string asm, 3853 RegisterOperand listty, ZPRRegOp zprty> 3854{ 3855 def NAME : sve_mem_cst_si<msz, esz, asm, listty>; 3856 3857 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $imm4, mul vl]", 3858 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>; 3859 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]", 3860 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>; 3861 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]", 3862 (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; 3863} 3864 3865class sve_mem_est_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList, 3866 string asm, Operand immtype> 3867: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm4), 3868 asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]", 3869 "", 3870 []>, Sched<[]> { 3871 bits<3> Pg; 3872 bits<5> Rn; 3873 bits<5> Zt; 3874 bits<4> imm4; 3875 let Inst{31-25} = 0b1110010; 3876 let Inst{24-23} = sz; 3877 let Inst{22-21} = nregs; 3878 let Inst{20} = 1; 3879 let Inst{19-16} = imm4; 3880 let Inst{15-13} = 0b111; 3881 let Inst{12-10} = Pg; 3882 let Inst{9-5} = Rn; 3883 let Inst{4-0} = Zt; 3884 3885 let mayStore = 1; 3886} 3887 3888multiclass sve_mem_est_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList, 3889 string asm, Operand immtype> { 3890 def NAME : sve_mem_est_si<sz, nregs, VecList, asm, immtype>; 3891 3892 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]", 3893 (!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; 3894} 3895 3896class sve_mem_est_ss<bits<2> sz, bits<2> nregs, RegisterOperand VecList, 3897 string asm, RegisterOperand gprty> 3898: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 3899 asm, "\t$Zt, $Pg, [$Rn, $Rm]", 3900 "", 3901 []>, Sched<[]> { 3902 bits<3> Pg; 3903 bits<5> Rm; 3904 bits<5> Rn; 3905 bits<5> Zt; 3906 let Inst{31-25} = 0b1110010; 3907 let Inst{24-23} = sz; 3908 let Inst{22-21} = nregs; 3909 let Inst{20-16} = Rm; 3910 let Inst{15-13} = 0b011; 3911 let Inst{12-10} = Pg; 3912 let Inst{9-5} = Rn; 3913 let Inst{4-0} = Zt; 3914 3915 let mayStore = 1; 3916} 3917 3918class sve_mem_cst_ss_base<bits<4> dtype, string asm, 3919 RegisterOperand listty, RegisterOperand gprty> 3920: I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 3921 asm, "\t$Zt, $Pg, [$Rn, $Rm]", 3922 "", 3923 []>, Sched<[]> { 3924 bits<3> Pg; 3925 bits<5> Rm; 3926 bits<5> Rn; 3927 bits<5> Zt; 3928 let Inst{31-25} = 0b1110010; 3929 let Inst{24-21} = dtype; 3930 let Inst{20-16} = Rm; 3931 let Inst{15-13} = 0b010; 3932 let Inst{12-10} = Pg; 3933 let Inst{9-5} = Rn; 3934 let Inst{4-0} = Zt; 3935 3936 let mayStore = 1; 3937} 3938 3939multiclass sve_mem_cst_ss<bits<4> dtype, string asm, 3940 RegisterOperand listty, ZPRRegOp zprty, 3941 RegisterOperand gprty> { 3942 def NAME : sve_mem_cst_ss_base<dtype, asm, listty, gprty>; 3943 3944 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Rm]", 3945 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; 3946} 3947 3948class sve_mem_cstnt_si<bits<2> msz, string asm, RegisterOperand VecList> 3949: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 3950 asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]", 3951 "", 3952 []>, Sched<[]> { 3953 bits<3> Pg; 3954 bits<5> Rn; 3955 bits<5> Zt; 3956 bits<4> imm4; 3957 let Inst{31-25} = 0b1110010; 3958 let Inst{24-23} = msz; 3959 let Inst{22-20} = 0b001; 3960 let Inst{19-16} = imm4; 3961 let Inst{15-13} = 0b111; 3962 let Inst{12-10} = Pg; 3963 let Inst{9-5} = Rn; 3964 let Inst{4-0} = Zt; 3965 3966 let mayStore = 1; 3967} 3968 3969multiclass sve_mem_cstnt_si<bits<2> msz, string asm, RegisterOperand listty, 3970 ZPRRegOp zprty> { 3971 def NAME : sve_mem_cstnt_si<msz, asm, listty>; 3972 3973 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]", 3974 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>; 3975 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $imm4, mul vl]", 3976 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>; 3977 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]", 3978 (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; 3979} 3980 3981class sve_mem_cstnt_ss_base<bits<2> msz, string asm, RegisterOperand listty, 3982 RegisterOperand gprty> 3983: I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 3984 asm, "\t$Zt, $Pg, [$Rn, $Rm]", 3985 "", 3986 []>, Sched<[]> { 3987 bits<3> Pg; 3988 bits<5> Rm; 3989 bits<5> Rn; 3990 bits<5> Zt; 3991 let Inst{31-25} = 0b1110010; 3992 let Inst{24-23} = msz; 3993 let Inst{22-21} = 0b00; 3994 let Inst{20-16} = Rm; 3995 let Inst{15-13} = 0b011; 3996 let Inst{12-10} = Pg; 3997 let Inst{9-5} = Rn; 3998 let Inst{4-0} = Zt; 3999 4000 let mayStore = 1; 4001} 4002 4003multiclass sve_mem_cstnt_ss<bits<2> msz, string asm, RegisterOperand listty, 4004 ZPRRegOp zprty, RegisterOperand gprty> { 4005 def NAME : sve_mem_cstnt_ss_base<msz, asm, listty, gprty>; 4006 4007 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Rm]", 4008 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; 4009} 4010 4011class sve2_mem_sstnt_vs_base<bits<3> opc, string asm, 4012 RegisterOperand listty, ZPRRegOp zprty> 4013: I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 4014 asm, "\t$Zt, $Pg, [$Zn, $Rm]", 4015 "", 4016 []>, Sched<[]> { 4017 bits<3> Pg; 4018 bits<5> Rm; 4019 bits<5> Zn; 4020 bits<5> Zt; 4021 let Inst{31-25} = 0b1110010; 4022 let Inst{24-22} = opc; 4023 let Inst{21} = 0b0; 4024 let Inst{20-16} = Rm; 4025 let Inst{15-13} = 0b001; 4026 let Inst{12-10} = Pg; 4027 let Inst{9-5} = Zn; 4028 let Inst{4-0} = Zt; 4029 4030 let mayStore = 1; 4031} 4032 4033multiclass sve2_mem_sstnt_vs<bits<3> opc, string asm, 4034 RegisterOperand listty, ZPRRegOp zprty> { 4035 def _REAL : sve2_mem_sstnt_vs_base<opc, asm, listty, zprty>; 4036 4037 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $Rm]", 4038 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>; 4039 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]", 4040 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 0>; 4041 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]", 4042 (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 1>; 4043} 4044 4045class sve_mem_sst_sv<bits<3> opc, bit xs, bit scaled, string asm, 4046 RegisterOperand VecList, RegisterOperand zprext> 4047: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 4048 asm, "\t$Zt, $Pg, [$Rn, $Zm]", 4049 "", 4050 []>, Sched<[]> { 4051 bits<3> Pg; 4052 bits<5> Rn; 4053 bits<5> Zm; 4054 bits<5> Zt; 4055 let Inst{31-25} = 0b1110010; 4056 let Inst{24-22} = opc; 4057 let Inst{21} = scaled; 4058 let Inst{20-16} = Zm; 4059 let Inst{15} = 0b1; 4060 let Inst{14} = xs; 4061 let Inst{13} = 0; 4062 let Inst{12-10} = Pg; 4063 let Inst{9-5} = Rn; 4064 let Inst{4-0} = Zt; 4065 4066 let mayStore = 1; 4067} 4068 4069multiclass sve_mem_sst_sv_32_scaled<bits<3> opc, string asm, 4070 RegisterOperand listty, 4071 ZPRRegOp zprty, 4072 RegisterOperand sxtw_opnd, 4073 RegisterOperand uxtw_opnd > { 4074 def _UXTW_SCALED : sve_mem_sst_sv<opc, 0, 1, asm, listty, uxtw_opnd>; 4075 def _SXTW_SCALED : sve_mem_sst_sv<opc, 1, 1, asm, listty, sxtw_opnd>; 4076 4077 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]", 4078 (!cast<Instruction>(NAME # _UXTW_SCALED) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>; 4079 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]", 4080 (!cast<Instruction>(NAME # _SXTW_SCALED) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>; 4081} 4082 4083multiclass sve_mem_sst_sv_32_unscaled<bits<3> opc, string asm, 4084 RegisterOperand listty, 4085 ZPRRegOp zprty, 4086 RegisterOperand sxtw_opnd, 4087 RegisterOperand uxtw_opnd> { 4088 def _UXTW : sve_mem_sst_sv<opc, 0, 0, asm, listty, uxtw_opnd>; 4089 def _SXTW : sve_mem_sst_sv<opc, 1, 0, asm, listty, sxtw_opnd>; 4090 4091 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]", 4092 (!cast<Instruction>(NAME # _UXTW) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>; 4093 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]", 4094 (!cast<Instruction>(NAME # _SXTW) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>; 4095} 4096 4097class sve_mem_sst_sv2<bits<2> msz, bit scaled, string asm, 4098 RegisterOperand zprext> 4099: I<(outs), (ins Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 4100 asm, "\t$Zt, $Pg, [$Rn, $Zm]", 4101 "", 4102 []>, Sched<[]> { 4103 bits<3> Pg; 4104 bits<5> Rn; 4105 bits<5> Zm; 4106 bits<5> Zt; 4107 let Inst{31-25} = 0b1110010; 4108 let Inst{24-23} = msz; 4109 let Inst{22} = 0b0; 4110 let Inst{21} = scaled; 4111 let Inst{20-16} = Zm; 4112 let Inst{15-13} = 0b101; 4113 let Inst{12-10} = Pg; 4114 let Inst{9-5} = Rn; 4115 let Inst{4-0} = Zt; 4116 4117 let mayStore = 1; 4118} 4119 4120multiclass sve_mem_sst_sv_64_scaled<bits<2> msz, string asm, 4121 RegisterOperand zprext> { 4122 def "" : sve_mem_sst_sv2<msz, 1, asm, zprext>; 4123 4124 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]", 4125 (!cast<Instruction>(NAME) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>; 4126 4127} 4128 4129multiclass sve_mem_sst_sv_64_unscaled<bits<2> msz, string asm> { 4130 def "" : sve_mem_sst_sv2<msz, 0, asm, ZPR64ExtLSL8>; 4131 4132 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]", 4133 (!cast<Instruction>(NAME) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>; 4134} 4135 4136class sve_mem_sst_vi<bits<3> opc, string asm, ZPRRegOp zprty, 4137 RegisterOperand VecList, Operand imm_ty> 4138: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, zprty:$Zn, imm_ty:$imm5), 4139 asm, "\t$Zt, $Pg, [$Zn, $imm5]", 4140 "", 4141 []>, Sched<[]> { 4142 bits<3> Pg; 4143 bits<5> imm5; 4144 bits<5> Zn; 4145 bits<5> Zt; 4146 let Inst{31-25} = 0b1110010; 4147 let Inst{24-23} = opc{2-1}; 4148 let Inst{22} = 0b1; 4149 let Inst{21} = opc{0}; 4150 let Inst{20-16} = imm5; 4151 let Inst{15-13} = 0b101; 4152 let Inst{12-10} = Pg; 4153 let Inst{9-5} = Zn; 4154 let Inst{4-0} = Zt; 4155 4156 let mayStore = 1; 4157} 4158 4159multiclass sve_mem_sst_vi_ptrs<bits<3> opc, string asm, RegisterOperand listty, 4160 ZPRRegOp zprty, Operand imm_ty> { 4161 def _IMM : sve_mem_sst_vi<opc, asm, zprty, listty, imm_ty>; 4162 4163 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]", 4164 (!cast<Instruction>(NAME # _IMM) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, 0), 0>; 4165 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $imm5]", 4166 (!cast<Instruction>(NAME # _IMM) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, imm_ty:$imm5), 0>; 4167 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]", 4168 (!cast<Instruction>(NAME # _IMM) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, 0), 1>; 4169} 4170 4171class sve_mem_z_spill<string asm> 4172: I<(outs), (ins ZPRAny:$Zt, GPR64sp:$Rn, simm9:$imm9), 4173 asm, "\t$Zt, [$Rn, $imm9, mul vl]", 4174 "", 4175 []>, Sched<[]> { 4176 bits<5> Rn; 4177 bits<5> Zt; 4178 bits<9> imm9; 4179 let Inst{31-22} = 0b1110010110; 4180 let Inst{21-16} = imm9{8-3}; 4181 let Inst{15-13} = 0b010; 4182 let Inst{12-10} = imm9{2-0}; 4183 let Inst{9-5} = Rn; 4184 let Inst{4-0} = Zt; 4185 4186 let mayStore = 1; 4187} 4188 4189multiclass sve_mem_z_spill<string asm> { 4190 def NAME : sve_mem_z_spill<asm>; 4191 4192 def : InstAlias<asm # "\t$Zt, [$Rn]", 4193 (!cast<Instruction>(NAME) ZPRAny:$Zt, GPR64sp:$Rn, 0), 1>; 4194} 4195 4196class sve_mem_p_spill<string asm> 4197: I<(outs), (ins PPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), 4198 asm, "\t$Pt, [$Rn, $imm9, mul vl]", 4199 "", 4200 []>, Sched<[]> { 4201 bits<4> Pt; 4202 bits<5> Rn; 4203 bits<9> imm9; 4204 let Inst{31-22} = 0b1110010110; 4205 let Inst{21-16} = imm9{8-3}; 4206 let Inst{15-13} = 0b000; 4207 let Inst{12-10} = imm9{2-0}; 4208 let Inst{9-5} = Rn; 4209 let Inst{4} = 0b0; 4210 let Inst{3-0} = Pt; 4211 4212 let mayStore = 1; 4213} 4214 4215multiclass sve_mem_p_spill<string asm> { 4216 def NAME : sve_mem_p_spill<asm>; 4217 4218 def : InstAlias<asm # "\t$Pt, [$Rn]", 4219 (!cast<Instruction>(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>; 4220} 4221 4222//===----------------------------------------------------------------------===// 4223// SVE Permute - Predicates Group 4224//===----------------------------------------------------------------------===// 4225 4226class sve_int_perm_bin_perm_pp<bits<3> opc, bits<2> sz8_64, string asm, 4227 PPRRegOp pprty> 4228: I<(outs pprty:$Pd), (ins pprty:$Pn, pprty:$Pm), 4229 asm, "\t$Pd, $Pn, $Pm", 4230 "", 4231 []>, Sched<[]> { 4232 bits<4> Pd; 4233 bits<4> Pm; 4234 bits<4> Pn; 4235 let Inst{31-24} = 0b00000101; 4236 let Inst{23-22} = sz8_64; 4237 let Inst{21-20} = 0b10; 4238 let Inst{19-16} = Pm; 4239 let Inst{15-13} = 0b010; 4240 let Inst{12-10} = opc; 4241 let Inst{9} = 0b0; 4242 let Inst{8-5} = Pn; 4243 let Inst{4} = 0b0; 4244 let Inst{3-0} = Pd; 4245} 4246 4247multiclass sve_int_perm_bin_perm_pp<bits<3> opc, string asm> { 4248 def _B : sve_int_perm_bin_perm_pp<opc, 0b00, asm, PPR8>; 4249 def _H : sve_int_perm_bin_perm_pp<opc, 0b01, asm, PPR16>; 4250 def _S : sve_int_perm_bin_perm_pp<opc, 0b10, asm, PPR32>; 4251 def _D : sve_int_perm_bin_perm_pp<opc, 0b11, asm, PPR64>; 4252} 4253 4254class sve_int_perm_punpk<bit opc, string asm> 4255: I<(outs PPR16:$Pd), (ins PPR8:$Pn), 4256 asm, "\t$Pd, $Pn", 4257 "", 4258 []>, Sched<[]> { 4259 bits<4> Pd; 4260 bits<4> Pn; 4261 let Inst{31-17} = 0b000001010011000; 4262 let Inst{16} = opc; 4263 let Inst{15-9} = 0b0100000; 4264 let Inst{8-5} = Pn; 4265 let Inst{4} = 0b0; 4266 let Inst{3-0} = Pd; 4267} 4268 4269class sve_int_rdffr_pred<bit s, string asm> 4270: I<(outs PPR8:$Pd), (ins PPRAny:$Pg), 4271 asm, "\t$Pd, $Pg/z", 4272 "", 4273 []>, Sched<[]> { 4274 bits<4> Pd; 4275 bits<4> Pg; 4276 let Inst{31-23} = 0b001001010; 4277 let Inst{22} = s; 4278 let Inst{21-9} = 0b0110001111000; 4279 let Inst{8-5} = Pg; 4280 let Inst{4} = 0; 4281 let Inst{3-0} = Pd; 4282 4283 let Defs = !if(!eq (s, 1), [NZCV], []); 4284 let Uses = [FFR]; 4285} 4286 4287class sve_int_rdffr_unpred<string asm> : I< 4288 (outs PPR8:$Pd), (ins), 4289 asm, "\t$Pd", 4290 "", 4291 []>, Sched<[]> { 4292 bits<4> Pd; 4293 let Inst{31-4} = 0b0010010100011001111100000000; 4294 let Inst{3-0} = Pd; 4295 4296 let Uses = [FFR]; 4297} 4298 4299class sve_int_wrffr<string asm> 4300: I<(outs), (ins PPR8:$Pn), 4301 asm, "\t$Pn", 4302 "", 4303 []>, Sched<[]> { 4304 bits<4> Pn; 4305 let Inst{31-9} = 0b00100101001010001001000; 4306 let Inst{8-5} = Pn; 4307 let Inst{4-0} = 0b00000; 4308 4309 let hasSideEffects = 1; 4310 let Defs = [FFR]; 4311} 4312 4313class sve_int_setffr<string asm> 4314: I<(outs), (ins), 4315 asm, "", 4316 "", 4317 []>, Sched<[]> { 4318 let Inst{31-0} = 0b00100101001011001001000000000000; 4319 4320 let hasSideEffects = 1; 4321 let Defs = [FFR]; 4322} 4323 4324//===----------------------------------------------------------------------===// 4325// SVE Permute Vector - Predicated Group 4326//===----------------------------------------------------------------------===// 4327 4328class sve_int_perm_clast_rz<bits<2> sz8_64, bit ab, string asm, 4329 ZPRRegOp zprty, RegisterClass rt> 4330: I<(outs rt:$Rdn), (ins PPR3bAny:$Pg, rt:$_Rdn, zprty:$Zm), 4331 asm, "\t$Rdn, $Pg, $_Rdn, $Zm", 4332 "", 4333 []>, Sched<[]> { 4334 bits<3> Pg; 4335 bits<5> Rdn; 4336 bits<5> Zm; 4337 let Inst{31-24} = 0b00000101; 4338 let Inst{23-22} = sz8_64; 4339 let Inst{21-17} = 0b11000; 4340 let Inst{16} = ab; 4341 let Inst{15-13} = 0b101; 4342 let Inst{12-10} = Pg; 4343 let Inst{9-5} = Zm; 4344 let Inst{4-0} = Rdn; 4345 4346 let Constraints = "$Rdn = $_Rdn"; 4347} 4348 4349multiclass sve_int_perm_clast_rz<bit ab, string asm> { 4350 def _B : sve_int_perm_clast_rz<0b00, ab, asm, ZPR8, GPR32>; 4351 def _H : sve_int_perm_clast_rz<0b01, ab, asm, ZPR16, GPR32>; 4352 def _S : sve_int_perm_clast_rz<0b10, ab, asm, ZPR32, GPR32>; 4353 def _D : sve_int_perm_clast_rz<0b11, ab, asm, ZPR64, GPR64>; 4354} 4355 4356class sve_int_perm_clast_vz<bits<2> sz8_64, bit ab, string asm, 4357 ZPRRegOp zprty, RegisterClass rt> 4358: I<(outs rt:$Vdn), (ins PPR3bAny:$Pg, rt:$_Vdn, zprty:$Zm), 4359 asm, "\t$Vdn, $Pg, $_Vdn, $Zm", 4360 "", 4361 []>, Sched<[]> { 4362 bits<3> Pg; 4363 bits<5> Vdn; 4364 bits<5> Zm; 4365 let Inst{31-24} = 0b00000101; 4366 let Inst{23-22} = sz8_64; 4367 let Inst{21-17} = 0b10101; 4368 let Inst{16} = ab; 4369 let Inst{15-13} = 0b100; 4370 let Inst{12-10} = Pg; 4371 let Inst{9-5} = Zm; 4372 let Inst{4-0} = Vdn; 4373 4374 let Constraints = "$Vdn = $_Vdn"; 4375} 4376 4377multiclass sve_int_perm_clast_vz<bit ab, string asm> { 4378 def _B : sve_int_perm_clast_vz<0b00, ab, asm, ZPR8, FPR8>; 4379 def _H : sve_int_perm_clast_vz<0b01, ab, asm, ZPR16, FPR16>; 4380 def _S : sve_int_perm_clast_vz<0b10, ab, asm, ZPR32, FPR32>; 4381 def _D : sve_int_perm_clast_vz<0b11, ab, asm, ZPR64, FPR64>; 4382} 4383 4384class sve_int_perm_clast_zz<bits<2> sz8_64, bit ab, string asm, 4385 ZPRRegOp zprty> 4386: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), 4387 asm, "\t$Zdn, $Pg, $_Zdn, $Zm", 4388 "", 4389 []>, Sched<[]> { 4390 bits<3> Pg; 4391 bits<5> Zdn; 4392 bits<5> Zm; 4393 let Inst{31-24} = 0b00000101; 4394 let Inst{23-22} = sz8_64; 4395 let Inst{21-17} = 0b10100; 4396 let Inst{16} = ab; 4397 let Inst{15-13} = 0b100; 4398 let Inst{12-10} = Pg; 4399 let Inst{9-5} = Zm; 4400 let Inst{4-0} = Zdn; 4401 4402 let Constraints = "$Zdn = $_Zdn"; 4403 let DestructiveInstType = Destructive; 4404 let ElementSize = ElementSizeNone; 4405} 4406 4407multiclass sve_int_perm_clast_zz<bit ab, string asm> { 4408 def _B : sve_int_perm_clast_zz<0b00, ab, asm, ZPR8>; 4409 def _H : sve_int_perm_clast_zz<0b01, ab, asm, ZPR16>; 4410 def _S : sve_int_perm_clast_zz<0b10, ab, asm, ZPR32>; 4411 def _D : sve_int_perm_clast_zz<0b11, ab, asm, ZPR64>; 4412} 4413 4414class sve_int_perm_last_r<bits<2> sz8_64, bit ab, string asm, 4415 ZPRRegOp zprty, RegisterClass resultRegType> 4416: I<(outs resultRegType:$Rd), (ins PPR3bAny:$Pg, zprty:$Zn), 4417 asm, "\t$Rd, $Pg, $Zn", 4418 "", 4419 []>, Sched<[]> { 4420 bits<3> Pg; 4421 bits<5> Rd; 4422 bits<5> Zn; 4423 let Inst{31-24} = 0b00000101; 4424 let Inst{23-22} = sz8_64; 4425 let Inst{21-17} = 0b10000; 4426 let Inst{16} = ab; 4427 let Inst{15-13} = 0b101; 4428 let Inst{12-10} = Pg; 4429 let Inst{9-5} = Zn; 4430 let Inst{4-0} = Rd; 4431} 4432 4433multiclass sve_int_perm_last_r<bit ab, string asm> { 4434 def _B : sve_int_perm_last_r<0b00, ab, asm, ZPR8, GPR32>; 4435 def _H : sve_int_perm_last_r<0b01, ab, asm, ZPR16, GPR32>; 4436 def _S : sve_int_perm_last_r<0b10, ab, asm, ZPR32, GPR32>; 4437 def _D : sve_int_perm_last_r<0b11, ab, asm, ZPR64, GPR64>; 4438} 4439 4440class sve_int_perm_last_v<bits<2> sz8_64, bit ab, string asm, 4441 ZPRRegOp zprty, RegisterClass dstRegtype> 4442: I<(outs dstRegtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn), 4443 asm, "\t$Vd, $Pg, $Zn", 4444 "", 4445 []>, Sched<[]> { 4446 bits<3> Pg; 4447 bits<5> Vd; 4448 bits<5> Zn; 4449 let Inst{31-24} = 0b00000101; 4450 let Inst{23-22} = sz8_64; 4451 let Inst{21-17} = 0b10001; 4452 let Inst{16} = ab; 4453 let Inst{15-13} = 0b100; 4454 let Inst{12-10} = Pg; 4455 let Inst{9-5} = Zn; 4456 let Inst{4-0} = Vd; 4457} 4458 4459multiclass sve_int_perm_last_v<bit ab, string asm> { 4460 def _B : sve_int_perm_last_v<0b00, ab, asm, ZPR8, FPR8>; 4461 def _H : sve_int_perm_last_v<0b01, ab, asm, ZPR16, FPR16>; 4462 def _S : sve_int_perm_last_v<0b10, ab, asm, ZPR32, FPR32>; 4463 def _D : sve_int_perm_last_v<0b11, ab, asm, ZPR64, FPR64>; 4464} 4465 4466class sve_int_perm_splice<bits<2> sz8_64, string asm, ZPRRegOp zprty> 4467: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), 4468 asm, "\t$Zdn, $Pg, $_Zdn, $Zm", 4469 "", 4470 []>, Sched<[]> { 4471 bits<3> Pg; 4472 bits<5> Zdn; 4473 bits<5> Zm; 4474 let Inst{31-24} = 0b00000101; 4475 let Inst{23-22} = sz8_64; 4476 let Inst{21-13} = 0b101100100; 4477 let Inst{12-10} = Pg; 4478 let Inst{9-5} = Zm; 4479 let Inst{4-0} = Zdn; 4480 4481 let Constraints = "$Zdn = $_Zdn"; 4482 let DestructiveInstType = Destructive; 4483 let ElementSize = ElementSizeNone; 4484} 4485 4486multiclass sve_int_perm_splice<string asm> { 4487 def _B : sve_int_perm_splice<0b00, asm, ZPR8>; 4488 def _H : sve_int_perm_splice<0b01, asm, ZPR16>; 4489 def _S : sve_int_perm_splice<0b10, asm, ZPR32>; 4490 def _D : sve_int_perm_splice<0b11, asm, ZPR64>; 4491} 4492 4493class sve2_int_perm_splice_cons<bits<2> sz8_64, string asm, 4494 ZPRRegOp zprty, RegisterOperand VecList> 4495: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, VecList:$Zn), 4496 asm, "\t$Zd, $Pg, $Zn", 4497 "", 4498 []>, Sched<[]> { 4499 bits<3> Pg; 4500 bits<5> Zn; 4501 bits<5> Zd; 4502 let Inst{31-24} = 0b00000101; 4503 let Inst{23-22} = sz8_64; 4504 let Inst{21-13} = 0b101101100; 4505 let Inst{12-10} = Pg; 4506 let Inst{9-5} = Zn; 4507 let Inst{4-0} = Zd; 4508} 4509 4510multiclass sve2_int_perm_splice_cons<string asm> { 4511 def _B : sve2_int_perm_splice_cons<0b00, asm, ZPR8, ZZ_b>; 4512 def _H : sve2_int_perm_splice_cons<0b01, asm, ZPR16, ZZ_h>; 4513 def _S : sve2_int_perm_splice_cons<0b10, asm, ZPR32, ZZ_s>; 4514 def _D : sve2_int_perm_splice_cons<0b11, asm, ZPR64, ZZ_d>; 4515} 4516 4517class sve_int_perm_rev<bits<2> sz8_64, bits<2> opc, string asm, 4518 ZPRRegOp zprty> 4519: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn), 4520 asm, "\t$Zd, $Pg/m, $Zn", 4521 "", 4522 []>, Sched<[]> { 4523 bits<5> Zd; 4524 bits<3> Pg; 4525 bits<5> Zn; 4526 let Inst{31-24} = 0b00000101; 4527 let Inst{23-22} = sz8_64; 4528 let Inst{21-18} = 0b1001; 4529 let Inst{17-16} = opc; 4530 let Inst{15-13} = 0b100; 4531 let Inst{12-10} = Pg; 4532 let Inst{9-5} = Zn; 4533 let Inst{4-0} = Zd; 4534 4535 let Constraints = "$Zd = $_Zd"; 4536 let DestructiveInstType = Destructive; 4537 let ElementSize = zprty.ElementSize; 4538} 4539 4540multiclass sve_int_perm_rev_rbit<string asm> { 4541 def _B : sve_int_perm_rev<0b00, 0b11, asm, ZPR8>; 4542 def _H : sve_int_perm_rev<0b01, 0b11, asm, ZPR16>; 4543 def _S : sve_int_perm_rev<0b10, 0b11, asm, ZPR32>; 4544 def _D : sve_int_perm_rev<0b11, 0b11, asm, ZPR64>; 4545} 4546 4547multiclass sve_int_perm_rev_revb<string asm> { 4548 def _H : sve_int_perm_rev<0b01, 0b00, asm, ZPR16>; 4549 def _S : sve_int_perm_rev<0b10, 0b00, asm, ZPR32>; 4550 def _D : sve_int_perm_rev<0b11, 0b00, asm, ZPR64>; 4551} 4552 4553multiclass sve_int_perm_rev_revh<string asm> { 4554 def _S : sve_int_perm_rev<0b10, 0b01, asm, ZPR32>; 4555 def _D : sve_int_perm_rev<0b11, 0b01, asm, ZPR64>; 4556} 4557 4558multiclass sve_int_perm_rev_revw<string asm> { 4559 def _D : sve_int_perm_rev<0b11, 0b10, asm, ZPR64>; 4560} 4561 4562class sve_int_perm_cpy_r<bits<2> sz8_64, string asm, ZPRRegOp zprty, 4563 RegisterClass srcRegType> 4564: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegType:$Rn), 4565 asm, "\t$Zd, $Pg/m, $Rn", 4566 "", 4567 []>, Sched<[]> { 4568 bits<3> Pg; 4569 bits<5> Rn; 4570 bits<5> Zd; 4571 let Inst{31-24} = 0b00000101; 4572 let Inst{23-22} = sz8_64; 4573 let Inst{21-13} = 0b101000101; 4574 let Inst{12-10} = Pg; 4575 let Inst{9-5} = Rn; 4576 let Inst{4-0} = Zd; 4577 4578 let Constraints = "$Zd = $_Zd"; 4579 let DestructiveInstType = Destructive; 4580 let ElementSize = zprty.ElementSize; 4581} 4582 4583multiclass sve_int_perm_cpy_r<string asm> { 4584 def _B : sve_int_perm_cpy_r<0b00, asm, ZPR8, GPR32sp>; 4585 def _H : sve_int_perm_cpy_r<0b01, asm, ZPR16, GPR32sp>; 4586 def _S : sve_int_perm_cpy_r<0b10, asm, ZPR32, GPR32sp>; 4587 def _D : sve_int_perm_cpy_r<0b11, asm, ZPR64, GPR64sp>; 4588 4589 def : InstAlias<"mov $Zd, $Pg/m, $Rn", 4590 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>; 4591 def : InstAlias<"mov $Zd, $Pg/m, $Rn", 4592 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>; 4593 def : InstAlias<"mov $Zd, $Pg/m, $Rn", 4594 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>; 4595 def : InstAlias<"mov $Zd, $Pg/m, $Rn", 4596 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn), 1>; 4597} 4598 4599class sve_int_perm_cpy_v<bits<2> sz8_64, string asm, ZPRRegOp zprty, 4600 RegisterClass srcRegtype> 4601: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegtype:$Vn), 4602 asm, "\t$Zd, $Pg/m, $Vn", 4603 "", 4604 []>, Sched<[]> { 4605 bits<3> Pg; 4606 bits<5> Vn; 4607 bits<5> Zd; 4608 let Inst{31-24} = 0b00000101; 4609 let Inst{23-22} = sz8_64; 4610 let Inst{21-13} = 0b100000100; 4611 let Inst{12-10} = Pg; 4612 let Inst{9-5} = Vn; 4613 let Inst{4-0} = Zd; 4614 4615 let Constraints = "$Zd = $_Zd"; 4616 let DestructiveInstType = Destructive; 4617 let ElementSize = zprty.ElementSize; 4618} 4619 4620multiclass sve_int_perm_cpy_v<string asm> { 4621 def _B : sve_int_perm_cpy_v<0b00, asm, ZPR8, FPR8>; 4622 def _H : sve_int_perm_cpy_v<0b01, asm, ZPR16, FPR16>; 4623 def _S : sve_int_perm_cpy_v<0b10, asm, ZPR32, FPR32>; 4624 def _D : sve_int_perm_cpy_v<0b11, asm, ZPR64, FPR64>; 4625 4626 def : InstAlias<"mov $Zd, $Pg/m, $Vn", 4627 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn), 1>; 4628 def : InstAlias<"mov $Zd, $Pg/m, $Vn", 4629 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn), 1>; 4630 def : InstAlias<"mov $Zd, $Pg/m, $Vn", 4631 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn), 1>; 4632 def : InstAlias<"mov $Zd, $Pg/m, $Vn", 4633 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn), 1>; 4634} 4635 4636class sve_int_perm_compact<bit sz, string asm, ZPRRegOp zprty> 4637: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn), 4638 asm, "\t$Zd, $Pg, $Zn", 4639 "", 4640 []>, Sched<[]> { 4641 bits<3> Pg; 4642 bits<5> Zd; 4643 bits<5> Zn; 4644 let Inst{31-23} = 0b000001011; 4645 let Inst{22} = sz; 4646 let Inst{21-13} = 0b100001100; 4647 let Inst{12-10} = Pg; 4648 let Inst{9-5} = Zn; 4649 let Inst{4-0} = Zd; 4650} 4651 4652multiclass sve_int_perm_compact<string asm> { 4653 def _S : sve_int_perm_compact<0b0, asm, ZPR32>; 4654 def _D : sve_int_perm_compact<0b1, asm, ZPR64>; 4655} 4656 4657 4658//===----------------------------------------------------------------------===// 4659// SVE Memory - Contiguous Load Group 4660//===----------------------------------------------------------------------===// 4661 4662class sve_mem_cld_si_base<bits<4> dtype, bit nf, string asm, 4663 RegisterOperand VecList> 4664: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 4665 asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]", 4666 "", 4667 []>, Sched<[]> { 4668 bits<3> Pg; 4669 bits<5> Rn; 4670 bits<5> Zt; 4671 bits<4> imm4; 4672 let Inst{31-25} = 0b1010010; 4673 let Inst{24-21} = dtype; 4674 let Inst{20} = nf; 4675 let Inst{19-16} = imm4; 4676 let Inst{15-13} = 0b101; 4677 let Inst{12-10} = Pg; 4678 let Inst{9-5} = Rn; 4679 let Inst{4-0} = Zt; 4680 4681 let mayLoad = 1; 4682 let Uses = !if(!eq(nf, 1), [FFR], []); 4683 let Defs = !if(!eq(nf, 1), [FFR], []); 4684} 4685 4686multiclass sve_mem_cld_si_base<bits<4> dtype, bit nf, string asm, 4687 RegisterOperand listty, ZPRRegOp zprty> { 4688 def _REAL : sve_mem_cld_si_base<dtype, nf, asm, listty>; 4689 4690 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]", 4691 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>; 4692 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]", 4693 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>; 4694 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]", 4695 (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; 4696} 4697 4698multiclass sve_mem_cld_si<bits<4> dtype, string asm, RegisterOperand listty, 4699 ZPRRegOp zprty> 4700: sve_mem_cld_si_base<dtype, 0, asm, listty, zprty>; 4701 4702class sve_mem_cldnt_si_base<bits<2> msz, string asm, RegisterOperand VecList> 4703: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 4704 asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]", 4705 "", 4706 []>, Sched<[]> { 4707 bits<5> Zt; 4708 bits<3> Pg; 4709 bits<5> Rn; 4710 bits<4> imm4; 4711 let Inst{31-25} = 0b1010010; 4712 let Inst{24-23} = msz; 4713 let Inst{22-20} = 0b000; 4714 let Inst{19-16} = imm4; 4715 let Inst{15-13} = 0b111; 4716 let Inst{12-10} = Pg; 4717 let Inst{9-5} = Rn; 4718 let Inst{4-0} = Zt; 4719 4720 let mayLoad = 1; 4721} 4722 4723multiclass sve_mem_cldnt_si<bits<2> msz, string asm, RegisterOperand listty, 4724 ZPRRegOp zprty> { 4725 def NAME : sve_mem_cldnt_si_base<msz, asm, listty>; 4726 4727 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]", 4728 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>; 4729 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]", 4730 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>; 4731 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]", 4732 (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; 4733} 4734 4735class sve_mem_cldnt_ss_base<bits<2> msz, string asm, RegisterOperand VecList, 4736 RegisterOperand gprty> 4737: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 4738 asm, "\t$Zt, $Pg/z, [$Rn, $Rm]", 4739 "", 4740 []>, Sched<[]> { 4741 bits<3> Pg; 4742 bits<5> Rm; 4743 bits<5> Rn; 4744 bits<5> Zt; 4745 let Inst{31-25} = 0b1010010; 4746 let Inst{24-23} = msz; 4747 let Inst{22-21} = 0b00; 4748 let Inst{20-16} = Rm; 4749 let Inst{15-13} = 0b110; 4750 let Inst{12-10} = Pg; 4751 let Inst{9-5} = Rn; 4752 let Inst{4-0} = Zt; 4753 4754 let mayLoad = 1; 4755} 4756 4757multiclass sve_mem_cldnt_ss<bits<2> msz, string asm, RegisterOperand listty, 4758 ZPRRegOp zprty, RegisterOperand gprty> { 4759 def NAME : sve_mem_cldnt_ss_base<msz, asm, listty, gprty>; 4760 4761 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]", 4762 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; 4763} 4764 4765class sve_mem_ldqr_si<bits<2> sz, string asm, RegisterOperand VecList> 4766: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s16:$imm4), 4767 asm, "\t$Zt, $Pg/z, [$Rn, $imm4]", "", []>, Sched<[]> { 4768 bits<5> Zt; 4769 bits<5> Rn; 4770 bits<3> Pg; 4771 bits<4> imm4; 4772 let Inst{31-25} = 0b1010010; 4773 let Inst{24-23} = sz; 4774 let Inst{22-20} = 0; 4775 let Inst{19-16} = imm4; 4776 let Inst{15-13} = 0b001; 4777 let Inst{12-10} = Pg; 4778 let Inst{9-5} = Rn; 4779 let Inst{4-0} = Zt; 4780 4781 let mayLoad = 1; 4782} 4783 4784multiclass sve_mem_ldqr_si<bits<2> sz, string asm, RegisterOperand listty, 4785 ZPRRegOp zprty> { 4786 def NAME : sve_mem_ldqr_si<sz, asm, listty>; 4787 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]", 4788 (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; 4789 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]", 4790 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>; 4791 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4]", 4792 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s16:$imm4), 0>; 4793} 4794 4795class sve_mem_ldqr_ss<bits<2> sz, string asm, RegisterOperand VecList, 4796 RegisterOperand gprty> 4797: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 4798 asm, "\t$Zt, $Pg/z, [$Rn, $Rm]", "", []>, Sched<[]> { 4799 bits<5> Zt; 4800 bits<3> Pg; 4801 bits<5> Rn; 4802 bits<5> Rm; 4803 let Inst{31-25} = 0b1010010; 4804 let Inst{24-23} = sz; 4805 let Inst{22-21} = 0; 4806 let Inst{20-16} = Rm; 4807 let Inst{15-13} = 0; 4808 let Inst{12-10} = Pg; 4809 let Inst{9-5} = Rn; 4810 let Inst{4-0} = Zt; 4811 4812 let mayLoad = 1; 4813} 4814 4815multiclass sve_mem_ldqr_ss<bits<2> sz, string asm, RegisterOperand listty, 4816 ZPRRegOp zprty, RegisterOperand gprty> { 4817 def NAME : sve_mem_ldqr_ss<sz, asm, listty, gprty>; 4818 4819 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]", 4820 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; 4821} 4822 4823class sve_mem_ld_dup<bits<2> dtypeh, bits<2> dtypel, string asm, 4824 RegisterOperand VecList, Operand immtype> 4825: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm6), 4826 asm, "\t$Zt, $Pg/z, [$Rn, $imm6]", 4827 "", 4828 []>, Sched<[]> { 4829 bits<3> Pg; 4830 bits<5> Rn; 4831 bits<5> Zt; 4832 bits<6> imm6; 4833 let Inst{31-25} = 0b1000010; 4834 let Inst{24-23} = dtypeh; 4835 let Inst{22} = 1; 4836 let Inst{21-16} = imm6; 4837 let Inst{15} = 0b1; 4838 let Inst{14-13} = dtypel; 4839 let Inst{12-10} = Pg; 4840 let Inst{9-5} = Rn; 4841 let Inst{4-0} = Zt; 4842 4843 let mayLoad = 1; 4844} 4845 4846multiclass sve_mem_ld_dup<bits<2> dtypeh, bits<2> dtypel, string asm, 4847 RegisterOperand zlistty, ZPRRegOp zprty, Operand immtype> { 4848 def NAME : sve_mem_ld_dup<dtypeh, dtypel, asm, zlistty, immtype>; 4849 4850 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]", 4851 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>; 4852 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm6]", 4853 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm6), 0>; 4854 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]", 4855 (!cast<Instruction>(NAME) zlistty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; 4856} 4857 4858class sve_mem_cld_ss_base<bits<4> dtype, bit ff, dag iops, string asm, 4859 RegisterOperand VecList> 4860: I<(outs VecList:$Zt), iops, 4861 asm, "\t$Zt, $Pg/z, [$Rn, $Rm]", 4862 "", 4863 []>, Sched<[]> { 4864 bits<5> Zt; 4865 bits<3> Pg; 4866 bits<5> Rm; 4867 bits<5> Rn; 4868 let Inst{31-25} = 0b1010010; 4869 let Inst{24-21} = dtype; 4870 let Inst{20-16} = Rm; 4871 let Inst{15-14} = 0b01; 4872 let Inst{13} = ff; 4873 let Inst{12-10} = Pg; 4874 let Inst{9-5} = Rn; 4875 let Inst{4-0} = Zt; 4876 4877 let mayLoad = 1; 4878 let Uses = !if(!eq(ff, 1), [FFR], []); 4879 let Defs = !if(!eq(ff, 1), [FFR], []); 4880} 4881 4882multiclass sve_mem_cld_ss<bits<4> dtype, string asm, RegisterOperand listty, 4883 ZPRRegOp zprty, RegisterOperand gprty> { 4884 def "" : sve_mem_cld_ss_base<dtype, 0, (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 4885 asm, listty>; 4886 4887 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]", 4888 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; 4889} 4890 4891multiclass sve_mem_cldff_ss<bits<4> dtype, string asm, RegisterOperand listty, 4892 ZPRRegOp zprty, RegisterOperand gprty> { 4893 def _REAL : sve_mem_cld_ss_base<dtype, 1, (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 4894 asm, listty>; 4895 4896 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]", 4897 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; 4898 4899 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]", 4900 (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 1>; 4901 4902 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]", 4903 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 0>; 4904} 4905 4906multiclass sve_mem_cldnf_si<bits<4> dtype, string asm, RegisterOperand listty, 4907 ZPRRegOp zprty> 4908: sve_mem_cld_si_base<dtype, 1, asm, listty, zprty>; 4909 4910class sve_mem_eld_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList, 4911 string asm, Operand immtype> 4912: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm4), 4913 asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]", 4914 "", 4915 []>, Sched<[]> { 4916 bits<5> Zt; 4917 bits<3> Pg; 4918 bits<5> Rn; 4919 bits<4> imm4; 4920 let Inst{31-25} = 0b1010010; 4921 let Inst{24-23} = sz; 4922 let Inst{22-21} = nregs; 4923 let Inst{20} = 0; 4924 let Inst{19-16} = imm4; 4925 let Inst{15-13} = 0b111; 4926 let Inst{12-10} = Pg; 4927 let Inst{9-5} = Rn; 4928 let Inst{4-0} = Zt; 4929 4930 let mayLoad = 1; 4931} 4932 4933multiclass sve_mem_eld_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList, 4934 string asm, Operand immtype> { 4935 def NAME : sve_mem_eld_si<sz, nregs, VecList, asm, immtype>; 4936 4937 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]", 4938 (!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; 4939} 4940 4941class sve_mem_eld_ss<bits<2> sz, bits<2> nregs, RegisterOperand VecList, 4942 string asm, RegisterOperand gprty> 4943: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 4944 asm, "\t$Zt, $Pg/z, [$Rn, $Rm]", 4945 "", 4946 []>, Sched<[]> { 4947 bits<3> Pg; 4948 bits<5> Rm; 4949 bits<5> Rn; 4950 bits<5> Zt; 4951 let Inst{31-25} = 0b1010010; 4952 let Inst{24-23} = sz; 4953 let Inst{22-21} = nregs; 4954 let Inst{20-16} = Rm; 4955 let Inst{15-13} = 0b110; 4956 let Inst{12-10} = Pg; 4957 let Inst{9-5} = Rn; 4958 let Inst{4-0} = Zt; 4959 4960 let mayLoad = 1; 4961} 4962 4963//===----------------------------------------------------------------------===// 4964// SVE Memory - 32-bit Gather and Unsized Contiguous Group 4965//===----------------------------------------------------------------------===// 4966 4967// bit xs is '1' if offsets are signed 4968// bit scaled is '1' if the offsets are scaled 4969class sve_mem_32b_gld_sv<bits<4> opc, bit xs, bit scaled, string asm, 4970 RegisterOperand zprext> 4971: I<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 4972 asm, "\t$Zt, $Pg/z, [$Rn, $Zm]", 4973 "", 4974 []>, Sched<[]> { 4975 bits<3> Pg; 4976 bits<5> Rn; 4977 bits<5> Zm; 4978 bits<5> Zt; 4979 let Inst{31-25} = 0b1000010; 4980 let Inst{24-23} = opc{3-2}; 4981 let Inst{22} = xs; 4982 let Inst{21} = scaled; 4983 let Inst{20-16} = Zm; 4984 let Inst{15} = 0b0; 4985 let Inst{14-13} = opc{1-0}; 4986 let Inst{12-10} = Pg; 4987 let Inst{9-5} = Rn; 4988 let Inst{4-0} = Zt; 4989 4990 let mayLoad = 1; 4991 let Defs = !if(!eq(opc{0}, 1), [FFR], []); 4992 let Uses = !if(!eq(opc{0}, 1), [FFR], []); 4993} 4994 4995multiclass sve_mem_32b_gld_sv_32_scaled<bits<4> opc, string asm, 4996 RegisterOperand sxtw_opnd, 4997 RegisterOperand uxtw_opnd> { 4998 def _UXTW_SCALED_REAL : sve_mem_32b_gld_sv<opc, 0, 1, asm, uxtw_opnd>; 4999 def _SXTW_SCALED_REAL : sve_mem_32b_gld_sv<opc, 1, 1, asm, sxtw_opnd>; 5000 5001 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]", 5002 (!cast<Instruction>(NAME # _UXTW_SCALED_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>; 5003 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]", 5004 (!cast<Instruction>(NAME # _SXTW_SCALED_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>; 5005} 5006 5007multiclass sve_mem_32b_gld_vs_32_unscaled<bits<4> opc, string asm, 5008 RegisterOperand sxtw_opnd, 5009 RegisterOperand uxtw_opnd> { 5010 def _UXTW_REAL : sve_mem_32b_gld_sv<opc, 0, 0, asm, uxtw_opnd>; 5011 def _SXTW_REAL : sve_mem_32b_gld_sv<opc, 1, 0, asm, sxtw_opnd>; 5012 5013 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]", 5014 (!cast<Instruction>(NAME # _UXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>; 5015 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]", 5016 (!cast<Instruction>(NAME # _SXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>; 5017} 5018 5019 5020class sve_mem_32b_gld_vi<bits<4> opc, string asm, Operand imm_ty> 5021: I<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5), 5022 asm, "\t$Zt, $Pg/z, [$Zn, $imm5]", 5023 "", 5024 []>, Sched<[]> { 5025 bits<3> Pg; 5026 bits<5> Zn; 5027 bits<5> Zt; 5028 bits<5> imm5; 5029 let Inst{31-25} = 0b1000010; 5030 let Inst{24-23} = opc{3-2}; 5031 let Inst{22-21} = 0b01; 5032 let Inst{20-16} = imm5; 5033 let Inst{15} = 0b1; 5034 let Inst{14-13} = opc{1-0}; 5035 let Inst{12-10} = Pg; 5036 let Inst{9-5} = Zn; 5037 let Inst{4-0} = Zt; 5038 5039 let mayLoad = 1; 5040 let Defs = !if(!eq(opc{0}, 1), [FFR], []); 5041 let Uses = !if(!eq(opc{0}, 1), [FFR], []); 5042} 5043 5044multiclass sve_mem_32b_gld_vi_32_ptrs<bits<4> opc, string asm, Operand imm_ty> { 5045 def _IMM_REAL : sve_mem_32b_gld_vi<opc, asm, imm_ty>; 5046 5047 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]", 5048 (!cast<Instruction>(NAME # _IMM_REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 0>; 5049 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $imm5]", 5050 (!cast<Instruction>(NAME # _IMM_REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5), 0>; 5051 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]", 5052 (!cast<Instruction>(NAME # _IMM_REAL) Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>; 5053} 5054 5055class sve_mem_prfm_si<bits<2> msz, string asm> 5056: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, simm6s1:$imm6), 5057 asm, "\t$prfop, $Pg, [$Rn, $imm6, mul vl]", 5058 "", 5059 []>, Sched<[]> { 5060 bits<5> Rn; 5061 bits<3> Pg; 5062 bits<6> imm6; 5063 bits<4> prfop; 5064 let Inst{31-22} = 0b1000010111; 5065 let Inst{21-16} = imm6; 5066 let Inst{15} = 0b0; 5067 let Inst{14-13} = msz; 5068 let Inst{12-10} = Pg; 5069 let Inst{9-5} = Rn; 5070 let Inst{4} = 0b0; 5071 let Inst{3-0} = prfop; 5072 5073 let hasSideEffects = 1; 5074} 5075 5076multiclass sve_mem_prfm_si<bits<2> msz, string asm> { 5077 def NAME : sve_mem_prfm_si<msz, asm>; 5078 5079 def : InstAlias<asm # "\t$prfop, $Pg, [$Rn]", 5080 (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; 5081} 5082 5083class sve_mem_prfm_ss<bits<3> opc, string asm, RegisterOperand gprty> 5084: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 5085 asm, "\t$prfop, $Pg, [$Rn, $Rm]", 5086 "", 5087 []>, Sched<[]> { 5088 bits<5> Rm; 5089 bits<5> Rn; 5090 bits<3> Pg; 5091 bits<4> prfop; 5092 let Inst{31-25} = 0b1000010; 5093 let Inst{24-23} = opc{2-1}; 5094 let Inst{22-21} = 0b00; 5095 let Inst{20-16} = Rm; 5096 let Inst{15} = 0b1; 5097 let Inst{14} = opc{0}; 5098 let Inst{13} = 0b0; 5099 let Inst{12-10} = Pg; 5100 let Inst{9-5} = Rn; 5101 let Inst{4} = 0b0; 5102 let Inst{3-0} = prfop; 5103 5104 let hasSideEffects = 1; 5105} 5106 5107class sve_mem_32b_prfm_sv<bits<2> msz, bit xs, string asm, 5108 RegisterOperand zprext> 5109: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 5110 asm, "\t$prfop, $Pg, [$Rn, $Zm]", 5111 "", 5112 []>, Sched<[]> { 5113 bits<3> Pg; 5114 bits<5> Rn; 5115 bits<5> Zm; 5116 bits<4> prfop; 5117 let Inst{31-23} = 0b100001000; 5118 let Inst{22} = xs; 5119 let Inst{21} = 0b1; 5120 let Inst{20-16} = Zm; 5121 let Inst{15} = 0b0; 5122 let Inst{14-13} = msz; 5123 let Inst{12-10} = Pg; 5124 let Inst{9-5} = Rn; 5125 let Inst{4} = 0b0; 5126 let Inst{3-0} = prfop; 5127 5128 let hasSideEffects = 1; 5129} 5130 5131multiclass sve_mem_32b_prfm_sv_scaled<bits<2> msz, string asm, 5132 RegisterOperand sxtw_opnd, 5133 RegisterOperand uxtw_opnd> { 5134 def _UXTW_SCALED : sve_mem_32b_prfm_sv<msz, 0, asm, uxtw_opnd>; 5135 def _SXTW_SCALED : sve_mem_32b_prfm_sv<msz, 1, asm, sxtw_opnd>; 5136} 5137 5138class sve_mem_32b_prfm_vi<bits<2> msz, string asm, Operand imm_ty> 5139: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5), 5140 asm, "\t$prfop, $Pg, [$Zn, $imm5]", 5141 "", 5142 []>, Sched<[]> { 5143 bits<3> Pg; 5144 bits<5> Zn; 5145 bits<5> imm5; 5146 bits<4> prfop; 5147 let Inst{31-25} = 0b1000010; 5148 let Inst{24-23} = msz; 5149 let Inst{22-21} = 0b00; 5150 let Inst{20-16} = imm5; 5151 let Inst{15-13} = 0b111; 5152 let Inst{12-10} = Pg; 5153 let Inst{9-5} = Zn; 5154 let Inst{4} = 0b0; 5155 let Inst{3-0} = prfop; 5156} 5157 5158multiclass sve_mem_32b_prfm_vi<bits<2> msz, string asm, Operand imm_ty> { 5159 def NAME : sve_mem_32b_prfm_vi<msz, asm, imm_ty>; 5160 5161 def : InstAlias<asm # "\t$prfop, $Pg, [$Zn]", 5162 (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>; 5163} 5164 5165class sve_mem_z_fill<string asm> 5166: I<(outs ZPRAny:$Zt), (ins GPR64sp:$Rn, simm9:$imm9), 5167 asm, "\t$Zt, [$Rn, $imm9, mul vl]", 5168 "", 5169 []>, Sched<[]> { 5170 bits<5> Rn; 5171 bits<5> Zt; 5172 bits<9> imm9; 5173 let Inst{31-22} = 0b1000010110; 5174 let Inst{21-16} = imm9{8-3}; 5175 let Inst{15-13} = 0b010; 5176 let Inst{12-10} = imm9{2-0}; 5177 let Inst{9-5} = Rn; 5178 let Inst{4-0} = Zt; 5179 5180 let mayLoad = 1; 5181} 5182 5183multiclass sve_mem_z_fill<string asm> { 5184 def NAME : sve_mem_z_fill<asm>; 5185 5186 def : InstAlias<asm # "\t$Zt, [$Rn]", 5187 (!cast<Instruction>(NAME) ZPRAny:$Zt, GPR64sp:$Rn, 0), 1>; 5188} 5189 5190class sve_mem_p_fill<string asm> 5191: I<(outs PPRAny:$Pt), (ins GPR64sp:$Rn, simm9:$imm9), 5192 asm, "\t$Pt, [$Rn, $imm9, mul vl]", 5193 "", 5194 []>, Sched<[]> { 5195 bits<4> Pt; 5196 bits<5> Rn; 5197 bits<9> imm9; 5198 let Inst{31-22} = 0b1000010110; 5199 let Inst{21-16} = imm9{8-3}; 5200 let Inst{15-13} = 0b000; 5201 let Inst{12-10} = imm9{2-0}; 5202 let Inst{9-5} = Rn; 5203 let Inst{4} = 0b0; 5204 let Inst{3-0} = Pt; 5205 5206 let mayLoad = 1; 5207} 5208 5209multiclass sve_mem_p_fill<string asm> { 5210 def NAME : sve_mem_p_fill<asm>; 5211 5212 def : InstAlias<asm # "\t$Pt, [$Rn]", 5213 (!cast<Instruction>(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>; 5214} 5215 5216class sve2_mem_gldnt_vs_base<bits<5> opc, dag iops, string asm, 5217 RegisterOperand VecList> 5218: I<(outs VecList:$Zt), iops, 5219 asm, "\t$Zt, $Pg/z, [$Zn, $Rm]", 5220 "", 5221 []>, Sched<[]> { 5222 bits<3> Pg; 5223 bits<5> Rm; 5224 bits<5> Zn; 5225 bits<5> Zt; 5226 let Inst{31} = 0b1; 5227 let Inst{30} = opc{4}; 5228 let Inst{29-25} = 0b00010; 5229 let Inst{24-23} = opc{3-2}; 5230 let Inst{22-21} = 0b00; 5231 let Inst{20-16} = Rm; 5232 let Inst{15} = 0b1; 5233 let Inst{14-13} = opc{1-0}; 5234 let Inst{12-10} = Pg; 5235 let Inst{9-5} = Zn; 5236 let Inst{4-0} = Zt; 5237 5238 let mayLoad = 1; 5239} 5240 5241multiclass sve2_mem_gldnt_vs<bits<5> opc, string asm, 5242 RegisterOperand listty, ZPRRegOp zprty> { 5243 def _REAL : sve2_mem_gldnt_vs_base<opc, (ins PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 5244 asm, listty>; 5245 5246 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $Rm]", 5247 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>; 5248 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]", 5249 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 0>; 5250 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]", 5251 (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 1>; 5252} 5253 5254//===----------------------------------------------------------------------===// 5255// SVE Memory - 64-bit Gather Group 5256//===----------------------------------------------------------------------===// 5257 5258// bit xs is '1' if offsets are signed 5259// bit scaled is '1' if the offsets are scaled 5260// bit lsl is '0' if the offsets are extended (uxtw/sxtw), '1' if shifted (lsl) 5261class sve_mem_64b_gld_sv<bits<4> opc, bit xs, bit scaled, bit lsl, string asm, 5262 RegisterOperand zprext> 5263: I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 5264 asm, "\t$Zt, $Pg/z, [$Rn, $Zm]", 5265 "", 5266 []>, Sched<[]> { 5267 bits<3> Pg; 5268 bits<5> Rn; 5269 bits<5> Zm; 5270 bits<5> Zt; 5271 let Inst{31-25} = 0b1100010; 5272 let Inst{24-23} = opc{3-2}; 5273 let Inst{22} = xs; 5274 let Inst{21} = scaled; 5275 let Inst{20-16} = Zm; 5276 let Inst{15} = lsl; 5277 let Inst{14-13} = opc{1-0}; 5278 let Inst{12-10} = Pg; 5279 let Inst{9-5} = Rn; 5280 let Inst{4-0} = Zt; 5281 5282 let mayLoad = 1; 5283 let Defs = !if(!eq(opc{0}, 1), [FFR], []); 5284 let Uses = !if(!eq(opc{0}, 1), [FFR], []); 5285} 5286 5287multiclass sve_mem_64b_gld_sv_32_scaled<bits<4> opc, string asm, 5288 RegisterOperand sxtw_opnd, 5289 RegisterOperand uxtw_opnd> { 5290 def _UXTW_SCALED_REAL : sve_mem_64b_gld_sv<opc, 0, 1, 0, asm, uxtw_opnd>; 5291 def _SXTW_SCALED_REAL : sve_mem_64b_gld_sv<opc, 1, 1, 0, asm, sxtw_opnd>; 5292 5293 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]", 5294 (!cast<Instruction>(NAME # _UXTW_SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>; 5295 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]", 5296 (!cast<Instruction>(NAME # _SXTW_SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>; 5297} 5298 5299multiclass sve_mem_64b_gld_vs_32_unscaled<bits<4> opc, string asm, 5300 RegisterOperand sxtw_opnd, 5301 RegisterOperand uxtw_opnd> { 5302 def _UXTW_REAL : sve_mem_64b_gld_sv<opc, 0, 0, 0, asm, uxtw_opnd>; 5303 def _SXTW_REAL : sve_mem_64b_gld_sv<opc, 1, 0, 0, asm, sxtw_opnd>; 5304 5305 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]", 5306 (!cast<Instruction>(NAME # _UXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>; 5307 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]", 5308 (!cast<Instruction>(NAME # _SXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>; 5309} 5310 5311multiclass sve_mem_64b_gld_sv2_64_scaled<bits<4> opc, string asm, 5312 RegisterOperand zprext> { 5313 def _SCALED_REAL : sve_mem_64b_gld_sv<opc, 1, 1, 1, asm, zprext>; 5314 5315 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]", 5316 (!cast<Instruction>(NAME # _SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>; 5317} 5318 5319multiclass sve_mem_64b_gld_vs2_64_unscaled<bits<4> opc, string asm> { 5320 def _REAL : sve_mem_64b_gld_sv<opc, 1, 0, 1, asm, ZPR64ExtLSL8>; 5321 5322 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]", 5323 (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>; 5324} 5325 5326class sve_mem_64b_gld_vi<bits<4> opc, string asm, Operand imm_ty> 5327: I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 5328 asm, "\t$Zt, $Pg/z, [$Zn, $imm5]", 5329 "", 5330 []>, Sched<[]> { 5331 bits<3> Pg; 5332 bits<5> Zn; 5333 bits<5> Zt; 5334 bits<5> imm5; 5335 let Inst{31-25} = 0b1100010; 5336 let Inst{24-23} = opc{3-2}; 5337 let Inst{22-21} = 0b01; 5338 let Inst{20-16} = imm5; 5339 let Inst{15} = 0b1; 5340 let Inst{14-13} = opc{1-0}; 5341 let Inst{12-10} = Pg; 5342 let Inst{9-5} = Zn; 5343 let Inst{4-0} = Zt; 5344 5345 let mayLoad = 1; 5346 let Defs = !if(!eq(opc{0}, 1), [FFR], []); 5347 let Uses = !if(!eq(opc{0}, 1), [FFR], []); 5348} 5349 5350multiclass sve_mem_64b_gld_vi_64_ptrs<bits<4> opc, string asm, Operand imm_ty> { 5351 def _IMM_REAL : sve_mem_64b_gld_vi<opc, asm, imm_ty>; 5352 5353 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]", 5354 (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 0>; 5355 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $imm5]", 5356 (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>; 5357 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]", 5358 (!cast<Instruction>(NAME # _IMM_REAL) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>; 5359} 5360 5361// bit lsl is '0' if the offsets are extended (uxtw/sxtw), '1' if shifted (lsl) 5362class sve_mem_64b_prfm_sv<bits<2> msz, bit xs, bit lsl, string asm, 5363 RegisterOperand zprext> 5364: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 5365 asm, "\t$prfop, $Pg, [$Rn, $Zm]", 5366 "", 5367 []>, Sched<[]> { 5368 bits<3> Pg; 5369 bits<5> Rn; 5370 bits<5> Zm; 5371 bits<4> prfop; 5372 let Inst{31-23} = 0b110001000; 5373 let Inst{22} = xs; 5374 let Inst{21} = 0b1; 5375 let Inst{20-16} = Zm; 5376 let Inst{15} = lsl; 5377 let Inst{14-13} = msz; 5378 let Inst{12-10} = Pg; 5379 let Inst{9-5} = Rn; 5380 let Inst{4} = 0b0; 5381 let Inst{3-0} = prfop; 5382 5383 let hasSideEffects = 1; 5384} 5385 5386multiclass sve_mem_64b_prfm_sv_ext_scaled<bits<2> msz, string asm, 5387 RegisterOperand sxtw_opnd, 5388 RegisterOperand uxtw_opnd> { 5389 def _UXTW_SCALED : sve_mem_64b_prfm_sv<msz, 0, 0, asm, uxtw_opnd>; 5390 def _SXTW_SCALED : sve_mem_64b_prfm_sv<msz, 1, 0, asm, sxtw_opnd>; 5391} 5392 5393multiclass sve_mem_64b_prfm_sv_lsl_scaled<bits<2> msz, string asm, 5394 RegisterOperand zprext> { 5395 def NAME : sve_mem_64b_prfm_sv<msz, 1, 1, asm, zprext>; 5396} 5397 5398 5399class sve_mem_64b_prfm_vi<bits<2> msz, string asm, Operand imm_ty> 5400: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 5401 asm, "\t$prfop, $Pg, [$Zn, $imm5]", 5402 "", 5403 []>, Sched<[]> { 5404 bits<3> Pg; 5405 bits<5> Zn; 5406 bits<5> imm5; 5407 bits<4> prfop; 5408 let Inst{31-25} = 0b1100010; 5409 let Inst{24-23} = msz; 5410 let Inst{22-21} = 0b00; 5411 let Inst{20-16} = imm5; 5412 let Inst{15-13} = 0b111; 5413 let Inst{12-10} = Pg; 5414 let Inst{9-5} = Zn; 5415 let Inst{4} = 0b0; 5416 let Inst{3-0} = prfop; 5417 5418 let hasSideEffects = 1; 5419} 5420 5421multiclass sve_mem_64b_prfm_vi<bits<2> msz, string asm, Operand imm_ty> { 5422 def NAME : sve_mem_64b_prfm_vi<msz, asm, imm_ty>; 5423 5424 def : InstAlias<asm # "\t$prfop, $Pg, [$Zn]", 5425 (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>; 5426} 5427 5428 5429//===----------------------------------------------------------------------===// 5430// SVE Compute Vector Address Group 5431//===----------------------------------------------------------------------===// 5432 5433class sve_int_bin_cons_misc_0_a<bits<2> opc, bits<2> msz, string asm, 5434 ZPRRegOp zprty, RegisterOperand zprext> 5435: I<(outs zprty:$Zd), (ins zprty:$Zn, zprext:$Zm), 5436 asm, "\t$Zd, [$Zn, $Zm]", 5437 "", 5438 []>, Sched<[]> { 5439 bits<5> Zd; 5440 bits<5> Zn; 5441 bits<5> Zm; 5442 let Inst{31-24} = 0b00000100; 5443 let Inst{23-22} = opc; 5444 let Inst{21} = 0b1; 5445 let Inst{20-16} = Zm; 5446 let Inst{15-12} = 0b1010; 5447 let Inst{11-10} = msz; 5448 let Inst{9-5} = Zn; 5449 let Inst{4-0} = Zd; 5450} 5451 5452multiclass sve_int_bin_cons_misc_0_a_uxtw<bits<2> opc, string asm> { 5453 def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR64, ZPR64ExtUXTW8>; 5454 def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR64, ZPR64ExtUXTW16>; 5455 def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR64, ZPR64ExtUXTW32>; 5456 def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR64, ZPR64ExtUXTW64>; 5457} 5458 5459multiclass sve_int_bin_cons_misc_0_a_sxtw<bits<2> opc, string asm> { 5460 def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR64, ZPR64ExtSXTW8>; 5461 def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR64, ZPR64ExtSXTW16>; 5462 def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR64, ZPR64ExtSXTW32>; 5463 def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR64, ZPR64ExtSXTW64>; 5464} 5465 5466multiclass sve_int_bin_cons_misc_0_a_32_lsl<bits<2> opc, string asm> { 5467 def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR32, ZPR32ExtLSL8>; 5468 def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR32, ZPR32ExtLSL16>; 5469 def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR32, ZPR32ExtLSL32>; 5470 def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR32, ZPR32ExtLSL64>; 5471} 5472 5473multiclass sve_int_bin_cons_misc_0_a_64_lsl<bits<2> opc, string asm> { 5474 def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR64, ZPR64ExtLSL8>; 5475 def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR64, ZPR64ExtLSL16>; 5476 def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR64, ZPR64ExtLSL32>; 5477 def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR64, ZPR64ExtLSL64>; 5478} 5479 5480 5481//===----------------------------------------------------------------------===// 5482// SVE Integer Misc - Unpredicated Group 5483//===----------------------------------------------------------------------===// 5484 5485class sve_int_bin_cons_misc_0_b<bits<2> sz, string asm, ZPRRegOp zprty> 5486: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), 5487 asm, "\t$Zd, $Zn, $Zm", 5488 "", 5489 []>, Sched<[]> { 5490 bits<5> Zd; 5491 bits<5> Zm; 5492 bits<5> Zn; 5493 let Inst{31-24} = 0b00000100; 5494 let Inst{23-22} = sz; 5495 let Inst{21} = 0b1; 5496 let Inst{20-16} = Zm; 5497 let Inst{15-10} = 0b101100; 5498 let Inst{9-5} = Zn; 5499 let Inst{4-0} = Zd; 5500} 5501 5502multiclass sve_int_bin_cons_misc_0_b<string asm> { 5503 def _H : sve_int_bin_cons_misc_0_b<0b01, asm, ZPR16>; 5504 def _S : sve_int_bin_cons_misc_0_b<0b10, asm, ZPR32>; 5505 def _D : sve_int_bin_cons_misc_0_b<0b11, asm, ZPR64>; 5506} 5507 5508class sve_int_bin_cons_misc_0_c<bits<8> opc, string asm, ZPRRegOp zprty> 5509: I<(outs zprty:$Zd), (ins zprty:$Zn), 5510 asm, "\t$Zd, $Zn", 5511 "", 5512 []>, Sched<[]> { 5513 bits<5> Zd; 5514 bits<5> Zn; 5515 let Inst{31-24} = 0b00000100; 5516 let Inst{23-22} = opc{7-6}; 5517 let Inst{21} = 0b1; 5518 let Inst{20-16} = opc{5-1}; 5519 let Inst{15-11} = 0b10111; 5520 let Inst{10} = opc{0}; 5521 let Inst{9-5} = Zn; 5522 let Inst{4-0} = Zd; 5523} 5524 5525//===----------------------------------------------------------------------===// 5526// SVE Integer Reduction Group 5527//===----------------------------------------------------------------------===// 5528 5529class sve_int_reduce<bits<2> sz8_32, bits<2> fmt, bits<3> opc, string asm, 5530 ZPRRegOp zprty, RegisterClass regtype> 5531: I<(outs regtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn), 5532 asm, "\t$Vd, $Pg, $Zn", 5533 "", 5534 []>, Sched<[]> { 5535 bits<3> Pg; 5536 bits<5> Vd; 5537 bits<5> Zn; 5538 let Inst{31-24} = 0b00000100; 5539 let Inst{23-22} = sz8_32; 5540 let Inst{21} = 0b0; 5541 let Inst{20-19} = fmt; 5542 let Inst{18-16} = opc; 5543 let Inst{15-13} = 0b001; 5544 let Inst{12-10} = Pg; 5545 let Inst{9-5} = Zn; 5546 let Inst{4-0} = Vd; 5547} 5548 5549multiclass sve_int_reduce_0_saddv<bits<3> opc, string asm> { 5550 def _B : sve_int_reduce<0b00, 0b00, opc, asm, ZPR8, FPR64>; 5551 def _H : sve_int_reduce<0b01, 0b00, opc, asm, ZPR16, FPR64>; 5552 def _S : sve_int_reduce<0b10, 0b00, opc, asm, ZPR32, FPR64>; 5553} 5554 5555multiclass sve_int_reduce_0_uaddv<bits<3> opc, string asm> { 5556 def _B : sve_int_reduce<0b00, 0b00, opc, asm, ZPR8, FPR64>; 5557 def _H : sve_int_reduce<0b01, 0b00, opc, asm, ZPR16, FPR64>; 5558 def _S : sve_int_reduce<0b10, 0b00, opc, asm, ZPR32, FPR64>; 5559 def _D : sve_int_reduce<0b11, 0b00, opc, asm, ZPR64, FPR64>; 5560} 5561 5562multiclass sve_int_reduce_1<bits<3> opc, string asm> { 5563 def _B : sve_int_reduce<0b00, 0b01, opc, asm, ZPR8, FPR8>; 5564 def _H : sve_int_reduce<0b01, 0b01, opc, asm, ZPR16, FPR16>; 5565 def _S : sve_int_reduce<0b10, 0b01, opc, asm, ZPR32, FPR32>; 5566 def _D : sve_int_reduce<0b11, 0b01, opc, asm, ZPR64, FPR64>; 5567} 5568 5569multiclass sve_int_reduce_2<bits<3> opc, string asm> { 5570 def _B : sve_int_reduce<0b00, 0b11, opc, asm, ZPR8, FPR8>; 5571 def _H : sve_int_reduce<0b01, 0b11, opc, asm, ZPR16, FPR16>; 5572 def _S : sve_int_reduce<0b10, 0b11, opc, asm, ZPR32, FPR32>; 5573 def _D : sve_int_reduce<0b11, 0b11, opc, asm, ZPR64, FPR64>; 5574} 5575 5576class sve_int_movprfx_pred<bits<2> sz8_32, bits<3> opc, string asm, 5577 ZPRRegOp zprty, string pg_suffix, dag iops> 5578: I<(outs zprty:$Zd), iops, 5579 asm, "\t$Zd, $Pg"#pg_suffix#", $Zn", 5580 "", 5581 []>, Sched<[]> { 5582 bits<3> Pg; 5583 bits<5> Zd; 5584 bits<5> Zn; 5585 let Inst{31-24} = 0b00000100; 5586 let Inst{23-22} = sz8_32; 5587 let Inst{21-19} = 0b010; 5588 let Inst{18-16} = opc; 5589 let Inst{15-13} = 0b001; 5590 let Inst{12-10} = Pg; 5591 let Inst{9-5} = Zn; 5592 let Inst{4-0} = Zd; 5593 5594 let ElementSize = zprty.ElementSize; 5595} 5596 5597multiclass sve_int_movprfx_pred_merge<bits<3> opc, string asm> { 5598let Constraints = "$Zd = $_Zd" in { 5599 def _B : sve_int_movprfx_pred<0b00, opc, asm, ZPR8, "/m", 5600 (ins ZPR8:$_Zd, PPR3bAny:$Pg, ZPR8:$Zn)>; 5601 def _H : sve_int_movprfx_pred<0b01, opc, asm, ZPR16, "/m", 5602 (ins ZPR16:$_Zd, PPR3bAny:$Pg, ZPR16:$Zn)>; 5603 def _S : sve_int_movprfx_pred<0b10, opc, asm, ZPR32, "/m", 5604 (ins ZPR32:$_Zd, PPR3bAny:$Pg, ZPR32:$Zn)>; 5605 def _D : sve_int_movprfx_pred<0b11, opc, asm, ZPR64, "/m", 5606 (ins ZPR64:$_Zd, PPR3bAny:$Pg, ZPR64:$Zn)>; 5607} 5608} 5609 5610multiclass sve_int_movprfx_pred_zero<bits<3> opc, string asm> { 5611 def _B : sve_int_movprfx_pred<0b00, opc, asm, ZPR8, "/z", 5612 (ins PPR3bAny:$Pg, ZPR8:$Zn)>; 5613 def _H : sve_int_movprfx_pred<0b01, opc, asm, ZPR16, "/z", 5614 (ins PPR3bAny:$Pg, ZPR16:$Zn)>; 5615 def _S : sve_int_movprfx_pred<0b10, opc, asm, ZPR32, "/z", 5616 (ins PPR3bAny:$Pg, ZPR32:$Zn)>; 5617 def _D : sve_int_movprfx_pred<0b11, opc, asm, ZPR64, "/z", 5618 (ins PPR3bAny:$Pg, ZPR64:$Zn)>; 5619} 5620 5621//===----------------------------------------------------------------------===// 5622// SVE Propagate Break Group 5623//===----------------------------------------------------------------------===// 5624 5625class sve_int_brkp<bits<2> opc, string asm> 5626: I<(outs PPR8:$Pd), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$Pm), 5627 asm, "\t$Pd, $Pg/z, $Pn, $Pm", 5628 "", 5629 []>, Sched<[]> { 5630 bits<4> Pd; 5631 bits<4> Pg; 5632 bits<4> Pm; 5633 bits<4> Pn; 5634 let Inst{31-24} = 0b00100101; 5635 let Inst{23} = 0b0; 5636 let Inst{22} = opc{1}; 5637 let Inst{21-20} = 0b00; 5638 let Inst{19-16} = Pm; 5639 let Inst{15-14} = 0b11; 5640 let Inst{13-10} = Pg; 5641 let Inst{9} = 0b0; 5642 let Inst{8-5} = Pn; 5643 let Inst{4} = opc{0}; 5644 let Inst{3-0} = Pd; 5645 5646 let Defs = !if(!eq (opc{1}, 1), [NZCV], []); 5647} 5648 5649 5650//===----------------------------------------------------------------------===// 5651// SVE Partition Break Group 5652//===----------------------------------------------------------------------===// 5653 5654class sve_int_brkn<bit S, string asm> 5655: I<(outs PPR8:$Pdm), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$_Pdm), 5656 asm, "\t$Pdm, $Pg/z, $Pn, $_Pdm", 5657 "", 5658 []>, Sched<[]> { 5659 bits<4> Pdm; 5660 bits<4> Pg; 5661 bits<4> Pn; 5662 let Inst{31-23} = 0b001001010; 5663 let Inst{22} = S; 5664 let Inst{21-14} = 0b01100001; 5665 let Inst{13-10} = Pg; 5666 let Inst{9} = 0b0; 5667 let Inst{8-5} = Pn; 5668 let Inst{4} = 0b0; 5669 let Inst{3-0} = Pdm; 5670 5671 let Constraints = "$Pdm = $_Pdm"; 5672 let Defs = !if(!eq (S, 0b1), [NZCV], []); 5673} 5674 5675class sve_int_break<bits<3> opc, string asm, string suffix, dag iops> 5676: I<(outs PPR8:$Pd), iops, 5677 asm, "\t$Pd, $Pg"#suffix#", $Pn", 5678 "", 5679 []>, Sched<[]> { 5680 bits<4> Pd; 5681 bits<4> Pg; 5682 bits<4> Pn; 5683 let Inst{31-24} = 0b00100101; 5684 let Inst{23-22} = opc{2-1}; 5685 let Inst{21-14} = 0b01000001; 5686 let Inst{13-10} = Pg; 5687 let Inst{9} = 0b0; 5688 let Inst{8-5} = Pn; 5689 let Inst{4} = opc{0}; 5690 let Inst{3-0} = Pd; 5691 5692 let Constraints = !if(!eq (opc{0}, 1), "$Pd = $_Pd", ""); 5693 let Defs = !if(!eq (opc{1}, 1), [NZCV], []); 5694 5695} 5696 5697multiclass sve_int_break_m<bits<3> opc, string asm> { 5698 def NAME : sve_int_break<opc, asm, "/m", (ins PPR8:$_Pd, PPRAny:$Pg, PPR8:$Pn)>; 5699} 5700 5701multiclass sve_int_break_z<bits<3> opc, string asm> { 5702 def NAME : sve_int_break<opc, asm, "/z", (ins PPRAny:$Pg, PPR8:$Pn)>; 5703} 5704 5705//===----------------------------------------------------------------------===// 5706// SVE2 String Processing Group 5707//===----------------------------------------------------------------------===// 5708 5709class sve2_char_match<bit sz, bit opc, string asm, 5710 PPRRegOp pprty, ZPRRegOp zprty> 5711: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm), 5712 asm, "\t$Pd, $Pg/z, $Zn, $Zm", 5713 "", 5714 []>, Sched<[]> { 5715 bits<4> Pd; 5716 bits<3> Pg; 5717 bits<5> Zm; 5718 bits<5> Zn; 5719 let Inst{31-23} = 0b010001010; 5720 let Inst{22} = sz; 5721 let Inst{21} = 0b1; 5722 let Inst{20-16} = Zm; 5723 let Inst{15-13} = 0b100; 5724 let Inst{12-10} = Pg; 5725 let Inst{9-5} = Zn; 5726 let Inst{4} = opc; 5727 let Inst{3-0} = Pd; 5728 5729 let Defs = [NZCV]; 5730} 5731 5732multiclass sve2_char_match<bit opc, string asm> { 5733 def _B : sve2_char_match<0b0, opc, asm, PPR8, ZPR8>; 5734 def _H : sve2_char_match<0b1, opc, asm, PPR16, ZPR16>; 5735} 5736 5737//===----------------------------------------------------------------------===// 5738// SVE2 Histogram Computation - Segment Group 5739//===----------------------------------------------------------------------===// 5740 5741class sve2_hist_gen_segment<string asm> 5742: I<(outs ZPR8:$Zd), (ins ZPR8:$Zn, ZPR8:$Zm), 5743 asm, "\t$Zd, $Zn, $Zm", 5744 "", 5745 []>, Sched<[]> { 5746 bits<5> Zd; 5747 bits<5> Zn; 5748 bits<5> Zm; 5749 let Inst{31-21} = 0b01000101001; 5750 let Inst{20-16} = Zm; 5751 let Inst{15-10} = 0b101000; 5752 let Inst{9-5} = Zn; 5753 let Inst{4-0} = Zd; 5754} 5755 5756//===----------------------------------------------------------------------===// 5757// SVE2 Histogram Computation - Vector Group 5758//===----------------------------------------------------------------------===// 5759 5760class sve2_hist_gen_vector<bit sz, string asm, ZPRRegOp zprty> 5761: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm), 5762 asm, "\t$Zd, $Pg/z, $Zn, $Zm", 5763 "", 5764 []>, Sched<[]> { 5765 bits<5> Zd; 5766 bits<5> Zn; 5767 bits<3> Pg; 5768 bits<5> Zm; 5769 let Inst{31-23} = 0b010001011; 5770 let Inst{22} = sz; 5771 let Inst{21} = 0b1; 5772 let Inst{20-16} = Zm; 5773 let Inst{15-13} = 0b110; 5774 let Inst{12-10} = Pg; 5775 let Inst{9-5} = Zn; 5776 let Inst{4-0} = Zd; 5777} 5778 5779multiclass sve2_hist_gen_vector<string asm> { 5780 def _S : sve2_hist_gen_vector<0b0, asm, ZPR32>; 5781 def _D : sve2_hist_gen_vector<0b1, asm, ZPR64>; 5782} 5783 5784//===----------------------------------------------------------------------===// 5785// SVE2 Crypto Extensions Group 5786//===----------------------------------------------------------------------===// 5787 5788class sve2_crypto_cons_bin_op<bit opc, string asm, ZPRRegOp zprty> 5789: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), 5790 asm, "\t$Zd, $Zn, $Zm", 5791 "", 5792 []>, Sched<[]> { 5793 bits<5> Zd; 5794 bits<5> Zn; 5795 bits<5> Zm; 5796 let Inst{31-21} = 0b01000101001; 5797 let Inst{20-16} = Zm; 5798 let Inst{15-11} = 0b11110; 5799 let Inst{10} = opc; 5800 let Inst{9-5} = Zn; 5801 let Inst{4-0} = Zd; 5802} 5803 5804class sve2_crypto_des_bin_op<bits<2> opc, string asm, ZPRRegOp zprty> 5805: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm), 5806 asm, "\t$Zdn, $_Zdn, $Zm", 5807 "", 5808 []>, Sched<[]> { 5809 bits<5> Zdn; 5810 bits<5> Zm; 5811 let Inst{31-17} = 0b010001010010001; 5812 let Inst{16} = opc{1}; 5813 let Inst{15-11} = 0b11100; 5814 let Inst{10} = opc{0}; 5815 let Inst{9-5} = Zm; 5816 let Inst{4-0} = Zdn; 5817 5818 let Constraints = "$Zdn = $_Zdn"; 5819} 5820 5821class sve2_crypto_unary_op<bit opc, string asm> 5822: I<(outs ZPR8:$Zdn), (ins ZPR8:$_Zdn), 5823 asm, "\t$Zdn, $_Zdn", 5824 "", 5825 []>, Sched<[]> { 5826 bits<5> Zdn; 5827 let Inst{31-11} = 0b010001010010000011100; 5828 let Inst{10} = opc; 5829 let Inst{9-5} = 0b00000; 5830 let Inst{4-0} = Zdn; 5831 5832 let Constraints = "$Zdn = $_Zdn"; 5833} 5834