1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides AArch64 specific target descriptions. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AArch64MCTargetDesc.h" 14 #include "AArch64ELFStreamer.h" 15 #include "AArch64MCAsmInfo.h" 16 #include "AArch64WinCOFFStreamer.h" 17 #include "MCTargetDesc/AArch64AddressingModes.h" 18 #include "MCTargetDesc/AArch64InstPrinter.h" 19 #include "TargetInfo/AArch64TargetInfo.h" 20 #include "llvm/DebugInfo/CodeView/CodeView.h" 21 #include "llvm/MC/MCAsmBackend.h" 22 #include "llvm/MC/MCCodeEmitter.h" 23 #include "llvm/MC/MCInstrAnalysis.h" 24 #include "llvm/MC/MCInstrInfo.h" 25 #include "llvm/MC/MCObjectWriter.h" 26 #include "llvm/MC/MCRegisterInfo.h" 27 #include "llvm/MC/MCStreamer.h" 28 #include "llvm/MC/MCSubtargetInfo.h" 29 #include "llvm/MC/TargetRegistry.h" 30 #include "llvm/Support/Endian.h" 31 #include "llvm/Support/ErrorHandling.h" 32 #include "llvm/TargetParser/AArch64TargetParser.h" 33 34 using namespace llvm; 35 36 #define GET_INSTRINFO_MC_DESC 37 #define GET_INSTRINFO_MC_HELPERS 38 #define ENABLE_INSTR_PREDICATE_VERIFIER 39 #include "AArch64GenInstrInfo.inc" 40 41 #define GET_SUBTARGETINFO_MC_DESC 42 #include "AArch64GenSubtargetInfo.inc" 43 44 #define GET_REGINFO_MC_DESC 45 #include "AArch64GenRegisterInfo.inc" 46 47 static MCInstrInfo *createAArch64MCInstrInfo() { 48 MCInstrInfo *X = new MCInstrInfo(); 49 InitAArch64MCInstrInfo(X); 50 return X; 51 } 52 53 static MCSubtargetInfo * 54 createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { 55 CPU = AArch64::resolveCPUAlias(CPU); 56 57 if (CPU.empty()) { 58 CPU = "generic"; 59 if (FS.empty()) 60 FS = "+v8a"; 61 62 if (TT.isArm64e()) 63 CPU = "apple-a12"; 64 } 65 66 return createAArch64MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); 67 } 68 69 void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) { 70 // Mapping from CodeView to MC register id. 71 static const struct { 72 codeview::RegisterId CVReg; 73 MCPhysReg Reg; 74 } RegMap[] = { 75 {codeview::RegisterId::ARM64_W0, AArch64::W0}, 76 {codeview::RegisterId::ARM64_W1, AArch64::W1}, 77 {codeview::RegisterId::ARM64_W2, AArch64::W2}, 78 {codeview::RegisterId::ARM64_W3, AArch64::W3}, 79 {codeview::RegisterId::ARM64_W4, AArch64::W4}, 80 {codeview::RegisterId::ARM64_W5, AArch64::W5}, 81 {codeview::RegisterId::ARM64_W6, AArch64::W6}, 82 {codeview::RegisterId::ARM64_W7, AArch64::W7}, 83 {codeview::RegisterId::ARM64_W8, AArch64::W8}, 84 {codeview::RegisterId::ARM64_W9, AArch64::W9}, 85 {codeview::RegisterId::ARM64_W10, AArch64::W10}, 86 {codeview::RegisterId::ARM64_W11, AArch64::W11}, 87 {codeview::RegisterId::ARM64_W12, AArch64::W12}, 88 {codeview::RegisterId::ARM64_W13, AArch64::W13}, 89 {codeview::RegisterId::ARM64_W14, AArch64::W14}, 90 {codeview::RegisterId::ARM64_W15, AArch64::W15}, 91 {codeview::RegisterId::ARM64_W16, AArch64::W16}, 92 {codeview::RegisterId::ARM64_W17, AArch64::W17}, 93 {codeview::RegisterId::ARM64_W18, AArch64::W18}, 94 {codeview::RegisterId::ARM64_W19, AArch64::W19}, 95 {codeview::RegisterId::ARM64_W20, AArch64::W20}, 96 {codeview::RegisterId::ARM64_W21, AArch64::W21}, 97 {codeview::RegisterId::ARM64_W22, AArch64::W22}, 98 {codeview::RegisterId::ARM64_W23, AArch64::W23}, 99 {codeview::RegisterId::ARM64_W24, AArch64::W24}, 100 {codeview::RegisterId::ARM64_W25, AArch64::W25}, 101 {codeview::RegisterId::ARM64_W26, AArch64::W26}, 102 {codeview::RegisterId::ARM64_W27, AArch64::W27}, 103 {codeview::RegisterId::ARM64_W28, AArch64::W28}, 104 {codeview::RegisterId::ARM64_W29, AArch64::W29}, 105 {codeview::RegisterId::ARM64_W30, AArch64::W30}, 106 {codeview::RegisterId::ARM64_WZR, AArch64::WZR}, 107 {codeview::RegisterId::ARM64_X0, AArch64::X0}, 108 {codeview::RegisterId::ARM64_X1, AArch64::X1}, 109 {codeview::RegisterId::ARM64_X2, AArch64::X2}, 110 {codeview::RegisterId::ARM64_X3, AArch64::X3}, 111 {codeview::RegisterId::ARM64_X4, AArch64::X4}, 112 {codeview::RegisterId::ARM64_X5, AArch64::X5}, 113 {codeview::RegisterId::ARM64_X6, AArch64::X6}, 114 {codeview::RegisterId::ARM64_X7, AArch64::X7}, 115 {codeview::RegisterId::ARM64_X8, AArch64::X8}, 116 {codeview::RegisterId::ARM64_X9, AArch64::X9}, 117 {codeview::RegisterId::ARM64_X10, AArch64::X10}, 118 {codeview::RegisterId::ARM64_X11, AArch64::X11}, 119 {codeview::RegisterId::ARM64_X12, AArch64::X12}, 120 {codeview::RegisterId::ARM64_X13, AArch64::X13}, 121 {codeview::RegisterId::ARM64_X14, AArch64::X14}, 122 {codeview::RegisterId::ARM64_X15, AArch64::X15}, 123 {codeview::RegisterId::ARM64_X16, AArch64::X16}, 124 {codeview::RegisterId::ARM64_X17, AArch64::X17}, 125 {codeview::RegisterId::ARM64_X18, AArch64::X18}, 126 {codeview::RegisterId::ARM64_X19, AArch64::X19}, 127 {codeview::RegisterId::ARM64_X20, AArch64::X20}, 128 {codeview::RegisterId::ARM64_X21, AArch64::X21}, 129 {codeview::RegisterId::ARM64_X22, AArch64::X22}, 130 {codeview::RegisterId::ARM64_X23, AArch64::X23}, 131 {codeview::RegisterId::ARM64_X24, AArch64::X24}, 132 {codeview::RegisterId::ARM64_X25, AArch64::X25}, 133 {codeview::RegisterId::ARM64_X26, AArch64::X26}, 134 {codeview::RegisterId::ARM64_X27, AArch64::X27}, 135 {codeview::RegisterId::ARM64_X28, AArch64::X28}, 136 {codeview::RegisterId::ARM64_FP, AArch64::FP}, 137 {codeview::RegisterId::ARM64_LR, AArch64::LR}, 138 {codeview::RegisterId::ARM64_SP, AArch64::SP}, 139 {codeview::RegisterId::ARM64_ZR, AArch64::XZR}, 140 {codeview::RegisterId::ARM64_NZCV, AArch64::NZCV}, 141 {codeview::RegisterId::ARM64_S0, AArch64::S0}, 142 {codeview::RegisterId::ARM64_S1, AArch64::S1}, 143 {codeview::RegisterId::ARM64_S2, AArch64::S2}, 144 {codeview::RegisterId::ARM64_S3, AArch64::S3}, 145 {codeview::RegisterId::ARM64_S4, AArch64::S4}, 146 {codeview::RegisterId::ARM64_S5, AArch64::S5}, 147 {codeview::RegisterId::ARM64_S6, AArch64::S6}, 148 {codeview::RegisterId::ARM64_S7, AArch64::S7}, 149 {codeview::RegisterId::ARM64_S8, AArch64::S8}, 150 {codeview::RegisterId::ARM64_S9, AArch64::S9}, 151 {codeview::RegisterId::ARM64_S10, AArch64::S10}, 152 {codeview::RegisterId::ARM64_S11, AArch64::S11}, 153 {codeview::RegisterId::ARM64_S12, AArch64::S12}, 154 {codeview::RegisterId::ARM64_S13, AArch64::S13}, 155 {codeview::RegisterId::ARM64_S14, AArch64::S14}, 156 {codeview::RegisterId::ARM64_S15, AArch64::S15}, 157 {codeview::RegisterId::ARM64_S16, AArch64::S16}, 158 {codeview::RegisterId::ARM64_S17, AArch64::S17}, 159 {codeview::RegisterId::ARM64_S18, AArch64::S18}, 160 {codeview::RegisterId::ARM64_S19, AArch64::S19}, 161 {codeview::RegisterId::ARM64_S20, AArch64::S20}, 162 {codeview::RegisterId::ARM64_S21, AArch64::S21}, 163 {codeview::RegisterId::ARM64_S22, AArch64::S22}, 164 {codeview::RegisterId::ARM64_S23, AArch64::S23}, 165 {codeview::RegisterId::ARM64_S24, AArch64::S24}, 166 {codeview::RegisterId::ARM64_S25, AArch64::S25}, 167 {codeview::RegisterId::ARM64_S26, AArch64::S26}, 168 {codeview::RegisterId::ARM64_S27, AArch64::S27}, 169 {codeview::RegisterId::ARM64_S28, AArch64::S28}, 170 {codeview::RegisterId::ARM64_S29, AArch64::S29}, 171 {codeview::RegisterId::ARM64_S30, AArch64::S30}, 172 {codeview::RegisterId::ARM64_S31, AArch64::S31}, 173 {codeview::RegisterId::ARM64_D0, AArch64::D0}, 174 {codeview::RegisterId::ARM64_D1, AArch64::D1}, 175 {codeview::RegisterId::ARM64_D2, AArch64::D2}, 176 {codeview::RegisterId::ARM64_D3, AArch64::D3}, 177 {codeview::RegisterId::ARM64_D4, AArch64::D4}, 178 {codeview::RegisterId::ARM64_D5, AArch64::D5}, 179 {codeview::RegisterId::ARM64_D6, AArch64::D6}, 180 {codeview::RegisterId::ARM64_D7, AArch64::D7}, 181 {codeview::RegisterId::ARM64_D8, AArch64::D8}, 182 {codeview::RegisterId::ARM64_D9, AArch64::D9}, 183 {codeview::RegisterId::ARM64_D10, AArch64::D10}, 184 {codeview::RegisterId::ARM64_D11, AArch64::D11}, 185 {codeview::RegisterId::ARM64_D12, AArch64::D12}, 186 {codeview::RegisterId::ARM64_D13, AArch64::D13}, 187 {codeview::RegisterId::ARM64_D14, AArch64::D14}, 188 {codeview::RegisterId::ARM64_D15, AArch64::D15}, 189 {codeview::RegisterId::ARM64_D16, AArch64::D16}, 190 {codeview::RegisterId::ARM64_D17, AArch64::D17}, 191 {codeview::RegisterId::ARM64_D18, AArch64::D18}, 192 {codeview::RegisterId::ARM64_D19, AArch64::D19}, 193 {codeview::RegisterId::ARM64_D20, AArch64::D20}, 194 {codeview::RegisterId::ARM64_D21, AArch64::D21}, 195 {codeview::RegisterId::ARM64_D22, AArch64::D22}, 196 {codeview::RegisterId::ARM64_D23, AArch64::D23}, 197 {codeview::RegisterId::ARM64_D24, AArch64::D24}, 198 {codeview::RegisterId::ARM64_D25, AArch64::D25}, 199 {codeview::RegisterId::ARM64_D26, AArch64::D26}, 200 {codeview::RegisterId::ARM64_D27, AArch64::D27}, 201 {codeview::RegisterId::ARM64_D28, AArch64::D28}, 202 {codeview::RegisterId::ARM64_D29, AArch64::D29}, 203 {codeview::RegisterId::ARM64_D30, AArch64::D30}, 204 {codeview::RegisterId::ARM64_D31, AArch64::D31}, 205 {codeview::RegisterId::ARM64_Q0, AArch64::Q0}, 206 {codeview::RegisterId::ARM64_Q1, AArch64::Q1}, 207 {codeview::RegisterId::ARM64_Q2, AArch64::Q2}, 208 {codeview::RegisterId::ARM64_Q3, AArch64::Q3}, 209 {codeview::RegisterId::ARM64_Q4, AArch64::Q4}, 210 {codeview::RegisterId::ARM64_Q5, AArch64::Q5}, 211 {codeview::RegisterId::ARM64_Q6, AArch64::Q6}, 212 {codeview::RegisterId::ARM64_Q7, AArch64::Q7}, 213 {codeview::RegisterId::ARM64_Q8, AArch64::Q8}, 214 {codeview::RegisterId::ARM64_Q9, AArch64::Q9}, 215 {codeview::RegisterId::ARM64_Q10, AArch64::Q10}, 216 {codeview::RegisterId::ARM64_Q11, AArch64::Q11}, 217 {codeview::RegisterId::ARM64_Q12, AArch64::Q12}, 218 {codeview::RegisterId::ARM64_Q13, AArch64::Q13}, 219 {codeview::RegisterId::ARM64_Q14, AArch64::Q14}, 220 {codeview::RegisterId::ARM64_Q15, AArch64::Q15}, 221 {codeview::RegisterId::ARM64_Q16, AArch64::Q16}, 222 {codeview::RegisterId::ARM64_Q17, AArch64::Q17}, 223 {codeview::RegisterId::ARM64_Q18, AArch64::Q18}, 224 {codeview::RegisterId::ARM64_Q19, AArch64::Q19}, 225 {codeview::RegisterId::ARM64_Q20, AArch64::Q20}, 226 {codeview::RegisterId::ARM64_Q21, AArch64::Q21}, 227 {codeview::RegisterId::ARM64_Q22, AArch64::Q22}, 228 {codeview::RegisterId::ARM64_Q23, AArch64::Q23}, 229 {codeview::RegisterId::ARM64_Q24, AArch64::Q24}, 230 {codeview::RegisterId::ARM64_Q25, AArch64::Q25}, 231 {codeview::RegisterId::ARM64_Q26, AArch64::Q26}, 232 {codeview::RegisterId::ARM64_Q27, AArch64::Q27}, 233 {codeview::RegisterId::ARM64_Q28, AArch64::Q28}, 234 {codeview::RegisterId::ARM64_Q29, AArch64::Q29}, 235 {codeview::RegisterId::ARM64_Q30, AArch64::Q30}, 236 {codeview::RegisterId::ARM64_Q31, AArch64::Q31}, 237 {codeview::RegisterId::ARM64_B0, AArch64::B0}, 238 {codeview::RegisterId::ARM64_B1, AArch64::B1}, 239 {codeview::RegisterId::ARM64_B2, AArch64::B2}, 240 {codeview::RegisterId::ARM64_B3, AArch64::B3}, 241 {codeview::RegisterId::ARM64_B4, AArch64::B4}, 242 {codeview::RegisterId::ARM64_B5, AArch64::B5}, 243 {codeview::RegisterId::ARM64_B6, AArch64::B6}, 244 {codeview::RegisterId::ARM64_B7, AArch64::B7}, 245 {codeview::RegisterId::ARM64_B8, AArch64::B8}, 246 {codeview::RegisterId::ARM64_B9, AArch64::B9}, 247 {codeview::RegisterId::ARM64_B10, AArch64::B10}, 248 {codeview::RegisterId::ARM64_B11, AArch64::B11}, 249 {codeview::RegisterId::ARM64_B12, AArch64::B12}, 250 {codeview::RegisterId::ARM64_B13, AArch64::B13}, 251 {codeview::RegisterId::ARM64_B14, AArch64::B14}, 252 {codeview::RegisterId::ARM64_B15, AArch64::B15}, 253 {codeview::RegisterId::ARM64_B16, AArch64::B16}, 254 {codeview::RegisterId::ARM64_B17, AArch64::B17}, 255 {codeview::RegisterId::ARM64_B18, AArch64::B18}, 256 {codeview::RegisterId::ARM64_B19, AArch64::B19}, 257 {codeview::RegisterId::ARM64_B20, AArch64::B20}, 258 {codeview::RegisterId::ARM64_B21, AArch64::B21}, 259 {codeview::RegisterId::ARM64_B22, AArch64::B22}, 260 {codeview::RegisterId::ARM64_B23, AArch64::B23}, 261 {codeview::RegisterId::ARM64_B24, AArch64::B24}, 262 {codeview::RegisterId::ARM64_B25, AArch64::B25}, 263 {codeview::RegisterId::ARM64_B26, AArch64::B26}, 264 {codeview::RegisterId::ARM64_B27, AArch64::B27}, 265 {codeview::RegisterId::ARM64_B28, AArch64::B28}, 266 {codeview::RegisterId::ARM64_B29, AArch64::B29}, 267 {codeview::RegisterId::ARM64_B30, AArch64::B30}, 268 {codeview::RegisterId::ARM64_B31, AArch64::B31}, 269 {codeview::RegisterId::ARM64_H0, AArch64::H0}, 270 {codeview::RegisterId::ARM64_H1, AArch64::H1}, 271 {codeview::RegisterId::ARM64_H2, AArch64::H2}, 272 {codeview::RegisterId::ARM64_H3, AArch64::H3}, 273 {codeview::RegisterId::ARM64_H4, AArch64::H4}, 274 {codeview::RegisterId::ARM64_H5, AArch64::H5}, 275 {codeview::RegisterId::ARM64_H6, AArch64::H6}, 276 {codeview::RegisterId::ARM64_H7, AArch64::H7}, 277 {codeview::RegisterId::ARM64_H8, AArch64::H8}, 278 {codeview::RegisterId::ARM64_H9, AArch64::H9}, 279 {codeview::RegisterId::ARM64_H10, AArch64::H10}, 280 {codeview::RegisterId::ARM64_H11, AArch64::H11}, 281 {codeview::RegisterId::ARM64_H12, AArch64::H12}, 282 {codeview::RegisterId::ARM64_H13, AArch64::H13}, 283 {codeview::RegisterId::ARM64_H14, AArch64::H14}, 284 {codeview::RegisterId::ARM64_H15, AArch64::H15}, 285 {codeview::RegisterId::ARM64_H16, AArch64::H16}, 286 {codeview::RegisterId::ARM64_H17, AArch64::H17}, 287 {codeview::RegisterId::ARM64_H18, AArch64::H18}, 288 {codeview::RegisterId::ARM64_H19, AArch64::H19}, 289 {codeview::RegisterId::ARM64_H20, AArch64::H20}, 290 {codeview::RegisterId::ARM64_H21, AArch64::H21}, 291 {codeview::RegisterId::ARM64_H22, AArch64::H22}, 292 {codeview::RegisterId::ARM64_H23, AArch64::H23}, 293 {codeview::RegisterId::ARM64_H24, AArch64::H24}, 294 {codeview::RegisterId::ARM64_H25, AArch64::H25}, 295 {codeview::RegisterId::ARM64_H26, AArch64::H26}, 296 {codeview::RegisterId::ARM64_H27, AArch64::H27}, 297 {codeview::RegisterId::ARM64_H28, AArch64::H28}, 298 {codeview::RegisterId::ARM64_H29, AArch64::H29}, 299 {codeview::RegisterId::ARM64_H30, AArch64::H30}, 300 {codeview::RegisterId::ARM64_H31, AArch64::H31}, 301 }; 302 for (const auto &I : RegMap) 303 MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg)); 304 } 305 306 bool AArch64_MC::isHForm(const MCInst &MI, const MCInstrInfo *MCII) { 307 const auto &FPR16 = AArch64MCRegisterClasses[AArch64::FPR16RegClassID]; 308 return llvm::any_of(MI, [&](const MCOperand &Op) { 309 return Op.isReg() && FPR16.contains(Op.getReg()); 310 }); 311 } 312 313 bool AArch64_MC::isQForm(const MCInst &MI, const MCInstrInfo *MCII) { 314 const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID]; 315 return llvm::any_of(MI, [&](const MCOperand &Op) { 316 return Op.isReg() && FPR128.contains(Op.getReg()); 317 }); 318 } 319 320 bool AArch64_MC::isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII) { 321 const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID]; 322 const auto &FPR64 = AArch64MCRegisterClasses[AArch64::FPR64RegClassID]; 323 const auto &FPR32 = AArch64MCRegisterClasses[AArch64::FPR32RegClassID]; 324 const auto &FPR16 = AArch64MCRegisterClasses[AArch64::FPR16RegClassID]; 325 const auto &FPR8 = AArch64MCRegisterClasses[AArch64::FPR8RegClassID]; 326 327 auto IsFPR = [&](const MCOperand &Op) { 328 if (!Op.isReg()) 329 return false; 330 auto Reg = Op.getReg(); 331 return FPR128.contains(Reg) || FPR64.contains(Reg) || FPR32.contains(Reg) || 332 FPR16.contains(Reg) || FPR8.contains(Reg); 333 }; 334 335 return llvm::any_of(MI, IsFPR); 336 } 337 338 static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) { 339 MCRegisterInfo *X = new MCRegisterInfo(); 340 InitAArch64MCRegisterInfo(X, AArch64::LR); 341 AArch64_MC::initLLVMToCVRegMapping(X); 342 return X; 343 } 344 345 static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI, 346 const Triple &TheTriple, 347 const MCTargetOptions &Options) { 348 MCAsmInfo *MAI; 349 if (TheTriple.isOSBinFormatMachO()) 350 MAI = new AArch64MCAsmInfoDarwin(TheTriple.getArch() == Triple::aarch64_32); 351 else if (TheTriple.isWindowsMSVCEnvironment()) 352 MAI = new AArch64MCAsmInfoMicrosoftCOFF(); 353 else if (TheTriple.isOSBinFormatCOFF()) 354 MAI = new AArch64MCAsmInfoGNUCOFF(); 355 else { 356 assert(TheTriple.isOSBinFormatELF() && "Invalid target"); 357 MAI = new AArch64MCAsmInfoELF(TheTriple); 358 } 359 360 // Initial state of the frame pointer is SP. 361 unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true); 362 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0); 363 MAI->addInitialFrameState(Inst); 364 365 return MAI; 366 } 367 368 static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T, 369 unsigned SyntaxVariant, 370 const MCAsmInfo &MAI, 371 const MCInstrInfo &MII, 372 const MCRegisterInfo &MRI) { 373 if (SyntaxVariant == 0) 374 return new AArch64InstPrinter(MAI, MII, MRI); 375 if (SyntaxVariant == 1) 376 return new AArch64AppleInstPrinter(MAI, MII, MRI); 377 378 return nullptr; 379 } 380 381 static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx, 382 std::unique_ptr<MCAsmBackend> &&TAB, 383 std::unique_ptr<MCObjectWriter> &&OW, 384 std::unique_ptr<MCCodeEmitter> &&Emitter) { 385 return createAArch64ELFStreamer(Ctx, std::move(TAB), std::move(OW), 386 std::move(Emitter)); 387 } 388 389 static MCStreamer * 390 createMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB, 391 std::unique_ptr<MCObjectWriter> &&OW, 392 std::unique_ptr<MCCodeEmitter> &&Emitter) { 393 return createMachOStreamer(Ctx, std::move(TAB), std::move(OW), 394 std::move(Emitter), /*ignore=*/false, 395 /*LabelSections*/ true); 396 } 397 398 static MCStreamer * 399 createWinCOFFStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB, 400 std::unique_ptr<MCObjectWriter> &&OW, 401 std::unique_ptr<MCCodeEmitter> &&Emitter) { 402 return createAArch64WinCOFFStreamer(Ctx, std::move(TAB), std::move(OW), 403 std::move(Emitter)); 404 } 405 406 namespace { 407 408 class AArch64MCInstrAnalysis : public MCInstrAnalysis { 409 public: 410 AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {} 411 412 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, 413 uint64_t &Target) const override { 414 // Search for a PC-relative argument. 415 // This will handle instructions like bcc (where the first argument is the 416 // condition code) and cbz (where it is a register). 417 const auto &Desc = Info->get(Inst.getOpcode()); 418 for (unsigned i = 0, e = Inst.getNumOperands(); i != e; i++) { 419 if (Desc.operands()[i].OperandType == MCOI::OPERAND_PCREL) { 420 int64_t Imm = Inst.getOperand(i).getImm(); 421 if (Inst.getOpcode() == AArch64::ADR) 422 Target = Addr + Imm; 423 else if (Inst.getOpcode() == AArch64::ADRP) 424 Target = (Addr & -4096) + Imm * 4096; 425 else 426 Target = Addr + Imm * 4; 427 return true; 428 } 429 } 430 return false; 431 } 432 433 bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst, 434 APInt &Mask) const override { 435 const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); 436 unsigned NumDefs = Desc.getNumDefs(); 437 unsigned NumImplicitDefs = Desc.implicit_defs().size(); 438 assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs && 439 "Unexpected number of bits in the mask!"); 440 // 32-bit General Purpose Register class. 441 const MCRegisterClass &GPR32RC = MRI.getRegClass(AArch64::GPR32RegClassID); 442 // Floating Point Register classes. 443 const MCRegisterClass &FPR8RC = MRI.getRegClass(AArch64::FPR8RegClassID); 444 const MCRegisterClass &FPR16RC = MRI.getRegClass(AArch64::FPR16RegClassID); 445 const MCRegisterClass &FPR32RC = MRI.getRegClass(AArch64::FPR32RegClassID); 446 const MCRegisterClass &FPR64RC = MRI.getRegClass(AArch64::FPR64RegClassID); 447 const MCRegisterClass &FPR128RC = 448 MRI.getRegClass(AArch64::FPR128RegClassID); 449 450 auto ClearsSuperReg = [=](unsigned RegID) { 451 // An update to the lower 32 bits of a 64 bit integer register is 452 // architecturally defined to zero extend the upper 32 bits on a write. 453 if (GPR32RC.contains(RegID)) 454 return true; 455 // SIMD&FP instructions operating on scalar data only acccess the lower 456 // bits of a register, the upper bits are zero extended on a write. For 457 // SIMD vector registers smaller than 128-bits, the upper 64-bits of the 458 // register are zero extended on a write. 459 // When VL is higher than 128 bits, any write to a SIMD&FP register sets 460 // bits higher than 128 to zero. 461 return FPR8RC.contains(RegID) || FPR16RC.contains(RegID) || 462 FPR32RC.contains(RegID) || FPR64RC.contains(RegID) || 463 FPR128RC.contains(RegID); 464 }; 465 466 Mask.clearAllBits(); 467 for (unsigned I = 0, E = NumDefs; I < E; ++I) { 468 const MCOperand &Op = Inst.getOperand(I); 469 if (ClearsSuperReg(Op.getReg())) 470 Mask.setBit(I); 471 } 472 473 for (unsigned I = 0, E = NumImplicitDefs; I < E; ++I) { 474 const MCPhysReg Reg = Desc.implicit_defs()[I]; 475 if (ClearsSuperReg(Reg)) 476 Mask.setBit(NumDefs + I); 477 } 478 479 return Mask.getBoolValue(); 480 } 481 482 std::vector<std::pair<uint64_t, uint64_t>> 483 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents, 484 const Triple &TargetTriple) const override { 485 // Do a lightweight parsing of PLT entries. 486 std::vector<std::pair<uint64_t, uint64_t>> Result; 487 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 7 < End; 488 Byte += 4) { 489 uint32_t Insn = support::endian::read32le(PltContents.data() + Byte); 490 uint64_t Off = 0; 491 // Check for optional bti c that prefixes adrp in BTI enabled entries 492 if (Insn == 0xd503245f) { 493 Off = 4; 494 Insn = support::endian::read32le(PltContents.data() + Byte + Off); 495 } 496 // Check for adrp. 497 if ((Insn & 0x9f000000) != 0x90000000) 498 continue; 499 Off += 4; 500 uint64_t Imm = (((PltSectionVA + Byte) >> 12) << 12) + 501 (((Insn >> 29) & 3) << 12) + (((Insn >> 5) & 0x3ffff) << 14); 502 uint32_t Insn2 = 503 support::endian::read32le(PltContents.data() + Byte + Off); 504 // Check for: ldr Xt, [Xn, #pimm]. 505 if (Insn2 >> 22 == 0x3e5) { 506 Imm += ((Insn2 >> 10) & 0xfff) << 3; 507 Result.push_back(std::make_pair(PltSectionVA + Byte, Imm)); 508 Byte += 4; 509 } 510 } 511 return Result; 512 } 513 }; 514 515 } // end anonymous namespace 516 517 static MCInstrAnalysis *createAArch64InstrAnalysis(const MCInstrInfo *Info) { 518 return new AArch64MCInstrAnalysis(Info); 519 } 520 521 // Force static initialization. 522 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64TargetMC() { 523 for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64beTarget(), 524 &getTheAArch64_32Target(), &getTheARM64Target(), 525 &getTheARM64_32Target()}) { 526 // Register the MC asm info. 527 RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo); 528 529 // Register the MC instruction info. 530 TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo); 531 532 // Register the MC register info. 533 TargetRegistry::RegisterMCRegInfo(*T, createAArch64MCRegisterInfo); 534 535 // Register the MC subtarget info. 536 TargetRegistry::RegisterMCSubtargetInfo(*T, createAArch64MCSubtargetInfo); 537 538 // Register the MC instruction analyzer. 539 TargetRegistry::RegisterMCInstrAnalysis(*T, createAArch64InstrAnalysis); 540 541 // Register the MC Code Emitter 542 TargetRegistry::RegisterMCCodeEmitter(*T, createAArch64MCCodeEmitter); 543 544 // Register the obj streamers. 545 TargetRegistry::RegisterELFStreamer(*T, createELFStreamer); 546 TargetRegistry::RegisterMachOStreamer(*T, createMachOStreamer); 547 TargetRegistry::RegisterCOFFStreamer(*T, createWinCOFFStreamer); 548 549 // Register the obj target streamer. 550 TargetRegistry::RegisterObjectTargetStreamer( 551 *T, createAArch64ObjectTargetStreamer); 552 553 // Register the asm streamer. 554 TargetRegistry::RegisterAsmTargetStreamer(*T, 555 createAArch64AsmTargetStreamer); 556 // Register the null streamer. 557 TargetRegistry::RegisterNullTargetStreamer(*T, 558 createAArch64NullTargetStreamer); 559 560 // Register the MCInstPrinter. 561 TargetRegistry::RegisterMCInstPrinter(*T, createAArch64MCInstPrinter); 562 } 563 564 // Register the asm backend. 565 for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64_32Target(), 566 &getTheARM64Target(), &getTheARM64_32Target()}) 567 TargetRegistry::RegisterMCAsmBackend(*T, createAArch64leAsmBackend); 568 TargetRegistry::RegisterMCAsmBackend(getTheAArch64beTarget(), 569 createAArch64beAsmBackend); 570 } 571