1 //===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This class prints an AArch64 MCInst to a .s file. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H 14 #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H 15 16 #include "MCTargetDesc/AArch64MCTargetDesc.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/MC/MCInstPrinter.h" 19 #include "../Utils/AArch64BaseInfo.h" 20 21 namespace llvm { 22 23 class AArch64InstPrinter : public MCInstPrinter { 24 public: 25 AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, 26 const MCRegisterInfo &MRI); 27 28 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, 29 const MCSubtargetInfo &STI, raw_ostream &O) override; 30 void printRegName(raw_ostream &OS, unsigned RegNo) const override; 31 32 // Autogenerated by tblgen. 33 std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override; 34 virtual void printInstruction(const MCInst *MI, uint64_t Address, 35 const MCSubtargetInfo &STI, raw_ostream &O); 36 virtual bool printAliasInstr(const MCInst *MI, uint64_t Address, 37 const MCSubtargetInfo &STI, raw_ostream &O); 38 virtual void printCustomAliasOperand(const MCInst *MI, uint64_t Address, 39 unsigned OpIdx, unsigned PrintMethodIdx, 40 const MCSubtargetInfo &STI, 41 raw_ostream &O); 42 43 virtual StringRef getRegName(unsigned RegNo) const { 44 return getRegisterName(RegNo); 45 } 46 47 static const char *getRegisterName(unsigned RegNo, 48 unsigned AltIdx = AArch64::NoRegAltName); 49 50 protected: 51 bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI, 52 raw_ostream &O); 53 // Operand printers 54 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 55 raw_ostream &O); 56 void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 57 raw_ostream &O); 58 void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 59 raw_ostream &O); 60 template <int Size> 61 void printSImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 62 raw_ostream &O); 63 template <typename T> void printImmSVE(T Value, raw_ostream &O); 64 void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm, 65 raw_ostream &O); 66 template <int Amount> 67 void printPostIncOperand(const MCInst *MI, unsigned OpNo, 68 const MCSubtargetInfo &STI, raw_ostream &O) { 69 printPostIncOperand(MI, OpNo, Amount, O); 70 } 71 72 void printVRegOperand(const MCInst *MI, unsigned OpNo, 73 const MCSubtargetInfo &STI, raw_ostream &O); 74 void printSysCROperand(const MCInst *MI, unsigned OpNo, 75 const MCSubtargetInfo &STI, raw_ostream &O); 76 void printAddSubImm(const MCInst *MI, unsigned OpNum, 77 const MCSubtargetInfo &STI, raw_ostream &O); 78 template <typename T> 79 void printLogicalImm(const MCInst *MI, unsigned OpNum, 80 const MCSubtargetInfo &STI, raw_ostream &O); 81 void printShifter(const MCInst *MI, unsigned OpNum, 82 const MCSubtargetInfo &STI, raw_ostream &O); 83 void printShiftedRegister(const MCInst *MI, unsigned OpNum, 84 const MCSubtargetInfo &STI, raw_ostream &O); 85 void printExtendedRegister(const MCInst *MI, unsigned OpNum, 86 const MCSubtargetInfo &STI, raw_ostream &O); 87 void printArithExtend(const MCInst *MI, unsigned OpNum, 88 const MCSubtargetInfo &STI, raw_ostream &O); 89 90 void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O, 91 char SrcRegKind, unsigned Width); 92 template <char SrcRegKind, unsigned Width> 93 void printMemExtend(const MCInst *MI, unsigned OpNum, 94 const MCSubtargetInfo &STI, raw_ostream &O) { 95 printMemExtend(MI, OpNum, O, SrcRegKind, Width); 96 } 97 template <bool SignedExtend, int ExtWidth, char SrcRegKind, char Suffix> 98 void printRegWithShiftExtend(const MCInst *MI, unsigned OpNum, 99 const MCSubtargetInfo &STI, raw_ostream &O); 100 void printCondCode(const MCInst *MI, unsigned OpNum, 101 const MCSubtargetInfo &STI, raw_ostream &O); 102 void printInverseCondCode(const MCInst *MI, unsigned OpNum, 103 const MCSubtargetInfo &STI, raw_ostream &O); 104 void printAlignedLabel(const MCInst *MI, uint64_t Address, unsigned OpNum, 105 const MCSubtargetInfo &STI, raw_ostream &O); 106 void printUImm12Offset(const MCInst *MI, unsigned OpNum, unsigned Scale, 107 raw_ostream &O); 108 void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale, 109 raw_ostream &O); 110 111 template <int Scale> 112 void printUImm12Offset(const MCInst *MI, unsigned OpNum, 113 const MCSubtargetInfo &STI, raw_ostream &O) { 114 printUImm12Offset(MI, OpNum, Scale, O); 115 } 116 117 template <int BitWidth> 118 void printAMIndexedWB(const MCInst *MI, unsigned OpNum, 119 const MCSubtargetInfo &STI, raw_ostream &O) { 120 printAMIndexedWB(MI, OpNum, BitWidth / 8, O); 121 } 122 123 void printAMNoIndex(const MCInst *MI, unsigned OpNum, 124 const MCSubtargetInfo &STI, raw_ostream &O); 125 126 template <int Scale> 127 void printImmScale(const MCInst *MI, unsigned OpNum, 128 const MCSubtargetInfo &STI, raw_ostream &O); 129 130 template <bool IsSVEPrefetch = false> 131 void printPrefetchOp(const MCInst *MI, unsigned OpNum, 132 const MCSubtargetInfo &STI, raw_ostream &O); 133 134 void printPSBHintOp(const MCInst *MI, unsigned OpNum, 135 const MCSubtargetInfo &STI, raw_ostream &O); 136 137 void printBTIHintOp(const MCInst *MI, unsigned OpNum, 138 const MCSubtargetInfo &STI, raw_ostream &O); 139 140 void printFPImmOperand(const MCInst *MI, unsigned OpNum, 141 const MCSubtargetInfo &STI, raw_ostream &O); 142 143 void printVectorList(const MCInst *MI, unsigned OpNum, 144 const MCSubtargetInfo &STI, raw_ostream &O, 145 StringRef LayoutSuffix); 146 147 /// Print a list of vector registers where the type suffix is implicit 148 /// (i.e. attached to the instruction rather than the registers). 149 void printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum, 150 const MCSubtargetInfo &STI, 151 raw_ostream &O); 152 153 template <unsigned NumLanes, char LaneKind> 154 void printTypedVectorList(const MCInst *MI, unsigned OpNum, 155 const MCSubtargetInfo &STI, raw_ostream &O); 156 157 void printVectorIndex(const MCInst *MI, unsigned OpNum, 158 const MCSubtargetInfo &STI, raw_ostream &O); 159 void printAdrpLabel(const MCInst *MI, uint64_t Address, unsigned OpNum, 160 const MCSubtargetInfo &STI, raw_ostream &O); 161 void printBarrierOption(const MCInst *MI, unsigned OpNum, 162 const MCSubtargetInfo &STI, raw_ostream &O); 163 void printBarriernXSOption(const MCInst *MI, unsigned OpNum, 164 const MCSubtargetInfo &STI, raw_ostream &O); 165 void printMSRSystemRegister(const MCInst *MI, unsigned OpNum, 166 const MCSubtargetInfo &STI, raw_ostream &O); 167 void printMRSSystemRegister(const MCInst *MI, unsigned OpNum, 168 const MCSubtargetInfo &STI, raw_ostream &O); 169 void printSystemPStateField(const MCInst *MI, unsigned OpNum, 170 const MCSubtargetInfo &STI, raw_ostream &O); 171 void printSIMDType10Operand(const MCInst *MI, unsigned OpNum, 172 const MCSubtargetInfo &STI, raw_ostream &O); 173 template<int64_t Angle, int64_t Remainder> 174 void printComplexRotationOp(const MCInst *MI, unsigned OpNo, 175 const MCSubtargetInfo &STI, raw_ostream &O); 176 template<unsigned size> 177 void printGPRSeqPairsClassOperand(const MCInst *MI, unsigned OpNum, 178 const MCSubtargetInfo &STI, 179 raw_ostream &O); 180 template <typename T> 181 void printImm8OptLsl(const MCInst *MI, unsigned OpNum, 182 const MCSubtargetInfo &STI, raw_ostream &O); 183 template <typename T> 184 void printSVELogicalImm(const MCInst *MI, unsigned OpNum, 185 const MCSubtargetInfo &STI, raw_ostream &O); 186 void printSVEPattern(const MCInst *MI, unsigned OpNum, 187 const MCSubtargetInfo &STI, raw_ostream &O); 188 template <char = 0> 189 void printSVERegOp(const MCInst *MI, unsigned OpNum, 190 const MCSubtargetInfo &STI, raw_ostream &O); 191 void printGPR64as32(const MCInst *MI, unsigned OpNum, 192 const MCSubtargetInfo &STI, raw_ostream &O); 193 void printGPR64x8(const MCInst *MI, unsigned OpNum, 194 const MCSubtargetInfo &STI, raw_ostream &O); 195 template <int Width> 196 void printZPRasFPR(const MCInst *MI, unsigned OpNum, 197 const MCSubtargetInfo &STI, raw_ostream &O); 198 template <unsigned ImmIs0, unsigned ImmIs1> 199 void printExactFPImm(const MCInst *MI, unsigned OpNum, 200 const MCSubtargetInfo &STI, raw_ostream &O); 201 }; 202 203 class AArch64AppleInstPrinter : public AArch64InstPrinter { 204 public: 205 AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, 206 const MCRegisterInfo &MRI); 207 208 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, 209 const MCSubtargetInfo &STI, raw_ostream &O) override; 210 211 std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override; 212 void printInstruction(const MCInst *MI, uint64_t Address, 213 const MCSubtargetInfo &STI, raw_ostream &O) override; 214 bool printAliasInstr(const MCInst *MI, uint64_t Address, 215 const MCSubtargetInfo &STI, raw_ostream &O) override; 216 void printCustomAliasOperand(const MCInst *MI, uint64_t Address, 217 unsigned OpIdx, unsigned PrintMethodIdx, 218 const MCSubtargetInfo &STI, 219 raw_ostream &O) override; 220 221 StringRef getRegName(unsigned RegNo) const override { 222 return getRegisterName(RegNo); 223 } 224 225 static const char *getRegisterName(unsigned RegNo, 226 unsigned AltIdx = AArch64::NoRegAltName); 227 }; 228 229 } // end namespace llvm 230 231 #endif // LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H 232