1 //===-- AArch64ELFObjectWriter.cpp - AArch64 ELF Writer -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file handles ELF-specific object emission, converting LLVM's internal 10 // fixups into the appropriate relocations. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MCTargetDesc/AArch64FixupKinds.h" 15 #include "MCTargetDesc/AArch64MCExpr.h" 16 #include "MCTargetDesc/AArch64MCTargetDesc.h" 17 #include "llvm/BinaryFormat/ELF.h" 18 #include "llvm/MC/MCContext.h" 19 #include "llvm/MC/MCELFObjectWriter.h" 20 #include "llvm/MC/MCFixup.h" 21 #include "llvm/MC/MCObjectWriter.h" 22 #include "llvm/MC/MCValue.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include <cassert> 25 #include <cstdint> 26 27 using namespace llvm; 28 29 namespace { 30 31 class AArch64ELFObjectWriter : public MCELFObjectTargetWriter { 32 public: 33 AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32); 34 35 ~AArch64ELFObjectWriter() override = default; 36 37 MCSectionELF *getMemtagRelocsSection(MCContext &Ctx) const override; 38 39 protected: 40 unsigned getRelocType(MCContext &Ctx, const MCValue &Target, 41 const MCFixup &Fixup, bool IsPCRel) const override; 42 bool needsRelocateWithSymbol(const MCValue &Val, const MCSymbol &Sym, 43 unsigned Type) const override; 44 bool IsILP32; 45 }; 46 47 } // end anonymous namespace 48 49 AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32) 50 : MCELFObjectTargetWriter(/*Is64Bit*/ !IsILP32, OSABI, ELF::EM_AARCH64, 51 /*HasRelocationAddend*/ true), 52 IsILP32(IsILP32) {} 53 54 #define R_CLS(rtype) \ 55 IsILP32 ? ELF::R_AARCH64_P32_##rtype : ELF::R_AARCH64_##rtype 56 #define BAD_ILP32_MOV(lp64rtype) \ 57 "ILP32 absolute MOV relocation not " \ 58 "supported (LP64 eqv: " #lp64rtype ")" 59 60 // assumes IsILP32 is true 61 static bool isNonILP32reloc(const MCFixup &Fixup, 62 AArch64MCExpr::VariantKind RefKind, 63 MCContext &Ctx) { 64 if (Fixup.getTargetKind() != AArch64::fixup_aarch64_movw) 65 return false; 66 switch (RefKind) { 67 case AArch64MCExpr::VK_ABS_G3: 68 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G3)); 69 return true; 70 case AArch64MCExpr::VK_ABS_G2: 71 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2)); 72 return true; 73 case AArch64MCExpr::VK_ABS_G2_S: 74 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G2)); 75 return true; 76 case AArch64MCExpr::VK_ABS_G2_NC: 77 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2_NC)); 78 return true; 79 case AArch64MCExpr::VK_ABS_G1_S: 80 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G1)); 81 return true; 82 case AArch64MCExpr::VK_ABS_G1_NC: 83 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G1_NC)); 84 return true; 85 case AArch64MCExpr::VK_DTPREL_G2: 86 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G2)); 87 return true; 88 case AArch64MCExpr::VK_DTPREL_G1_NC: 89 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G1_NC)); 90 return true; 91 case AArch64MCExpr::VK_TPREL_G2: 92 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G2)); 93 return true; 94 case AArch64MCExpr::VK_TPREL_G1_NC: 95 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G1_NC)); 96 return true; 97 case AArch64MCExpr::VK_GOTTPREL_G1: 98 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G1)); 99 return true; 100 case AArch64MCExpr::VK_GOTTPREL_G0_NC: 101 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G0_NC)); 102 return true; 103 default: 104 return false; 105 } 106 return false; 107 } 108 109 unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx, 110 const MCValue &Target, 111 const MCFixup &Fixup, 112 bool IsPCRel) const { 113 unsigned Kind = Fixup.getTargetKind(); 114 if (Kind >= FirstLiteralRelocationKind) 115 return Kind - FirstLiteralRelocationKind; 116 AArch64MCExpr::VariantKind RefKind = 117 static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind()); 118 AArch64MCExpr::VariantKind SymLoc = AArch64MCExpr::getSymbolLoc(RefKind); 119 bool IsNC = AArch64MCExpr::isNotChecked(RefKind); 120 121 assert((!Target.getSymA() || 122 Target.getSymA()->getKind() == MCSymbolRefExpr::VK_None || 123 Target.getSymA()->getKind() == MCSymbolRefExpr::VK_PLT || 124 Target.getSymA()->getKind() == MCSymbolRefExpr::VK_GOTPCREL) && 125 "Should only be expression-level modifiers here"); 126 127 assert((!Target.getSymB() || 128 Target.getSymB()->getKind() == MCSymbolRefExpr::VK_None) && 129 "Should only be expression-level modifiers here"); 130 131 if (IsPCRel) { 132 switch (Kind) { 133 case FK_Data_1: 134 Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported"); 135 return ELF::R_AARCH64_NONE; 136 case FK_Data_2: 137 return R_CLS(PREL16); 138 case FK_Data_4: { 139 return Target.getAccessVariant() == MCSymbolRefExpr::VK_PLT 140 ? R_CLS(PLT32) 141 : R_CLS(PREL32); 142 } 143 case FK_Data_8: 144 if (IsILP32) { 145 Ctx.reportError(Fixup.getLoc(), 146 "ILP32 8 byte PC relative data " 147 "relocation not supported (LP64 eqv: PREL64)"); 148 return ELF::R_AARCH64_NONE; 149 } 150 return ELF::R_AARCH64_PREL64; 151 case AArch64::fixup_aarch64_pcrel_adr_imm21: 152 if (SymLoc != AArch64MCExpr::VK_ABS) 153 Ctx.reportError(Fixup.getLoc(), 154 "invalid symbol kind for ADR relocation"); 155 return R_CLS(ADR_PREL_LO21); 156 case AArch64::fixup_aarch64_pcrel_adrp_imm21: 157 if (SymLoc == AArch64MCExpr::VK_ABS && !IsNC) 158 return R_CLS(ADR_PREL_PG_HI21); 159 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) { 160 if (IsILP32) { 161 Ctx.reportError(Fixup.getLoc(), 162 "invalid fixup for 32-bit pcrel ADRP instruction " 163 "VK_ABS VK_NC"); 164 return ELF::R_AARCH64_NONE; 165 } 166 return ELF::R_AARCH64_ADR_PREL_PG_HI21_NC; 167 } 168 if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC) 169 return R_CLS(ADR_GOT_PAGE); 170 if (SymLoc == AArch64MCExpr::VK_GOTTPREL && !IsNC) 171 return R_CLS(TLSIE_ADR_GOTTPREL_PAGE21); 172 if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC) 173 return R_CLS(TLSDESC_ADR_PAGE21); 174 Ctx.reportError(Fixup.getLoc(), 175 "invalid symbol kind for ADRP relocation"); 176 return ELF::R_AARCH64_NONE; 177 case AArch64::fixup_aarch64_pcrel_branch26: 178 return R_CLS(JUMP26); 179 case AArch64::fixup_aarch64_pcrel_call26: 180 return R_CLS(CALL26); 181 case AArch64::fixup_aarch64_ldr_pcrel_imm19: 182 if (SymLoc == AArch64MCExpr::VK_GOTTPREL) 183 return R_CLS(TLSIE_LD_GOTTPREL_PREL19); 184 if (SymLoc == AArch64MCExpr::VK_GOT) 185 return R_CLS(GOT_LD_PREL19); 186 return R_CLS(LD_PREL_LO19); 187 case AArch64::fixup_aarch64_pcrel_branch14: 188 return R_CLS(TSTBR14); 189 case AArch64::fixup_aarch64_pcrel_branch16: 190 Ctx.reportError(Fixup.getLoc(), 191 "relocation of PAC/AUT instructions is not supported"); 192 return ELF::R_AARCH64_NONE; 193 case AArch64::fixup_aarch64_pcrel_branch19: 194 return R_CLS(CONDBR19); 195 default: 196 Ctx.reportError(Fixup.getLoc(), "Unsupported pc-relative fixup kind"); 197 return ELF::R_AARCH64_NONE; 198 } 199 } else { 200 if (IsILP32 && isNonILP32reloc(Fixup, RefKind, Ctx)) 201 return ELF::R_AARCH64_NONE; 202 switch (Fixup.getTargetKind()) { 203 case FK_Data_1: 204 Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported"); 205 return ELF::R_AARCH64_NONE; 206 case FK_Data_2: 207 return R_CLS(ABS16); 208 case FK_Data_4: 209 return (!IsILP32 && 210 Target.getAccessVariant() == MCSymbolRefExpr::VK_GOTPCREL) 211 ? ELF::R_AARCH64_GOTPCREL32 212 : R_CLS(ABS32); 213 case FK_Data_8: { 214 bool IsAuth = (RefKind == AArch64MCExpr::VK_AUTH || 215 RefKind == AArch64MCExpr::VK_AUTHADDR); 216 if (IsILP32) { 217 Ctx.reportError(Fixup.getLoc(), 218 Twine("ILP32 8 byte absolute data " 219 "relocation not supported (LP64 eqv: ") + 220 (IsAuth ? "AUTH_ABS64" : "ABS64") + Twine(')')); 221 return ELF::R_AARCH64_NONE; 222 } 223 return (IsAuth ? ELF::R_AARCH64_AUTH_ABS64 : ELF::R_AARCH64_ABS64); 224 } 225 case AArch64::fixup_aarch64_add_imm12: 226 if (RefKind == AArch64MCExpr::VK_DTPREL_HI12) 227 return R_CLS(TLSLD_ADD_DTPREL_HI12); 228 if (RefKind == AArch64MCExpr::VK_TPREL_HI12) 229 return R_CLS(TLSLE_ADD_TPREL_HI12); 230 if (RefKind == AArch64MCExpr::VK_DTPREL_LO12_NC) 231 return R_CLS(TLSLD_ADD_DTPREL_LO12_NC); 232 if (RefKind == AArch64MCExpr::VK_DTPREL_LO12) 233 return R_CLS(TLSLD_ADD_DTPREL_LO12); 234 if (RefKind == AArch64MCExpr::VK_TPREL_LO12_NC) 235 return R_CLS(TLSLE_ADD_TPREL_LO12_NC); 236 if (RefKind == AArch64MCExpr::VK_TPREL_LO12) 237 return R_CLS(TLSLE_ADD_TPREL_LO12); 238 if (RefKind == AArch64MCExpr::VK_TLSDESC_LO12) 239 return R_CLS(TLSDESC_ADD_LO12); 240 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) 241 return R_CLS(ADD_ABS_LO12_NC); 242 243 Ctx.reportError(Fixup.getLoc(), 244 "invalid fixup for add (uimm12) instruction"); 245 return ELF::R_AARCH64_NONE; 246 case AArch64::fixup_aarch64_ldst_imm12_scale1: 247 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) 248 return R_CLS(LDST8_ABS_LO12_NC); 249 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC) 250 return R_CLS(TLSLD_LDST8_DTPREL_LO12); 251 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC) 252 return R_CLS(TLSLD_LDST8_DTPREL_LO12_NC); 253 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC) 254 return R_CLS(TLSLE_LDST8_TPREL_LO12); 255 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC) 256 return R_CLS(TLSLE_LDST8_TPREL_LO12_NC); 257 258 Ctx.reportError(Fixup.getLoc(), 259 "invalid fixup for 8-bit load/store instruction"); 260 return ELF::R_AARCH64_NONE; 261 case AArch64::fixup_aarch64_ldst_imm12_scale2: 262 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) 263 return R_CLS(LDST16_ABS_LO12_NC); 264 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC) 265 return R_CLS(TLSLD_LDST16_DTPREL_LO12); 266 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC) 267 return R_CLS(TLSLD_LDST16_DTPREL_LO12_NC); 268 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC) 269 return R_CLS(TLSLE_LDST16_TPREL_LO12); 270 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC) 271 return R_CLS(TLSLE_LDST16_TPREL_LO12_NC); 272 273 Ctx.reportError(Fixup.getLoc(), 274 "invalid fixup for 16-bit load/store instruction"); 275 return ELF::R_AARCH64_NONE; 276 case AArch64::fixup_aarch64_ldst_imm12_scale4: 277 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) 278 return R_CLS(LDST32_ABS_LO12_NC); 279 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC) 280 return R_CLS(TLSLD_LDST32_DTPREL_LO12); 281 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC) 282 return R_CLS(TLSLD_LDST32_DTPREL_LO12_NC); 283 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC) 284 return R_CLS(TLSLE_LDST32_TPREL_LO12); 285 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC) 286 return R_CLS(TLSLE_LDST32_TPREL_LO12_NC); 287 if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) { 288 if (IsILP32) 289 return ELF::R_AARCH64_P32_LD32_GOT_LO12_NC; 290 Ctx.reportError(Fixup.getLoc(), 291 "LP64 4 byte unchecked GOT load/store relocation " 292 "not supported (ILP32 eqv: LD32_GOT_LO12_NC"); 293 return ELF::R_AARCH64_NONE; 294 } 295 if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC) { 296 if (IsILP32) { 297 Ctx.reportError(Fixup.getLoc(), 298 "ILP32 4 byte checked GOT load/store relocation " 299 "not supported (unchecked eqv: LD32_GOT_LO12_NC)"); 300 } else { 301 Ctx.reportError(Fixup.getLoc(), 302 "LP64 4 byte checked GOT load/store relocation " 303 "not supported (unchecked/ILP32 eqv: " 304 "LD32_GOT_LO12_NC)"); 305 } 306 return ELF::R_AARCH64_NONE; 307 } 308 if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) { 309 if (IsILP32) 310 return ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC; 311 Ctx.reportError(Fixup.getLoc(), "LP64 32-bit load/store " 312 "relocation not supported (ILP32 eqv: " 313 "TLSIE_LD32_GOTTPREL_LO12_NC)"); 314 return ELF::R_AARCH64_NONE; 315 } 316 if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC) { 317 if (IsILP32) 318 return ELF::R_AARCH64_P32_TLSDESC_LD32_LO12; 319 Ctx.reportError(Fixup.getLoc(), 320 "LP64 4 byte TLSDESC load/store relocation " 321 "not supported (ILP32 eqv: TLSDESC_LD64_LO12)"); 322 return ELF::R_AARCH64_NONE; 323 } 324 325 Ctx.reportError(Fixup.getLoc(), 326 "invalid fixup for 32-bit load/store instruction " 327 "fixup_aarch64_ldst_imm12_scale4"); 328 return ELF::R_AARCH64_NONE; 329 case AArch64::fixup_aarch64_ldst_imm12_scale8: 330 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) 331 return R_CLS(LDST64_ABS_LO12_NC); 332 if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) { 333 AArch64MCExpr::VariantKind AddressLoc = 334 AArch64MCExpr::getAddressFrag(RefKind); 335 if (!IsILP32) { 336 if (AddressLoc == AArch64MCExpr::VK_LO15) 337 return ELF::R_AARCH64_LD64_GOTPAGE_LO15; 338 return ELF::R_AARCH64_LD64_GOT_LO12_NC; 339 } 340 Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store " 341 "relocation not supported (LP64 eqv: " 342 "LD64_GOT_LO12_NC)"); 343 return ELF::R_AARCH64_NONE; 344 } 345 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC) 346 return R_CLS(TLSLD_LDST64_DTPREL_LO12); 347 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC) 348 return R_CLS(TLSLD_LDST64_DTPREL_LO12_NC); 349 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC) 350 return R_CLS(TLSLE_LDST64_TPREL_LO12); 351 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC) 352 return R_CLS(TLSLE_LDST64_TPREL_LO12_NC); 353 if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) { 354 if (!IsILP32) 355 return ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC; 356 Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store " 357 "relocation not supported (LP64 eqv: " 358 "TLSIE_LD64_GOTTPREL_LO12_NC)"); 359 return ELF::R_AARCH64_NONE; 360 } 361 if (SymLoc == AArch64MCExpr::VK_TLSDESC) { 362 if (!IsILP32) 363 return ELF::R_AARCH64_TLSDESC_LD64_LO12; 364 Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store " 365 "relocation not supported (LP64 eqv: " 366 "TLSDESC_LD64_LO12)"); 367 return ELF::R_AARCH64_NONE; 368 } 369 Ctx.reportError(Fixup.getLoc(), 370 "invalid fixup for 64-bit load/store instruction"); 371 return ELF::R_AARCH64_NONE; 372 case AArch64::fixup_aarch64_ldst_imm12_scale16: 373 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) 374 return R_CLS(LDST128_ABS_LO12_NC); 375 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC) 376 return R_CLS(TLSLD_LDST128_DTPREL_LO12); 377 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC) 378 return R_CLS(TLSLD_LDST128_DTPREL_LO12_NC); 379 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC) 380 return R_CLS(TLSLE_LDST128_TPREL_LO12); 381 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC) 382 return R_CLS(TLSLE_LDST128_TPREL_LO12_NC); 383 384 Ctx.reportError(Fixup.getLoc(), 385 "invalid fixup for 128-bit load/store instruction"); 386 return ELF::R_AARCH64_NONE; 387 // ILP32 case not reached here, tested with isNonILP32reloc 388 case AArch64::fixup_aarch64_movw: 389 if (RefKind == AArch64MCExpr::VK_ABS_G3) 390 return ELF::R_AARCH64_MOVW_UABS_G3; 391 if (RefKind == AArch64MCExpr::VK_ABS_G2) 392 return ELF::R_AARCH64_MOVW_UABS_G2; 393 if (RefKind == AArch64MCExpr::VK_ABS_G2_S) 394 return ELF::R_AARCH64_MOVW_SABS_G2; 395 if (RefKind == AArch64MCExpr::VK_ABS_G2_NC) 396 return ELF::R_AARCH64_MOVW_UABS_G2_NC; 397 if (RefKind == AArch64MCExpr::VK_ABS_G1) 398 return R_CLS(MOVW_UABS_G1); 399 if (RefKind == AArch64MCExpr::VK_ABS_G1_S) 400 return ELF::R_AARCH64_MOVW_SABS_G1; 401 if (RefKind == AArch64MCExpr::VK_ABS_G1_NC) 402 return ELF::R_AARCH64_MOVW_UABS_G1_NC; 403 if (RefKind == AArch64MCExpr::VK_ABS_G0) 404 return R_CLS(MOVW_UABS_G0); 405 if (RefKind == AArch64MCExpr::VK_ABS_G0_S) 406 return R_CLS(MOVW_SABS_G0); 407 if (RefKind == AArch64MCExpr::VK_ABS_G0_NC) 408 return R_CLS(MOVW_UABS_G0_NC); 409 if (RefKind == AArch64MCExpr::VK_PREL_G3) 410 return ELF::R_AARCH64_MOVW_PREL_G3; 411 if (RefKind == AArch64MCExpr::VK_PREL_G2) 412 return ELF::R_AARCH64_MOVW_PREL_G2; 413 if (RefKind == AArch64MCExpr::VK_PREL_G2_NC) 414 return ELF::R_AARCH64_MOVW_PREL_G2_NC; 415 if (RefKind == AArch64MCExpr::VK_PREL_G1) 416 return R_CLS(MOVW_PREL_G1); 417 if (RefKind == AArch64MCExpr::VK_PREL_G1_NC) 418 return ELF::R_AARCH64_MOVW_PREL_G1_NC; 419 if (RefKind == AArch64MCExpr::VK_PREL_G0) 420 return R_CLS(MOVW_PREL_G0); 421 if (RefKind == AArch64MCExpr::VK_PREL_G0_NC) 422 return R_CLS(MOVW_PREL_G0_NC); 423 if (RefKind == AArch64MCExpr::VK_DTPREL_G2) 424 return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G2; 425 if (RefKind == AArch64MCExpr::VK_DTPREL_G1) 426 return R_CLS(TLSLD_MOVW_DTPREL_G1); 427 if (RefKind == AArch64MCExpr::VK_DTPREL_G1_NC) 428 return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC; 429 if (RefKind == AArch64MCExpr::VK_DTPREL_G0) 430 return R_CLS(TLSLD_MOVW_DTPREL_G0); 431 if (RefKind == AArch64MCExpr::VK_DTPREL_G0_NC) 432 return R_CLS(TLSLD_MOVW_DTPREL_G0_NC); 433 if (RefKind == AArch64MCExpr::VK_TPREL_G2) 434 return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G2; 435 if (RefKind == AArch64MCExpr::VK_TPREL_G1) 436 return R_CLS(TLSLE_MOVW_TPREL_G1); 437 if (RefKind == AArch64MCExpr::VK_TPREL_G1_NC) 438 return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G1_NC; 439 if (RefKind == AArch64MCExpr::VK_TPREL_G0) 440 return R_CLS(TLSLE_MOVW_TPREL_G0); 441 if (RefKind == AArch64MCExpr::VK_TPREL_G0_NC) 442 return R_CLS(TLSLE_MOVW_TPREL_G0_NC); 443 if (RefKind == AArch64MCExpr::VK_GOTTPREL_G1) 444 return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G1; 445 if (RefKind == AArch64MCExpr::VK_GOTTPREL_G0_NC) 446 return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC; 447 Ctx.reportError(Fixup.getLoc(), 448 "invalid fixup for movz/movk instruction"); 449 return ELF::R_AARCH64_NONE; 450 default: 451 Ctx.reportError(Fixup.getLoc(), "Unknown ELF relocation type"); 452 return ELF::R_AARCH64_NONE; 453 } 454 } 455 456 llvm_unreachable("Unimplemented fixup -> relocation"); 457 } 458 459 bool AArch64ELFObjectWriter::needsRelocateWithSymbol(const MCValue &Val, 460 const MCSymbol &, 461 unsigned) const { 462 return (Val.getRefKind() & AArch64MCExpr::VK_GOT) == AArch64MCExpr::VK_GOT; 463 } 464 465 MCSectionELF * 466 AArch64ELFObjectWriter::getMemtagRelocsSection(MCContext &Ctx) const { 467 return Ctx.getELFSection(".memtag.globals.static", 468 ELF::SHT_AARCH64_MEMTAG_GLOBALS_STATIC, 0); 469 } 470 471 std::unique_ptr<MCObjectTargetWriter> 472 llvm::createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32) { 473 return std::make_unique<AArch64ELFObjectWriter>(OSABI, IsILP32); 474 } 475