1 //===-- AArch64AsmBackend.cpp - AArch64 Assembler Backend -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/AArch64FixupKinds.h" 10 #include "MCTargetDesc/AArch64MCExpr.h" 11 #include "MCTargetDesc/AArch64MCTargetDesc.h" 12 #include "Utils/AArch64BaseInfo.h" 13 #include "llvm/ADT/Triple.h" 14 #include "llvm/BinaryFormat/MachO.h" 15 #include "llvm/MC/MCAsmBackend.h" 16 #include "llvm/MC/MCAssembler.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDirectives.h" 19 #include "llvm/MC/MCELFObjectWriter.h" 20 #include "llvm/MC/MCFixupKindInfo.h" 21 #include "llvm/MC/MCObjectWriter.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSectionELF.h" 24 #include "llvm/MC/MCSectionMachO.h" 25 #include "llvm/MC/MCTargetOptions.h" 26 #include "llvm/MC/MCValue.h" 27 #include "llvm/Support/ErrorHandling.h" 28 #include "llvm/Support/TargetRegistry.h" 29 using namespace llvm; 30 31 namespace { 32 33 class AArch64AsmBackend : public MCAsmBackend { 34 static const unsigned PCRelFlagVal = 35 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits | MCFixupKindInfo::FKF_IsPCRel; 36 Triple TheTriple; 37 38 public: 39 AArch64AsmBackend(const Target &T, const Triple &TT, bool IsLittleEndian) 40 : MCAsmBackend(IsLittleEndian ? support::little : support::big), 41 TheTriple(TT) {} 42 43 unsigned getNumFixupKinds() const override { 44 return AArch64::NumTargetFixupKinds; 45 } 46 47 Optional<MCFixupKind> getFixupKind(StringRef Name) const override; 48 49 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { 50 const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = { 51 // This table *must* be in the order that the fixup_* kinds are defined 52 // in AArch64FixupKinds.h. 53 // 54 // Name Offset (bits) Size (bits) Flags 55 {"fixup_aarch64_pcrel_adr_imm21", 0, 32, PCRelFlagVal}, 56 {"fixup_aarch64_pcrel_adrp_imm21", 0, 32, PCRelFlagVal}, 57 {"fixup_aarch64_add_imm12", 10, 12, 0}, 58 {"fixup_aarch64_ldst_imm12_scale1", 10, 12, 0}, 59 {"fixup_aarch64_ldst_imm12_scale2", 10, 12, 0}, 60 {"fixup_aarch64_ldst_imm12_scale4", 10, 12, 0}, 61 {"fixup_aarch64_ldst_imm12_scale8", 10, 12, 0}, 62 {"fixup_aarch64_ldst_imm12_scale16", 10, 12, 0}, 63 {"fixup_aarch64_ldr_pcrel_imm19", 5, 19, PCRelFlagVal}, 64 {"fixup_aarch64_movw", 5, 16, 0}, 65 {"fixup_aarch64_pcrel_branch14", 5, 14, PCRelFlagVal}, 66 {"fixup_aarch64_pcrel_branch19", 5, 19, PCRelFlagVal}, 67 {"fixup_aarch64_pcrel_branch26", 0, 26, PCRelFlagVal}, 68 {"fixup_aarch64_pcrel_call26", 0, 26, PCRelFlagVal}, 69 {"fixup_aarch64_tlsdesc_call", 0, 0, 0}}; 70 71 if (Kind < FirstTargetFixupKind) 72 return MCAsmBackend::getFixupKindInfo(Kind); 73 74 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 75 "Invalid kind!"); 76 return Infos[Kind - FirstTargetFixupKind]; 77 } 78 79 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 80 const MCValue &Target, MutableArrayRef<char> Data, 81 uint64_t Value, bool IsResolved, 82 const MCSubtargetInfo *STI) const override; 83 84 bool mayNeedRelaxation(const MCInst &Inst, 85 const MCSubtargetInfo &STI) const override; 86 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, 87 const MCRelaxableFragment *DF, 88 const MCAsmLayout &Layout) const override; 89 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, 90 MCInst &Res) const override; 91 bool writeNopData(raw_ostream &OS, uint64_t Count) const override; 92 93 void HandleAssemblerFlag(MCAssemblerFlag Flag) {} 94 95 unsigned getPointerSize() const { return 8; } 96 97 unsigned getFixupKindContainereSizeInBytes(unsigned Kind) const; 98 99 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, 100 const MCValue &Target) override; 101 }; 102 103 } // end anonymous namespace 104 105 /// The number of bytes the fixup may change. 106 static unsigned getFixupKindNumBytes(unsigned Kind) { 107 switch (Kind) { 108 default: 109 llvm_unreachable("Unknown fixup kind!"); 110 111 case FK_NONE: 112 case AArch64::fixup_aarch64_tlsdesc_call: 113 return 0; 114 115 case FK_Data_1: 116 return 1; 117 118 case FK_Data_2: 119 case FK_SecRel_2: 120 return 2; 121 122 case AArch64::fixup_aarch64_movw: 123 case AArch64::fixup_aarch64_pcrel_branch14: 124 case AArch64::fixup_aarch64_add_imm12: 125 case AArch64::fixup_aarch64_ldst_imm12_scale1: 126 case AArch64::fixup_aarch64_ldst_imm12_scale2: 127 case AArch64::fixup_aarch64_ldst_imm12_scale4: 128 case AArch64::fixup_aarch64_ldst_imm12_scale8: 129 case AArch64::fixup_aarch64_ldst_imm12_scale16: 130 case AArch64::fixup_aarch64_ldr_pcrel_imm19: 131 case AArch64::fixup_aarch64_pcrel_branch19: 132 return 3; 133 134 case AArch64::fixup_aarch64_pcrel_adr_imm21: 135 case AArch64::fixup_aarch64_pcrel_adrp_imm21: 136 case AArch64::fixup_aarch64_pcrel_branch26: 137 case AArch64::fixup_aarch64_pcrel_call26: 138 case FK_Data_4: 139 case FK_SecRel_4: 140 return 4; 141 142 case FK_Data_8: 143 return 8; 144 } 145 } 146 147 static unsigned AdrImmBits(unsigned Value) { 148 unsigned lo2 = Value & 0x3; 149 unsigned hi19 = (Value & 0x1ffffc) >> 2; 150 return (hi19 << 5) | (lo2 << 29); 151 } 152 153 static bool valueFitsIntoFixupKind(unsigned Kind, uint64_t Value) { 154 unsigned NumBits; 155 switch(Kind) { 156 case FK_Data_1: NumBits = 8; break; 157 case FK_Data_2: NumBits = 16; break; 158 case FK_Data_4: NumBits = 32; break; 159 case FK_Data_8: NumBits = 64; break; 160 default: return true; 161 } 162 return isUIntN(NumBits, Value) || 163 isIntN(NumBits, static_cast<int64_t>(Value)); 164 } 165 166 static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, 167 uint64_t Value, MCContext &Ctx, 168 const Triple &TheTriple, bool IsResolved) { 169 int64_t SignedValue = static_cast<int64_t>(Value); 170 switch (Fixup.getTargetKind()) { 171 default: 172 llvm_unreachable("Unknown fixup kind!"); 173 case AArch64::fixup_aarch64_pcrel_adr_imm21: 174 if (SignedValue > 2097151 || SignedValue < -2097152) 175 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 176 return AdrImmBits(Value & 0x1fffffULL); 177 case AArch64::fixup_aarch64_pcrel_adrp_imm21: 178 assert(!IsResolved); 179 if (TheTriple.isOSBinFormatCOFF()) 180 return AdrImmBits(Value & 0x1fffffULL); 181 return AdrImmBits((Value & 0x1fffff000ULL) >> 12); 182 case AArch64::fixup_aarch64_ldr_pcrel_imm19: 183 case AArch64::fixup_aarch64_pcrel_branch19: 184 // Signed 21-bit immediate 185 if (SignedValue > 2097151 || SignedValue < -2097152) 186 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 187 if (Value & 0x3) 188 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned"); 189 // Low two bits are not encoded. 190 return (Value >> 2) & 0x7ffff; 191 case AArch64::fixup_aarch64_add_imm12: 192 case AArch64::fixup_aarch64_ldst_imm12_scale1: 193 if (TheTriple.isOSBinFormatCOFF() && !IsResolved) 194 Value &= 0xfff; 195 // Unsigned 12-bit immediate 196 if (Value >= 0x1000) 197 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 198 return Value; 199 case AArch64::fixup_aarch64_ldst_imm12_scale2: 200 if (TheTriple.isOSBinFormatCOFF() && !IsResolved) 201 Value &= 0xfff; 202 // Unsigned 12-bit immediate which gets multiplied by 2 203 if (Value >= 0x2000) 204 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 205 if (Value & 0x1) 206 Ctx.reportError(Fixup.getLoc(), "fixup must be 2-byte aligned"); 207 return Value >> 1; 208 case AArch64::fixup_aarch64_ldst_imm12_scale4: 209 if (TheTriple.isOSBinFormatCOFF() && !IsResolved) 210 Value &= 0xfff; 211 // Unsigned 12-bit immediate which gets multiplied by 4 212 if (Value >= 0x4000) 213 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 214 if (Value & 0x3) 215 Ctx.reportError(Fixup.getLoc(), "fixup must be 4-byte aligned"); 216 return Value >> 2; 217 case AArch64::fixup_aarch64_ldst_imm12_scale8: 218 if (TheTriple.isOSBinFormatCOFF() && !IsResolved) 219 Value &= 0xfff; 220 // Unsigned 12-bit immediate which gets multiplied by 8 221 if (Value >= 0x8000) 222 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 223 if (Value & 0x7) 224 Ctx.reportError(Fixup.getLoc(), "fixup must be 8-byte aligned"); 225 return Value >> 3; 226 case AArch64::fixup_aarch64_ldst_imm12_scale16: 227 if (TheTriple.isOSBinFormatCOFF() && !IsResolved) 228 Value &= 0xfff; 229 // Unsigned 12-bit immediate which gets multiplied by 16 230 if (Value >= 0x10000) 231 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 232 if (Value & 0xf) 233 Ctx.reportError(Fixup.getLoc(), "fixup must be 16-byte aligned"); 234 return Value >> 4; 235 case AArch64::fixup_aarch64_movw: { 236 AArch64MCExpr::VariantKind RefKind = 237 static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind()); 238 if (AArch64MCExpr::getSymbolLoc(RefKind) != AArch64MCExpr::VK_ABS && 239 AArch64MCExpr::getSymbolLoc(RefKind) != AArch64MCExpr::VK_SABS) { 240 // VK_GOTTPREL, VK_TPREL, VK_DTPREL are movw fixups, but they can't 241 // ever be resolved in the assembler. 242 Ctx.reportError(Fixup.getLoc(), 243 "relocation for a thread-local variable points to an " 244 "absolute symbol"); 245 return Value; 246 } 247 248 if (!IsResolved) { 249 // FIXME: Figure out when this can actually happen, and verify our 250 // behavior. 251 Ctx.reportError(Fixup.getLoc(), "unresolved movw fixup not yet " 252 "implemented"); 253 return Value; 254 } 255 256 if (AArch64MCExpr::getSymbolLoc(RefKind) == AArch64MCExpr::VK_SABS) { 257 switch (AArch64MCExpr::getAddressFrag(RefKind)) { 258 case AArch64MCExpr::VK_G0: 259 break; 260 case AArch64MCExpr::VK_G1: 261 SignedValue = SignedValue >> 16; 262 break; 263 case AArch64MCExpr::VK_G2: 264 SignedValue = SignedValue >> 32; 265 break; 266 case AArch64MCExpr::VK_G3: 267 SignedValue = SignedValue >> 48; 268 break; 269 default: 270 llvm_unreachable("Variant kind doesn't correspond to fixup"); 271 } 272 273 } else { 274 switch (AArch64MCExpr::getAddressFrag(RefKind)) { 275 case AArch64MCExpr::VK_G0: 276 break; 277 case AArch64MCExpr::VK_G1: 278 Value = Value >> 16; 279 break; 280 case AArch64MCExpr::VK_G2: 281 Value = Value >> 32; 282 break; 283 case AArch64MCExpr::VK_G3: 284 Value = Value >> 48; 285 break; 286 default: 287 llvm_unreachable("Variant kind doesn't correspond to fixup"); 288 } 289 } 290 291 if (RefKind & AArch64MCExpr::VK_NC) { 292 Value &= 0xFFFF; 293 } 294 else if (AArch64MCExpr::getSymbolLoc(RefKind) == AArch64MCExpr::VK_SABS) { 295 if (SignedValue > 0xFFFF || SignedValue < -0xFFFF) 296 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 297 298 // Invert the negative immediate because it will feed into a MOVN. 299 if (SignedValue < 0) 300 SignedValue = ~SignedValue; 301 Value = static_cast<uint64_t>(SignedValue); 302 } 303 else if (Value > 0xFFFF) { 304 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 305 } 306 return Value; 307 } 308 case AArch64::fixup_aarch64_pcrel_branch14: 309 // Signed 16-bit immediate 310 if (SignedValue > 32767 || SignedValue < -32768) 311 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 312 // Low two bits are not encoded (4-byte alignment assumed). 313 if (Value & 0x3) 314 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned"); 315 return (Value >> 2) & 0x3fff; 316 case AArch64::fixup_aarch64_pcrel_branch26: 317 case AArch64::fixup_aarch64_pcrel_call26: 318 // Signed 28-bit immediate 319 if (SignedValue > 134217727 || SignedValue < -134217728) 320 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 321 // Low two bits are not encoded (4-byte alignment assumed). 322 if (Value & 0x3) 323 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned"); 324 return (Value >> 2) & 0x3ffffff; 325 case FK_Data_1: 326 case FK_Data_2: 327 case FK_Data_4: 328 case FK_Data_8: 329 if (!valueFitsIntoFixupKind(Fixup.getTargetKind(), Value)) 330 Ctx.reportError(Fixup.getLoc(), "fixup value too large for data type!"); 331 LLVM_FALLTHROUGH; 332 case FK_NONE: 333 case FK_SecRel_2: 334 case FK_SecRel_4: 335 return Value; 336 } 337 } 338 339 Optional<MCFixupKind> AArch64AsmBackend::getFixupKind(StringRef Name) const { 340 if (TheTriple.isOSBinFormatELF() && Name == "R_AARCH64_NONE") 341 return FK_NONE; 342 return MCAsmBackend::getFixupKind(Name); 343 } 344 345 /// getFixupKindContainereSizeInBytes - The number of bytes of the 346 /// container involved in big endian or 0 if the item is little endian 347 unsigned AArch64AsmBackend::getFixupKindContainereSizeInBytes(unsigned Kind) const { 348 if (Endian == support::little) 349 return 0; 350 351 switch (Kind) { 352 default: 353 llvm_unreachable("Unknown fixup kind!"); 354 355 case FK_Data_1: 356 return 1; 357 case FK_Data_2: 358 return 2; 359 case FK_Data_4: 360 return 4; 361 case FK_Data_8: 362 return 8; 363 364 case AArch64::fixup_aarch64_tlsdesc_call: 365 case AArch64::fixup_aarch64_movw: 366 case AArch64::fixup_aarch64_pcrel_branch14: 367 case AArch64::fixup_aarch64_add_imm12: 368 case AArch64::fixup_aarch64_ldst_imm12_scale1: 369 case AArch64::fixup_aarch64_ldst_imm12_scale2: 370 case AArch64::fixup_aarch64_ldst_imm12_scale4: 371 case AArch64::fixup_aarch64_ldst_imm12_scale8: 372 case AArch64::fixup_aarch64_ldst_imm12_scale16: 373 case AArch64::fixup_aarch64_ldr_pcrel_imm19: 374 case AArch64::fixup_aarch64_pcrel_branch19: 375 case AArch64::fixup_aarch64_pcrel_adr_imm21: 376 case AArch64::fixup_aarch64_pcrel_adrp_imm21: 377 case AArch64::fixup_aarch64_pcrel_branch26: 378 case AArch64::fixup_aarch64_pcrel_call26: 379 // Instructions are always little endian 380 return 0; 381 } 382 } 383 384 void AArch64AsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 385 const MCValue &Target, 386 MutableArrayRef<char> Data, uint64_t Value, 387 bool IsResolved, 388 const MCSubtargetInfo *STI) const { 389 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 390 if (!Value) 391 return; // Doesn't change encoding. 392 MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind()); 393 MCContext &Ctx = Asm.getContext(); 394 int64_t SignedValue = static_cast<int64_t>(Value); 395 // Apply any target-specific value adjustments. 396 Value = adjustFixupValue(Fixup, Target, Value, Ctx, TheTriple, IsResolved); 397 398 // Shift the value into position. 399 Value <<= Info.TargetOffset; 400 401 unsigned Offset = Fixup.getOffset(); 402 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!"); 403 404 // Used to point to big endian bytes. 405 unsigned FulleSizeInBytes = getFixupKindContainereSizeInBytes(Fixup.getKind()); 406 407 // For each byte of the fragment that the fixup touches, mask in the 408 // bits from the fixup value. 409 if (FulleSizeInBytes == 0) { 410 // Handle as little-endian 411 for (unsigned i = 0; i != NumBytes; ++i) { 412 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); 413 } 414 } else { 415 // Handle as big-endian 416 assert((Offset + FulleSizeInBytes) <= Data.size() && "Invalid fixup size!"); 417 assert(NumBytes <= FulleSizeInBytes && "Invalid fixup size!"); 418 for (unsigned i = 0; i != NumBytes; ++i) { 419 unsigned Idx = FulleSizeInBytes - 1 - i; 420 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff); 421 } 422 } 423 424 // FIXME: getFixupKindInfo() and getFixupKindNumBytes() could be fixed to 425 // handle this more cleanly. This may affect the output of -show-mc-encoding. 426 AArch64MCExpr::VariantKind RefKind = 427 static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind()); 428 if (AArch64MCExpr::getSymbolLoc(RefKind) == AArch64MCExpr::VK_SABS) { 429 // If the immediate is negative, generate MOVN else MOVZ. 430 // (Bit 30 = 0) ==> MOVN, (Bit 30 = 1) ==> MOVZ. 431 if (SignedValue < 0) 432 Data[Offset + 3] &= ~(1 << 6); 433 else 434 Data[Offset + 3] |= (1 << 6); 435 } 436 } 437 438 bool AArch64AsmBackend::mayNeedRelaxation(const MCInst &Inst, 439 const MCSubtargetInfo &STI) const { 440 return false; 441 } 442 443 bool AArch64AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, 444 uint64_t Value, 445 const MCRelaxableFragment *DF, 446 const MCAsmLayout &Layout) const { 447 // FIXME: This isn't correct for AArch64. Just moving the "generic" logic 448 // into the targets for now. 449 // 450 // Relax if the value is too big for a (signed) i8. 451 return int64_t(Value) != int64_t(int8_t(Value)); 452 } 453 454 void AArch64AsmBackend::relaxInstruction(const MCInst &Inst, 455 const MCSubtargetInfo &STI, 456 MCInst &Res) const { 457 llvm_unreachable("AArch64AsmBackend::relaxInstruction() unimplemented"); 458 } 459 460 bool AArch64AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const { 461 // If the count is not 4-byte aligned, we must be writing data into the text 462 // section (otherwise we have unaligned instructions, and thus have far 463 // bigger problems), so just write zeros instead. 464 OS.write_zeros(Count % 4); 465 466 // We are properly aligned, so write NOPs as requested. 467 Count /= 4; 468 for (uint64_t i = 0; i != Count; ++i) 469 support::endian::write<uint32_t>(OS, 0xd503201f, Endian); 470 return true; 471 } 472 473 bool AArch64AsmBackend::shouldForceRelocation(const MCAssembler &Asm, 474 const MCFixup &Fixup, 475 const MCValue &Target) { 476 unsigned Kind = Fixup.getKind(); 477 if (Kind == FK_NONE) 478 return true; 479 480 // The ADRP instruction adds some multiple of 0x1000 to the current PC & 481 // ~0xfff. This means that the required offset to reach a symbol can vary by 482 // up to one step depending on where the ADRP is in memory. For example: 483 // 484 // ADRP x0, there 485 // there: 486 // 487 // If the ADRP occurs at address 0xffc then "there" will be at 0x1000 and 488 // we'll need that as an offset. At any other address "there" will be in the 489 // same page as the ADRP and the instruction should encode 0x0. Assuming the 490 // section isn't 0x1000-aligned, we therefore need to delegate this decision 491 // to the linker -- a relocation! 492 if (Kind == AArch64::fixup_aarch64_pcrel_adrp_imm21) 493 return true; 494 495 AArch64MCExpr::VariantKind RefKind = 496 static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind()); 497 AArch64MCExpr::VariantKind SymLoc = AArch64MCExpr::getSymbolLoc(RefKind); 498 // LDR GOT relocations need a relocation 499 if (Kind == AArch64::fixup_aarch64_ldr_pcrel_imm19 && 500 SymLoc == AArch64MCExpr::VK_GOT) 501 return true; 502 return false; 503 } 504 505 namespace { 506 507 namespace CU { 508 509 /// Compact unwind encoding values. 510 enum CompactUnwindEncodings { 511 /// A "frameless" leaf function, where no non-volatile registers are 512 /// saved. The return remains in LR throughout the function. 513 UNWIND_ARM64_MODE_FRAMELESS = 0x02000000, 514 515 /// No compact unwind encoding available. Instead the low 23-bits of 516 /// the compact unwind encoding is the offset of the DWARF FDE in the 517 /// __eh_frame section. This mode is never used in object files. It is only 518 /// generated by the linker in final linked images, which have only DWARF info 519 /// for a function. 520 UNWIND_ARM64_MODE_DWARF = 0x03000000, 521 522 /// This is a standard arm64 prologue where FP/LR are immediately 523 /// pushed on the stack, then SP is copied to FP. If there are any 524 /// non-volatile register saved, they are copied into the stack fame in pairs 525 /// in a contiguous ranger right below the saved FP/LR pair. Any subset of the 526 /// five X pairs and four D pairs can be saved, but the memory layout must be 527 /// in register number order. 528 UNWIND_ARM64_MODE_FRAME = 0x04000000, 529 530 /// Frame register pair encodings. 531 UNWIND_ARM64_FRAME_X19_X20_PAIR = 0x00000001, 532 UNWIND_ARM64_FRAME_X21_X22_PAIR = 0x00000002, 533 UNWIND_ARM64_FRAME_X23_X24_PAIR = 0x00000004, 534 UNWIND_ARM64_FRAME_X25_X26_PAIR = 0x00000008, 535 UNWIND_ARM64_FRAME_X27_X28_PAIR = 0x00000010, 536 UNWIND_ARM64_FRAME_D8_D9_PAIR = 0x00000100, 537 UNWIND_ARM64_FRAME_D10_D11_PAIR = 0x00000200, 538 UNWIND_ARM64_FRAME_D12_D13_PAIR = 0x00000400, 539 UNWIND_ARM64_FRAME_D14_D15_PAIR = 0x00000800 540 }; 541 542 } // end CU namespace 543 544 // FIXME: This should be in a separate file. 545 class DarwinAArch64AsmBackend : public AArch64AsmBackend { 546 const MCRegisterInfo &MRI; 547 bool IsILP32; 548 549 /// Encode compact unwind stack adjustment for frameless functions. 550 /// See UNWIND_ARM64_FRAMELESS_STACK_SIZE_MASK in compact_unwind_encoding.h. 551 /// The stack size always needs to be 16 byte aligned. 552 uint32_t encodeStackAdjustment(uint32_t StackSize) const { 553 return (StackSize / 16) << 12; 554 } 555 556 public: 557 DarwinAArch64AsmBackend(const Target &T, const Triple &TT, 558 const MCRegisterInfo &MRI, bool IsILP32) 559 : AArch64AsmBackend(T, TT, /*IsLittleEndian*/ true), MRI(MRI), 560 IsILP32(IsILP32) {} 561 562 std::unique_ptr<MCObjectTargetWriter> 563 createObjectTargetWriter() const override { 564 if (IsILP32) 565 return createAArch64MachObjectWriter( 566 MachO::CPU_TYPE_ARM64_32, MachO::CPU_SUBTYPE_ARM64_32_V8, true); 567 else 568 return createAArch64MachObjectWriter(MachO::CPU_TYPE_ARM64, 569 MachO::CPU_SUBTYPE_ARM64_ALL, false); 570 } 571 572 /// Generate the compact unwind encoding from the CFI directives. 573 uint32_t generateCompactUnwindEncoding( 574 ArrayRef<MCCFIInstruction> Instrs) const override { 575 if (Instrs.empty()) 576 return CU::UNWIND_ARM64_MODE_FRAMELESS; 577 578 bool HasFP = false; 579 unsigned StackSize = 0; 580 581 uint32_t CompactUnwindEncoding = 0; 582 for (size_t i = 0, e = Instrs.size(); i != e; ++i) { 583 const MCCFIInstruction &Inst = Instrs[i]; 584 585 switch (Inst.getOperation()) { 586 default: 587 // Cannot handle this directive: bail out. 588 return CU::UNWIND_ARM64_MODE_DWARF; 589 case MCCFIInstruction::OpDefCfa: { 590 // Defines a frame pointer. 591 unsigned XReg = 592 getXRegFromWReg(*MRI.getLLVMRegNum(Inst.getRegister(), true)); 593 594 // Other CFA registers than FP are not supported by compact unwind. 595 // Fallback on DWARF. 596 // FIXME: When opt-remarks are supported in MC, add a remark to notify 597 // the user. 598 if (XReg != AArch64::FP) 599 return CU::UNWIND_ARM64_MODE_DWARF; 600 601 assert(XReg == AArch64::FP && "Invalid frame pointer!"); 602 assert(i + 2 < e && "Insufficient CFI instructions to define a frame!"); 603 604 const MCCFIInstruction &LRPush = Instrs[++i]; 605 assert(LRPush.getOperation() == MCCFIInstruction::OpOffset && 606 "Link register not pushed!"); 607 const MCCFIInstruction &FPPush = Instrs[++i]; 608 assert(FPPush.getOperation() == MCCFIInstruction::OpOffset && 609 "Frame pointer not pushed!"); 610 611 unsigned LRReg = *MRI.getLLVMRegNum(LRPush.getRegister(), true); 612 unsigned FPReg = *MRI.getLLVMRegNum(FPPush.getRegister(), true); 613 614 LRReg = getXRegFromWReg(LRReg); 615 FPReg = getXRegFromWReg(FPReg); 616 617 assert(LRReg == AArch64::LR && FPReg == AArch64::FP && 618 "Pushing invalid registers for frame!"); 619 620 // Indicate that the function has a frame. 621 CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAME; 622 HasFP = true; 623 break; 624 } 625 case MCCFIInstruction::OpDefCfaOffset: { 626 assert(StackSize == 0 && "We already have the CFA offset!"); 627 StackSize = std::abs(Inst.getOffset()); 628 break; 629 } 630 case MCCFIInstruction::OpOffset: { 631 // Registers are saved in pairs. We expect there to be two consecutive 632 // `.cfi_offset' instructions with the appropriate registers specified. 633 unsigned Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true); 634 if (i + 1 == e) 635 return CU::UNWIND_ARM64_MODE_DWARF; 636 637 const MCCFIInstruction &Inst2 = Instrs[++i]; 638 if (Inst2.getOperation() != MCCFIInstruction::OpOffset) 639 return CU::UNWIND_ARM64_MODE_DWARF; 640 unsigned Reg2 = *MRI.getLLVMRegNum(Inst2.getRegister(), true); 641 642 // N.B. The encodings must be in register number order, and the X 643 // registers before the D registers. 644 645 // X19/X20 pair = 0x00000001, 646 // X21/X22 pair = 0x00000002, 647 // X23/X24 pair = 0x00000004, 648 // X25/X26 pair = 0x00000008, 649 // X27/X28 pair = 0x00000010 650 Reg1 = getXRegFromWReg(Reg1); 651 Reg2 = getXRegFromWReg(Reg2); 652 653 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && 654 (CompactUnwindEncoding & 0xF1E) == 0) 655 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X19_X20_PAIR; 656 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && 657 (CompactUnwindEncoding & 0xF1C) == 0) 658 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X21_X22_PAIR; 659 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && 660 (CompactUnwindEncoding & 0xF18) == 0) 661 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X23_X24_PAIR; 662 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && 663 (CompactUnwindEncoding & 0xF10) == 0) 664 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X25_X26_PAIR; 665 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && 666 (CompactUnwindEncoding & 0xF00) == 0) 667 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X27_X28_PAIR; 668 else { 669 Reg1 = getDRegFromBReg(Reg1); 670 Reg2 = getDRegFromBReg(Reg2); 671 672 // D8/D9 pair = 0x00000100, 673 // D10/D11 pair = 0x00000200, 674 // D12/D13 pair = 0x00000400, 675 // D14/D15 pair = 0x00000800 676 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && 677 (CompactUnwindEncoding & 0xE00) == 0) 678 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D8_D9_PAIR; 679 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && 680 (CompactUnwindEncoding & 0xC00) == 0) 681 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D10_D11_PAIR; 682 else if (Reg1 == AArch64::D12 && Reg2 == AArch64::D13 && 683 (CompactUnwindEncoding & 0x800) == 0) 684 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D12_D13_PAIR; 685 else if (Reg1 == AArch64::D14 && Reg2 == AArch64::D15) 686 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D14_D15_PAIR; 687 else 688 // A pair was pushed which we cannot handle. 689 return CU::UNWIND_ARM64_MODE_DWARF; 690 } 691 692 break; 693 } 694 } 695 } 696 697 if (!HasFP) { 698 // With compact unwind info we can only represent stack adjustments of up 699 // to 65520 bytes. 700 if (StackSize > 65520) 701 return CU::UNWIND_ARM64_MODE_DWARF; 702 703 CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAMELESS; 704 CompactUnwindEncoding |= encodeStackAdjustment(StackSize); 705 } 706 707 return CompactUnwindEncoding; 708 } 709 }; 710 711 } // end anonymous namespace 712 713 namespace { 714 715 class ELFAArch64AsmBackend : public AArch64AsmBackend { 716 public: 717 uint8_t OSABI; 718 bool IsILP32; 719 720 ELFAArch64AsmBackend(const Target &T, const Triple &TT, uint8_t OSABI, 721 bool IsLittleEndian, bool IsILP32) 722 : AArch64AsmBackend(T, TT, IsLittleEndian), OSABI(OSABI), 723 IsILP32(IsILP32) {} 724 725 std::unique_ptr<MCObjectTargetWriter> 726 createObjectTargetWriter() const override { 727 return createAArch64ELFObjectWriter(OSABI, IsILP32); 728 } 729 }; 730 731 } 732 733 namespace { 734 class COFFAArch64AsmBackend : public AArch64AsmBackend { 735 public: 736 COFFAArch64AsmBackend(const Target &T, const Triple &TheTriple) 737 : AArch64AsmBackend(T, TheTriple, /*IsLittleEndian*/ true) {} 738 739 std::unique_ptr<MCObjectTargetWriter> 740 createObjectTargetWriter() const override { 741 return createAArch64WinCOFFObjectWriter(); 742 } 743 }; 744 } 745 746 MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T, 747 const MCSubtargetInfo &STI, 748 const MCRegisterInfo &MRI, 749 const MCTargetOptions &Options) { 750 const Triple &TheTriple = STI.getTargetTriple(); 751 if (TheTriple.isOSBinFormatMachO()) { 752 const bool IsILP32 = TheTriple.isArch32Bit(); 753 return new DarwinAArch64AsmBackend(T, TheTriple, MRI, IsILP32); 754 } 755 756 if (TheTriple.isOSBinFormatCOFF()) 757 return new COFFAArch64AsmBackend(T, TheTriple); 758 759 assert(TheTriple.isOSBinFormatELF() && "Invalid target"); 760 761 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); 762 bool IsILP32 = Options.getABIName() == "ilp32"; 763 return new ELFAArch64AsmBackend(T, TheTriple, OSABI, /*IsLittleEndian=*/true, 764 IsILP32); 765 } 766 767 MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T, 768 const MCSubtargetInfo &STI, 769 const MCRegisterInfo &MRI, 770 const MCTargetOptions &Options) { 771 const Triple &TheTriple = STI.getTargetTriple(); 772 assert(TheTriple.isOSBinFormatELF() && 773 "Big endian is only supported for ELF targets!"); 774 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); 775 bool IsILP32 = Options.getABIName() == "ilp32"; 776 return new ELFAArch64AsmBackend(T, TheTriple, OSABI, /*IsLittleEndian=*/false, 777 IsILP32); 778 } 779