1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "AArch64Disassembler.h" 13 #include "AArch64ExternalSymbolizer.h" 14 #include "MCTargetDesc/AArch64AddressingModes.h" 15 #include "MCTargetDesc/AArch64MCTargetDesc.h" 16 #include "TargetInfo/AArch64TargetInfo.h" 17 #include "Utils/AArch64BaseInfo.h" 18 #include "llvm-c/Disassembler.h" 19 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 20 #include "llvm/MC/MCFixedLenDisassembler.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/Support/Compiler.h" 25 #include "llvm/Support/Debug.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include <algorithm> 29 #include <memory> 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "aarch64-disassembler" 34 35 // Pull DecodeStatus and its enum values into the global namespace. 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 // Forward declare these because the autogenerated code will reference them. 39 // Definitions are further down. 40 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, 41 unsigned RegNo, uint64_t Address, 42 const void *Decoder); 43 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, 44 unsigned RegNo, 45 uint64_t Address, 46 const void *Decoder); 47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 48 uint64_t Address, 49 const void *Decoder); 50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 51 uint64_t Address, 52 const void *Decoder); 53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 54 uint64_t Address, 55 const void *Decoder); 56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 57 uint64_t Address, 58 const void *Decoder); 59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 60 uint64_t Address, 61 const void *Decoder); 62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 63 uint64_t Address, 64 const void *Decoder); 65 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, 66 unsigned RegNo, 67 uint64_t Address, 68 const void *Decoder); 69 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, 70 unsigned RegNo, uint64_t Address, 71 const void *Decoder); 72 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 73 uint64_t Address, 74 const void *Decoder); 75 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, 76 unsigned RegNo, uint64_t Address, 77 const void *Decoder); 78 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 79 uint64_t Address, 80 const void *Decoder); 81 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 82 uint64_t Address, 83 const void *Decoder); 84 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 85 uint64_t Address, 86 const void *Decoder); 87 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 88 uint64_t Address, 89 const void *Decoder); 90 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 91 uint64_t Address, 92 const void *Decoder); 93 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 94 uint64_t Address, 95 const void *Decoder); 96 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 97 uint64_t Address, 98 const void *Decoder); 99 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 100 uint64_t Address, 101 const void *Decoder); 102 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 103 uint64_t Address, 104 const void *Decoder); 105 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 106 uint64_t Address, 107 const void *Decoder); 108 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 109 uint64_t Address, 110 const void *Decoder); 111 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 112 uint64_t Address, 113 const void *Decoder); 114 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 115 uint64_t Address, 116 const void *Decoder); 117 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 118 uint64_t Address, 119 const void *Decoder); 120 121 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 122 uint64_t Address, 123 const void *Decoder); 124 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 125 uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 128 uint64_t Address, const void *Decoder); 129 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 130 uint64_t Address, const void *Decoder); 131 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 132 uint64_t Address, const void *Decoder); 133 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 134 uint64_t Address, const void *Decoder); 135 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 136 uint64_t Address, 137 const void *Decoder); 138 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 139 uint64_t Address, 140 const void *Decoder); 141 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 142 uint64_t Address, 143 const void *Decoder); 144 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 145 uint64_t Address, 146 const void *Decoder); 147 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 148 uint64_t Address, 149 const void *Decoder); 150 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 151 uint64_t Address, 152 const void *Decoder); 153 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 154 uint64_t Address, 155 const void *Decoder); 156 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 157 uint64_t Address, 158 const void *Decoder); 159 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 160 uint64_t Address, 161 const void *Decoder); 162 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 163 uint64_t Address, 164 const void *Decoder); 165 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 166 uint64_t Address, 167 const void *Decoder); 168 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 173 uint64_t Address, 174 const void *Decoder); 175 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 176 uint64_t Address, 177 const void *Decoder); 178 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 179 uint64_t Address, const void *Decoder); 180 181 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 182 uint64_t Address, 183 const void *Decoder); 184 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 185 uint64_t Addr, const void *Decoder); 186 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 187 uint64_t Addr, 188 const void *Decoder); 189 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 190 uint64_t Addr, const void *Decoder); 191 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 192 uint64_t Addr, 193 const void *Decoder); 194 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 195 uint64_t Addr, const void *Decoder); 196 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 197 uint64_t Addr, 198 const void *Decoder); 199 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 200 uint64_t Addr, const void *Decoder); 201 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 202 uint64_t Addr, const void *Decoder); 203 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 204 uint64_t Addr, const void *Decoder); 205 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 206 uint64_t Addr, const void *Decoder); 207 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 208 uint64_t Addr, const void *Decoder); 209 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 210 unsigned RegNo, 211 uint64_t Addr, 212 const void *Decoder); 213 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 214 unsigned RegNo, 215 uint64_t Addr, 216 const void *Decoder); 217 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 218 uint32_t insn, 219 uint64_t Address, 220 const void *Decoder); 221 template<int Bits> 222 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 223 uint64_t Address, const void *Decoder); 224 template <int ElementWidth> 225 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 226 uint64_t Addr, const void *Decoder); 227 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 228 uint64_t Addr, const void *Decoder); 229 230 static bool Check(DecodeStatus &Out, DecodeStatus In) { 231 switch (In) { 232 case MCDisassembler::Success: 233 // Out stays the same. 234 return true; 235 case MCDisassembler::SoftFail: 236 Out = In; 237 return true; 238 case MCDisassembler::Fail: 239 Out = In; 240 return false; 241 } 242 llvm_unreachable("Invalid DecodeStatus!"); 243 } 244 245 #include "AArch64GenDisassemblerTables.inc" 246 #include "AArch64GenInstrInfo.inc" 247 248 #define Success MCDisassembler::Success 249 #define Fail MCDisassembler::Fail 250 #define SoftFail MCDisassembler::SoftFail 251 252 static MCDisassembler *createAArch64Disassembler(const Target &T, 253 const MCSubtargetInfo &STI, 254 MCContext &Ctx) { 255 return new AArch64Disassembler(STI, Ctx); 256 } 257 258 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 259 ArrayRef<uint8_t> Bytes, 260 uint64_t Address, 261 raw_ostream &CS) const { 262 CommentStream = &CS; 263 264 Size = 0; 265 // We want to read exactly 4 bytes of data. 266 if (Bytes.size() < 4) 267 return Fail; 268 Size = 4; 269 270 // Encoded as a small-endian 32-bit word in the stream. 271 uint32_t Insn = 272 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 273 274 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32}; 275 276 for (auto Table : Tables) { 277 DecodeStatus Result = 278 decodeInstruction(Table, MI, Insn, Address, this, STI); 279 if (Result != MCDisassembler::Fail) 280 return Result; 281 } 282 283 return MCDisassembler::Fail; 284 } 285 286 static MCSymbolizer * 287 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 288 LLVMSymbolLookupCallback SymbolLookUp, 289 void *DisInfo, MCContext *Ctx, 290 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 291 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 292 SymbolLookUp, DisInfo); 293 } 294 295 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() { 296 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 297 createAArch64Disassembler); 298 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 299 createAArch64Disassembler); 300 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 301 createAArch64ExternalSymbolizer); 302 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 303 createAArch64ExternalSymbolizer); 304 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(), 305 createAArch64Disassembler); 306 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(), 307 createAArch64ExternalSymbolizer); 308 309 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 310 createAArch64Disassembler); 311 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 312 createAArch64ExternalSymbolizer); 313 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(), 314 createAArch64Disassembler); 315 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(), 316 createAArch64ExternalSymbolizer); 317 } 318 319 static const unsigned FPR128DecoderTable[] = { 320 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 321 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 322 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 323 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 324 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 325 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 326 AArch64::Q30, AArch64::Q31 327 }; 328 329 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 330 uint64_t Addr, 331 const void *Decoder) { 332 if (RegNo > 31) 333 return Fail; 334 335 unsigned Register = FPR128DecoderTable[RegNo]; 336 Inst.addOperand(MCOperand::createReg(Register)); 337 return Success; 338 } 339 340 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 341 uint64_t Addr, 342 const void *Decoder) { 343 if (RegNo > 15) 344 return Fail; 345 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 346 } 347 348 static const unsigned FPR64DecoderTable[] = { 349 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, 350 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, 351 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, 352 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, 353 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, 354 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, 355 AArch64::D30, AArch64::D31 356 }; 357 358 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 359 uint64_t Addr, 360 const void *Decoder) { 361 if (RegNo > 31) 362 return Fail; 363 364 unsigned Register = FPR64DecoderTable[RegNo]; 365 Inst.addOperand(MCOperand::createReg(Register)); 366 return Success; 367 } 368 369 static const unsigned FPR32DecoderTable[] = { 370 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, 371 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, 372 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, 373 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, 374 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, 375 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, 376 AArch64::S30, AArch64::S31 377 }; 378 379 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 380 uint64_t Addr, 381 const void *Decoder) { 382 if (RegNo > 31) 383 return Fail; 384 385 unsigned Register = FPR32DecoderTable[RegNo]; 386 Inst.addOperand(MCOperand::createReg(Register)); 387 return Success; 388 } 389 390 static const unsigned FPR16DecoderTable[] = { 391 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, 392 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, 393 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, 394 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, 395 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, 396 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, 397 AArch64::H30, AArch64::H31 398 }; 399 400 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 401 uint64_t Addr, 402 const void *Decoder) { 403 if (RegNo > 31) 404 return Fail; 405 406 unsigned Register = FPR16DecoderTable[RegNo]; 407 Inst.addOperand(MCOperand::createReg(Register)); 408 return Success; 409 } 410 411 static const unsigned FPR8DecoderTable[] = { 412 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, 413 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, 414 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, 415 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, 416 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, 417 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, 418 AArch64::B30, AArch64::B31 419 }; 420 421 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 422 uint64_t Addr, 423 const void *Decoder) { 424 if (RegNo > 31) 425 return Fail; 426 427 unsigned Register = FPR8DecoderTable[RegNo]; 428 Inst.addOperand(MCOperand::createReg(Register)); 429 return Success; 430 } 431 432 static const unsigned GPR64DecoderTable[] = { 433 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, 434 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, 435 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, 436 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, 437 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, 438 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, 439 AArch64::LR, AArch64::XZR 440 }; 441 442 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 443 uint64_t Addr, 444 const void *Decoder) { 445 if (RegNo > 30) 446 return Fail; 447 448 unsigned Register = GPR64DecoderTable[RegNo]; 449 Inst.addOperand(MCOperand::createReg(Register)); 450 return Success; 451 } 452 453 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 454 uint64_t Addr, 455 const void *Decoder) { 456 if (RegNo > 31) 457 return Fail; 458 459 unsigned Register = GPR64DecoderTable[RegNo]; 460 Inst.addOperand(MCOperand::createReg(Register)); 461 return Success; 462 } 463 464 static const unsigned GPR64x8DecoderTable[] = { 465 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, 466 AArch64::X2_X3_X4_X5_X6_X7_X8_X9, 467 AArch64::X4_X5_X6_X7_X8_X9_X10_X11, 468 AArch64::X6_X7_X8_X9_X10_X11_X12_X13, 469 AArch64::X8_X9_X10_X11_X12_X13_X14_X15, 470 AArch64::X10_X11_X12_X13_X14_X15_X16_X17, 471 AArch64::X12_X13_X14_X15_X16_X17_X18_X19, 472 AArch64::X14_X15_X16_X17_X18_X19_X20_X21, 473 AArch64::X16_X17_X18_X19_X20_X21_X22_X23, 474 AArch64::X18_X19_X20_X21_X22_X23_X24_X25, 475 AArch64::X20_X21_X22_X23_X24_X25_X26_X27, 476 AArch64::X22_X23_X24_X25_X26_X27_X28_FP, 477 }; 478 479 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, 480 unsigned RegNo, 481 uint64_t Address, 482 const void *Decoder) { 483 if (RegNo > 22) 484 return Fail; 485 if (RegNo & 1) 486 return Fail; 487 488 unsigned Register = GPR64x8DecoderTable[RegNo >> 1]; 489 Inst.addOperand(MCOperand::createReg(Register)); 490 return Success; 491 } 492 493 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 494 uint64_t Addr, 495 const void *Decoder) { 496 if (RegNo > 31) 497 return Fail; 498 unsigned Register = GPR64DecoderTable[RegNo]; 499 if (Register == AArch64::XZR) 500 Register = AArch64::SP; 501 Inst.addOperand(MCOperand::createReg(Register)); 502 return Success; 503 } 504 505 static const unsigned GPR32DecoderTable[] = { 506 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, 507 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, 508 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, 509 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, 510 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, 511 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, 512 AArch64::W30, AArch64::WZR 513 }; 514 515 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 516 uint64_t Addr, 517 const void *Decoder) { 518 if (RegNo > 31) 519 return Fail; 520 521 unsigned Register = GPR32DecoderTable[RegNo]; 522 Inst.addOperand(MCOperand::createReg(Register)); 523 return Success; 524 } 525 526 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 527 uint64_t Addr, 528 const void *Decoder) { 529 if (RegNo > 31) 530 return Fail; 531 532 unsigned Register = GPR32DecoderTable[RegNo]; 533 if (Register == AArch64::WZR) 534 Register = AArch64::WSP; 535 Inst.addOperand(MCOperand::createReg(Register)); 536 return Success; 537 } 538 static const unsigned ZPRDecoderTable[] = { 539 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, 540 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, 541 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, 542 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 543 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, 544 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, 545 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, 546 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31 547 }; 548 549 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 550 uint64_t Address, 551 const void* Decoder) { 552 if (RegNo > 31) 553 return Fail; 554 555 unsigned Register = ZPRDecoderTable[RegNo]; 556 Inst.addOperand(MCOperand::createReg(Register)); 557 return Success; 558 } 559 560 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, 561 uint64_t Address, 562 const void *Decoder) { 563 if (RegNo > 15) 564 return Fail; 565 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 566 } 567 568 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 569 uint64_t Address, 570 const void *Decoder) { 571 if (RegNo > 7) 572 return Fail; 573 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); 574 } 575 576 static const unsigned ZZDecoderTable[] = { 577 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, 578 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, 579 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, 580 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, 581 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, 582 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, 583 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, 584 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0 585 }; 586 587 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, 588 uint64_t Address, 589 const void* Decoder) { 590 if (RegNo > 31) 591 return Fail; 592 unsigned Register = ZZDecoderTable[RegNo]; 593 Inst.addOperand(MCOperand::createReg(Register)); 594 return Success; 595 } 596 597 static const unsigned ZZZDecoderTable[] = { 598 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, 599 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, 600 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, 601 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, 602 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, 603 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, 604 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, 605 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, 606 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, 607 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, 608 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1 609 }; 610 611 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, 612 uint64_t Address, 613 const void* Decoder) { 614 if (RegNo > 31) 615 return Fail; 616 unsigned Register = ZZZDecoderTable[RegNo]; 617 Inst.addOperand(MCOperand::createReg(Register)); 618 return Success; 619 } 620 621 static const unsigned ZZZZDecoderTable[] = { 622 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, 623 AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, 624 AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, 625 AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, 626 AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, 627 AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, 628 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, 629 AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, 630 AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, 631 AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, 632 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2 633 }; 634 635 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, 636 uint64_t Address, 637 const void* Decoder) { 638 if (RegNo > 31) 639 return Fail; 640 unsigned Register = ZZZZDecoderTable[RegNo]; 641 Inst.addOperand(MCOperand::createReg(Register)); 642 return Success; 643 } 644 645 static const unsigned PPRDecoderTable[] = { 646 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, 647 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, 648 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, 649 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15 650 }; 651 652 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 653 uint64_t Addr, const void *Decoder) { 654 if (RegNo > 15) 655 return Fail; 656 657 unsigned Register = PPRDecoderTable[RegNo]; 658 Inst.addOperand(MCOperand::createReg(Register)); 659 return Success; 660 } 661 662 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, 663 uint64_t Addr, 664 const void* Decoder) { 665 if (RegNo > 7) 666 return Fail; 667 668 // Just reuse the PPR decode table 669 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); 670 } 671 672 static const unsigned VectorDecoderTable[] = { 673 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 674 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 675 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 676 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 677 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 678 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 679 AArch64::Q30, AArch64::Q31 680 }; 681 682 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, 683 uint64_t Addr, 684 const void *Decoder) { 685 if (RegNo > 31) 686 return Fail; 687 688 unsigned Register = VectorDecoderTable[RegNo]; 689 Inst.addOperand(MCOperand::createReg(Register)); 690 return Success; 691 } 692 693 static const unsigned QQDecoderTable[] = { 694 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, 695 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, 696 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, 697 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 698 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, 699 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, 700 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, 701 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0 702 }; 703 704 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 705 uint64_t Addr, const void *Decoder) { 706 if (RegNo > 31) 707 return Fail; 708 unsigned Register = QQDecoderTable[RegNo]; 709 Inst.addOperand(MCOperand::createReg(Register)); 710 return Success; 711 } 712 713 static const unsigned QQQDecoderTable[] = { 714 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, 715 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, 716 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, 717 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, 718 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 719 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, 720 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, 721 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, 722 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, 723 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, 724 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1 725 }; 726 727 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 728 uint64_t Addr, const void *Decoder) { 729 if (RegNo > 31) 730 return Fail; 731 unsigned Register = QQQDecoderTable[RegNo]; 732 Inst.addOperand(MCOperand::createReg(Register)); 733 return Success; 734 } 735 736 static const unsigned QQQQDecoderTable[] = { 737 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, 738 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, 739 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, 740 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, 741 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 742 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, 743 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, 744 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, 745 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, 746 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, 747 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2 748 }; 749 750 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 751 uint64_t Addr, 752 const void *Decoder) { 753 if (RegNo > 31) 754 return Fail; 755 unsigned Register = QQQQDecoderTable[RegNo]; 756 Inst.addOperand(MCOperand::createReg(Register)); 757 return Success; 758 } 759 760 static const unsigned DDDecoderTable[] = { 761 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, 762 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, 763 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, 764 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, 765 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, 766 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, 767 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, 768 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0 769 }; 770 771 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 772 uint64_t Addr, const void *Decoder) { 773 if (RegNo > 31) 774 return Fail; 775 unsigned Register = DDDecoderTable[RegNo]; 776 Inst.addOperand(MCOperand::createReg(Register)); 777 return Success; 778 } 779 780 static const unsigned DDDDecoderTable[] = { 781 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, 782 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, 783 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, 784 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, 785 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, 786 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, 787 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, 788 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, 789 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, 790 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, 791 AArch64::D30_D31_D0, AArch64::D31_D0_D1 792 }; 793 794 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 795 uint64_t Addr, const void *Decoder) { 796 if (RegNo > 31) 797 return Fail; 798 unsigned Register = DDDDecoderTable[RegNo]; 799 Inst.addOperand(MCOperand::createReg(Register)); 800 return Success; 801 } 802 803 static const unsigned DDDDDecoderTable[] = { 804 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, 805 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, 806 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, 807 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, 808 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, 809 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, 810 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, 811 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, 812 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, 813 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, 814 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2 815 }; 816 817 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 818 uint64_t Addr, 819 const void *Decoder) { 820 if (RegNo > 31) 821 return Fail; 822 unsigned Register = DDDDDecoderTable[RegNo]; 823 Inst.addOperand(MCOperand::createReg(Register)); 824 return Success; 825 } 826 827 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 828 uint64_t Addr, 829 const void *Decoder) { 830 // scale{5} is asserted as 1 in tblgen. 831 Imm |= 0x20; 832 Inst.addOperand(MCOperand::createImm(64 - Imm)); 833 return Success; 834 } 835 836 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 837 uint64_t Addr, 838 const void *Decoder) { 839 Inst.addOperand(MCOperand::createImm(64 - Imm)); 840 return Success; 841 } 842 843 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 844 uint64_t Addr, const void *Decoder) { 845 int64_t ImmVal = Imm; 846 const AArch64Disassembler *Dis = 847 static_cast<const AArch64Disassembler *>(Decoder); 848 849 // Sign-extend 19-bit immediate. 850 if (ImmVal & (1 << (19 - 1))) 851 ImmVal |= ~((1LL << 19) - 1); 852 853 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, 854 Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 855 Inst.addOperand(MCOperand::createImm(ImmVal)); 856 return Success; 857 } 858 859 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 860 uint64_t Address, const void *Decoder) { 861 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 862 Inst.addOperand(MCOperand::createImm(Imm & 1)); 863 return Success; 864 } 865 866 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 867 uint64_t Address, 868 const void *Decoder) { 869 Inst.addOperand(MCOperand::createImm(Imm)); 870 871 // Every system register in the encoding space is valid with the syntax 872 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 873 return Success; 874 } 875 876 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 877 uint64_t Address, 878 const void *Decoder) { 879 Inst.addOperand(MCOperand::createImm(Imm)); 880 881 return Success; 882 } 883 884 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 885 uint64_t Address, 886 const void *Decoder) { 887 // This decoder exists to add the dummy Lane operand to the MCInst, which must 888 // be 1 in assembly but has no other real manifestation. 889 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 890 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 891 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 892 893 if (IsToVec) { 894 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 895 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 896 } else { 897 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 898 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 899 } 900 901 // Add the lane 902 Inst.addOperand(MCOperand::createImm(1)); 903 904 return Success; 905 } 906 907 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 908 unsigned Add) { 909 Inst.addOperand(MCOperand::createImm(Add - Imm)); 910 return Success; 911 } 912 913 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 914 unsigned Add) { 915 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 916 return Success; 917 } 918 919 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 920 uint64_t Addr, const void *Decoder) { 921 return DecodeVecShiftRImm(Inst, Imm, 64); 922 } 923 924 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 925 uint64_t Addr, 926 const void *Decoder) { 927 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 928 } 929 930 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 931 uint64_t Addr, const void *Decoder) { 932 return DecodeVecShiftRImm(Inst, Imm, 32); 933 } 934 935 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 936 uint64_t Addr, 937 const void *Decoder) { 938 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 939 } 940 941 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 942 uint64_t Addr, const void *Decoder) { 943 return DecodeVecShiftRImm(Inst, Imm, 16); 944 } 945 946 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 947 uint64_t Addr, 948 const void *Decoder) { 949 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 950 } 951 952 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 953 uint64_t Addr, const void *Decoder) { 954 return DecodeVecShiftRImm(Inst, Imm, 8); 955 } 956 957 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 958 uint64_t Addr, const void *Decoder) { 959 return DecodeVecShiftLImm(Inst, Imm, 64); 960 } 961 962 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 963 uint64_t Addr, const void *Decoder) { 964 return DecodeVecShiftLImm(Inst, Imm, 32); 965 } 966 967 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 968 uint64_t Addr, const void *Decoder) { 969 return DecodeVecShiftLImm(Inst, Imm, 16); 970 } 971 972 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 973 uint64_t Addr, const void *Decoder) { 974 return DecodeVecShiftLImm(Inst, Imm, 8); 975 } 976 977 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 978 uint64_t Addr, 979 const void *Decoder) { 980 unsigned Rd = fieldFromInstruction(insn, 0, 5); 981 unsigned Rn = fieldFromInstruction(insn, 5, 5); 982 unsigned Rm = fieldFromInstruction(insn, 16, 5); 983 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 984 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 985 unsigned shift = (shiftHi << 6) | shiftLo; 986 switch (Inst.getOpcode()) { 987 default: 988 return Fail; 989 case AArch64::ADDWrs: 990 case AArch64::ADDSWrs: 991 case AArch64::SUBWrs: 992 case AArch64::SUBSWrs: 993 // if shift == '11' then ReservedValue() 994 if (shiftHi == 0x3) 995 return Fail; 996 LLVM_FALLTHROUGH; 997 case AArch64::ANDWrs: 998 case AArch64::ANDSWrs: 999 case AArch64::BICWrs: 1000 case AArch64::BICSWrs: 1001 case AArch64::ORRWrs: 1002 case AArch64::ORNWrs: 1003 case AArch64::EORWrs: 1004 case AArch64::EONWrs: { 1005 // if sf == '0' and imm6<5> == '1' then ReservedValue() 1006 if (shiftLo >> 5 == 1) 1007 return Fail; 1008 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1009 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1010 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1011 break; 1012 } 1013 case AArch64::ADDXrs: 1014 case AArch64::ADDSXrs: 1015 case AArch64::SUBXrs: 1016 case AArch64::SUBSXrs: 1017 // if shift == '11' then ReservedValue() 1018 if (shiftHi == 0x3) 1019 return Fail; 1020 LLVM_FALLTHROUGH; 1021 case AArch64::ANDXrs: 1022 case AArch64::ANDSXrs: 1023 case AArch64::BICXrs: 1024 case AArch64::BICSXrs: 1025 case AArch64::ORRXrs: 1026 case AArch64::ORNXrs: 1027 case AArch64::EORXrs: 1028 case AArch64::EONXrs: 1029 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1030 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1031 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1032 break; 1033 } 1034 1035 Inst.addOperand(MCOperand::createImm(shift)); 1036 return Success; 1037 } 1038 1039 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 1040 uint64_t Addr, 1041 const void *Decoder) { 1042 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1043 unsigned imm = fieldFromInstruction(insn, 5, 16); 1044 unsigned shift = fieldFromInstruction(insn, 21, 2); 1045 shift <<= 4; 1046 switch (Inst.getOpcode()) { 1047 default: 1048 return Fail; 1049 case AArch64::MOVZWi: 1050 case AArch64::MOVNWi: 1051 case AArch64::MOVKWi: 1052 if (shift & (1U << 5)) 1053 return Fail; 1054 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1055 break; 1056 case AArch64::MOVZXi: 1057 case AArch64::MOVNXi: 1058 case AArch64::MOVKXi: 1059 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1060 break; 1061 } 1062 1063 if (Inst.getOpcode() == AArch64::MOVKWi || 1064 Inst.getOpcode() == AArch64::MOVKXi) 1065 Inst.addOperand(Inst.getOperand(0)); 1066 1067 Inst.addOperand(MCOperand::createImm(imm)); 1068 Inst.addOperand(MCOperand::createImm(shift)); 1069 return Success; 1070 } 1071 1072 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 1073 uint64_t Addr, 1074 const void *Decoder) { 1075 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1076 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1077 unsigned offset = fieldFromInstruction(insn, 10, 12); 1078 const AArch64Disassembler *Dis = 1079 static_cast<const AArch64Disassembler *>(Decoder); 1080 1081 switch (Inst.getOpcode()) { 1082 default: 1083 return Fail; 1084 case AArch64::PRFMui: 1085 // Rt is an immediate in prefetch. 1086 Inst.addOperand(MCOperand::createImm(Rt)); 1087 break; 1088 case AArch64::STRBBui: 1089 case AArch64::LDRBBui: 1090 case AArch64::LDRSBWui: 1091 case AArch64::STRHHui: 1092 case AArch64::LDRHHui: 1093 case AArch64::LDRSHWui: 1094 case AArch64::STRWui: 1095 case AArch64::LDRWui: 1096 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1097 break; 1098 case AArch64::LDRSBXui: 1099 case AArch64::LDRSHXui: 1100 case AArch64::LDRSWui: 1101 case AArch64::STRXui: 1102 case AArch64::LDRXui: 1103 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1104 break; 1105 case AArch64::LDRQui: 1106 case AArch64::STRQui: 1107 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1108 break; 1109 case AArch64::LDRDui: 1110 case AArch64::STRDui: 1111 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1112 break; 1113 case AArch64::LDRSui: 1114 case AArch64::STRSui: 1115 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1116 break; 1117 case AArch64::LDRHui: 1118 case AArch64::STRHui: 1119 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1120 break; 1121 case AArch64::LDRBui: 1122 case AArch64::STRBui: 1123 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1124 break; 1125 } 1126 1127 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1128 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 1129 Inst.addOperand(MCOperand::createImm(offset)); 1130 return Success; 1131 } 1132 1133 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 1134 uint64_t Addr, 1135 const void *Decoder) { 1136 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1137 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1138 int64_t offset = fieldFromInstruction(insn, 12, 9); 1139 1140 // offset is a 9-bit signed immediate, so sign extend it to 1141 // fill the unsigned. 1142 if (offset & (1 << (9 - 1))) 1143 offset |= ~((1LL << 9) - 1); 1144 1145 // First operand is always the writeback to the address register, if needed. 1146 switch (Inst.getOpcode()) { 1147 default: 1148 break; 1149 case AArch64::LDRSBWpre: 1150 case AArch64::LDRSHWpre: 1151 case AArch64::STRBBpre: 1152 case AArch64::LDRBBpre: 1153 case AArch64::STRHHpre: 1154 case AArch64::LDRHHpre: 1155 case AArch64::STRWpre: 1156 case AArch64::LDRWpre: 1157 case AArch64::LDRSBWpost: 1158 case AArch64::LDRSHWpost: 1159 case AArch64::STRBBpost: 1160 case AArch64::LDRBBpost: 1161 case AArch64::STRHHpost: 1162 case AArch64::LDRHHpost: 1163 case AArch64::STRWpost: 1164 case AArch64::LDRWpost: 1165 case AArch64::LDRSBXpre: 1166 case AArch64::LDRSHXpre: 1167 case AArch64::STRXpre: 1168 case AArch64::LDRSWpre: 1169 case AArch64::LDRXpre: 1170 case AArch64::LDRSBXpost: 1171 case AArch64::LDRSHXpost: 1172 case AArch64::STRXpost: 1173 case AArch64::LDRSWpost: 1174 case AArch64::LDRXpost: 1175 case AArch64::LDRQpre: 1176 case AArch64::STRQpre: 1177 case AArch64::LDRQpost: 1178 case AArch64::STRQpost: 1179 case AArch64::LDRDpre: 1180 case AArch64::STRDpre: 1181 case AArch64::LDRDpost: 1182 case AArch64::STRDpost: 1183 case AArch64::LDRSpre: 1184 case AArch64::STRSpre: 1185 case AArch64::LDRSpost: 1186 case AArch64::STRSpost: 1187 case AArch64::LDRHpre: 1188 case AArch64::STRHpre: 1189 case AArch64::LDRHpost: 1190 case AArch64::STRHpost: 1191 case AArch64::LDRBpre: 1192 case AArch64::STRBpre: 1193 case AArch64::LDRBpost: 1194 case AArch64::STRBpost: 1195 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1196 break; 1197 } 1198 1199 switch (Inst.getOpcode()) { 1200 default: 1201 return Fail; 1202 case AArch64::PRFUMi: 1203 // Rt is an immediate in prefetch. 1204 Inst.addOperand(MCOperand::createImm(Rt)); 1205 break; 1206 case AArch64::STURBBi: 1207 case AArch64::LDURBBi: 1208 case AArch64::LDURSBWi: 1209 case AArch64::STURHHi: 1210 case AArch64::LDURHHi: 1211 case AArch64::LDURSHWi: 1212 case AArch64::STURWi: 1213 case AArch64::LDURWi: 1214 case AArch64::LDTRSBWi: 1215 case AArch64::LDTRSHWi: 1216 case AArch64::STTRWi: 1217 case AArch64::LDTRWi: 1218 case AArch64::STTRHi: 1219 case AArch64::LDTRHi: 1220 case AArch64::LDTRBi: 1221 case AArch64::STTRBi: 1222 case AArch64::LDRSBWpre: 1223 case AArch64::LDRSHWpre: 1224 case AArch64::STRBBpre: 1225 case AArch64::LDRBBpre: 1226 case AArch64::STRHHpre: 1227 case AArch64::LDRHHpre: 1228 case AArch64::STRWpre: 1229 case AArch64::LDRWpre: 1230 case AArch64::LDRSBWpost: 1231 case AArch64::LDRSHWpost: 1232 case AArch64::STRBBpost: 1233 case AArch64::LDRBBpost: 1234 case AArch64::STRHHpost: 1235 case AArch64::LDRHHpost: 1236 case AArch64::STRWpost: 1237 case AArch64::LDRWpost: 1238 case AArch64::STLURBi: 1239 case AArch64::STLURHi: 1240 case AArch64::STLURWi: 1241 case AArch64::LDAPURBi: 1242 case AArch64::LDAPURSBWi: 1243 case AArch64::LDAPURHi: 1244 case AArch64::LDAPURSHWi: 1245 case AArch64::LDAPURi: 1246 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1247 break; 1248 case AArch64::LDURSBXi: 1249 case AArch64::LDURSHXi: 1250 case AArch64::LDURSWi: 1251 case AArch64::STURXi: 1252 case AArch64::LDURXi: 1253 case AArch64::LDTRSBXi: 1254 case AArch64::LDTRSHXi: 1255 case AArch64::LDTRSWi: 1256 case AArch64::STTRXi: 1257 case AArch64::LDTRXi: 1258 case AArch64::LDRSBXpre: 1259 case AArch64::LDRSHXpre: 1260 case AArch64::STRXpre: 1261 case AArch64::LDRSWpre: 1262 case AArch64::LDRXpre: 1263 case AArch64::LDRSBXpost: 1264 case AArch64::LDRSHXpost: 1265 case AArch64::STRXpost: 1266 case AArch64::LDRSWpost: 1267 case AArch64::LDRXpost: 1268 case AArch64::LDAPURSWi: 1269 case AArch64::LDAPURSHXi: 1270 case AArch64::LDAPURSBXi: 1271 case AArch64::STLURXi: 1272 case AArch64::LDAPURXi: 1273 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1274 break; 1275 case AArch64::LDURQi: 1276 case AArch64::STURQi: 1277 case AArch64::LDRQpre: 1278 case AArch64::STRQpre: 1279 case AArch64::LDRQpost: 1280 case AArch64::STRQpost: 1281 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1282 break; 1283 case AArch64::LDURDi: 1284 case AArch64::STURDi: 1285 case AArch64::LDRDpre: 1286 case AArch64::STRDpre: 1287 case AArch64::LDRDpost: 1288 case AArch64::STRDpost: 1289 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1290 break; 1291 case AArch64::LDURSi: 1292 case AArch64::STURSi: 1293 case AArch64::LDRSpre: 1294 case AArch64::STRSpre: 1295 case AArch64::LDRSpost: 1296 case AArch64::STRSpost: 1297 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1298 break; 1299 case AArch64::LDURHi: 1300 case AArch64::STURHi: 1301 case AArch64::LDRHpre: 1302 case AArch64::STRHpre: 1303 case AArch64::LDRHpost: 1304 case AArch64::STRHpost: 1305 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1306 break; 1307 case AArch64::LDURBi: 1308 case AArch64::STURBi: 1309 case AArch64::LDRBpre: 1310 case AArch64::STRBpre: 1311 case AArch64::LDRBpost: 1312 case AArch64::STRBpost: 1313 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1314 break; 1315 } 1316 1317 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1318 Inst.addOperand(MCOperand::createImm(offset)); 1319 1320 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1321 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1322 bool IsFP = fieldFromInstruction(insn, 26, 1); 1323 1324 // Cannot write back to a transfer register (but xzr != sp). 1325 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1326 return SoftFail; 1327 1328 return Success; 1329 } 1330 1331 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 1332 uint64_t Addr, 1333 const void *Decoder) { 1334 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1335 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1336 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1337 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1338 1339 unsigned Opcode = Inst.getOpcode(); 1340 switch (Opcode) { 1341 default: 1342 return Fail; 1343 case AArch64::STLXRW: 1344 case AArch64::STLXRB: 1345 case AArch64::STLXRH: 1346 case AArch64::STXRW: 1347 case AArch64::STXRB: 1348 case AArch64::STXRH: 1349 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1350 LLVM_FALLTHROUGH; 1351 case AArch64::LDARW: 1352 case AArch64::LDARB: 1353 case AArch64::LDARH: 1354 case AArch64::LDAXRW: 1355 case AArch64::LDAXRB: 1356 case AArch64::LDAXRH: 1357 case AArch64::LDXRW: 1358 case AArch64::LDXRB: 1359 case AArch64::LDXRH: 1360 case AArch64::STLRW: 1361 case AArch64::STLRB: 1362 case AArch64::STLRH: 1363 case AArch64::STLLRW: 1364 case AArch64::STLLRB: 1365 case AArch64::STLLRH: 1366 case AArch64::LDLARW: 1367 case AArch64::LDLARB: 1368 case AArch64::LDLARH: 1369 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1370 break; 1371 case AArch64::STLXRX: 1372 case AArch64::STXRX: 1373 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1374 LLVM_FALLTHROUGH; 1375 case AArch64::LDARX: 1376 case AArch64::LDAXRX: 1377 case AArch64::LDXRX: 1378 case AArch64::STLRX: 1379 case AArch64::LDLARX: 1380 case AArch64::STLLRX: 1381 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1382 break; 1383 case AArch64::STLXPW: 1384 case AArch64::STXPW: 1385 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1386 LLVM_FALLTHROUGH; 1387 case AArch64::LDAXPW: 1388 case AArch64::LDXPW: 1389 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1390 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1391 break; 1392 case AArch64::STLXPX: 1393 case AArch64::STXPX: 1394 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1395 LLVM_FALLTHROUGH; 1396 case AArch64::LDAXPX: 1397 case AArch64::LDXPX: 1398 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1399 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1400 break; 1401 } 1402 1403 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1404 1405 // You shouldn't load to the same register twice in an instruction... 1406 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1407 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1408 Rt == Rt2) 1409 return SoftFail; 1410 1411 return Success; 1412 } 1413 1414 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1415 uint64_t Addr, 1416 const void *Decoder) { 1417 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1418 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1419 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1420 int64_t offset = fieldFromInstruction(insn, 15, 7); 1421 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1422 1423 // offset is a 7-bit signed immediate, so sign extend it to 1424 // fill the unsigned. 1425 if (offset & (1 << (7 - 1))) 1426 offset |= ~((1LL << 7) - 1); 1427 1428 unsigned Opcode = Inst.getOpcode(); 1429 bool NeedsDisjointWritebackTransfer = false; 1430 1431 // First operand is always writeback of base register. 1432 switch (Opcode) { 1433 default: 1434 break; 1435 case AArch64::LDPXpost: 1436 case AArch64::STPXpost: 1437 case AArch64::LDPSWpost: 1438 case AArch64::LDPXpre: 1439 case AArch64::STPXpre: 1440 case AArch64::LDPSWpre: 1441 case AArch64::LDPWpost: 1442 case AArch64::STPWpost: 1443 case AArch64::LDPWpre: 1444 case AArch64::STPWpre: 1445 case AArch64::LDPQpost: 1446 case AArch64::STPQpost: 1447 case AArch64::LDPQpre: 1448 case AArch64::STPQpre: 1449 case AArch64::LDPDpost: 1450 case AArch64::STPDpost: 1451 case AArch64::LDPDpre: 1452 case AArch64::STPDpre: 1453 case AArch64::LDPSpost: 1454 case AArch64::STPSpost: 1455 case AArch64::LDPSpre: 1456 case AArch64::STPSpre: 1457 case AArch64::STGPpre: 1458 case AArch64::STGPpost: 1459 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1460 break; 1461 } 1462 1463 switch (Opcode) { 1464 default: 1465 return Fail; 1466 case AArch64::LDPXpost: 1467 case AArch64::STPXpost: 1468 case AArch64::LDPSWpost: 1469 case AArch64::LDPXpre: 1470 case AArch64::STPXpre: 1471 case AArch64::LDPSWpre: 1472 case AArch64::STGPpre: 1473 case AArch64::STGPpost: 1474 NeedsDisjointWritebackTransfer = true; 1475 LLVM_FALLTHROUGH; 1476 case AArch64::LDNPXi: 1477 case AArch64::STNPXi: 1478 case AArch64::LDPXi: 1479 case AArch64::STPXi: 1480 case AArch64::LDPSWi: 1481 case AArch64::STGPi: 1482 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1483 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1484 break; 1485 case AArch64::LDPWpost: 1486 case AArch64::STPWpost: 1487 case AArch64::LDPWpre: 1488 case AArch64::STPWpre: 1489 NeedsDisjointWritebackTransfer = true; 1490 LLVM_FALLTHROUGH; 1491 case AArch64::LDNPWi: 1492 case AArch64::STNPWi: 1493 case AArch64::LDPWi: 1494 case AArch64::STPWi: 1495 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1496 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1497 break; 1498 case AArch64::LDNPQi: 1499 case AArch64::STNPQi: 1500 case AArch64::LDPQpost: 1501 case AArch64::STPQpost: 1502 case AArch64::LDPQi: 1503 case AArch64::STPQi: 1504 case AArch64::LDPQpre: 1505 case AArch64::STPQpre: 1506 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1507 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1508 break; 1509 case AArch64::LDNPDi: 1510 case AArch64::STNPDi: 1511 case AArch64::LDPDpost: 1512 case AArch64::STPDpost: 1513 case AArch64::LDPDi: 1514 case AArch64::STPDi: 1515 case AArch64::LDPDpre: 1516 case AArch64::STPDpre: 1517 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1518 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1519 break; 1520 case AArch64::LDNPSi: 1521 case AArch64::STNPSi: 1522 case AArch64::LDPSpost: 1523 case AArch64::STPSpost: 1524 case AArch64::LDPSi: 1525 case AArch64::STPSi: 1526 case AArch64::LDPSpre: 1527 case AArch64::STPSpre: 1528 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1529 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1530 break; 1531 } 1532 1533 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1534 Inst.addOperand(MCOperand::createImm(offset)); 1535 1536 // You shouldn't load to the same register twice in an instruction... 1537 if (IsLoad && Rt == Rt2) 1538 return SoftFail; 1539 1540 // ... or do any operation that writes-back to a transfer register. But note 1541 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1542 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1543 return SoftFail; 1544 1545 return Success; 1546 } 1547 1548 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, 1549 uint64_t Addr, 1550 const void *Decoder) { 1551 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1552 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1553 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 | 1554 fieldFromInstruction(insn, 12, 9); 1555 unsigned writeback = fieldFromInstruction(insn, 11, 1); 1556 1557 switch (Inst.getOpcode()) { 1558 default: 1559 return Fail; 1560 case AArch64::LDRAAwriteback: 1561 case AArch64::LDRABwriteback: 1562 DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr, 1563 Decoder); 1564 break; 1565 case AArch64::LDRAAindexed: 1566 case AArch64::LDRABindexed: 1567 break; 1568 } 1569 1570 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1571 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1572 DecodeSImm<10>(Inst, offset, Addr, Decoder); 1573 1574 if (writeback && Rt == Rn && Rn != 31) { 1575 return SoftFail; 1576 } 1577 1578 return Success; 1579 } 1580 1581 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1582 uint64_t Addr, 1583 const void *Decoder) { 1584 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1585 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1586 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1587 unsigned extend = fieldFromInstruction(insn, 10, 6); 1588 1589 unsigned shift = extend & 0x7; 1590 if (shift > 4) 1591 return Fail; 1592 1593 switch (Inst.getOpcode()) { 1594 default: 1595 return Fail; 1596 case AArch64::ADDWrx: 1597 case AArch64::SUBWrx: 1598 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1599 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1600 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1601 break; 1602 case AArch64::ADDSWrx: 1603 case AArch64::SUBSWrx: 1604 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1605 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1606 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1607 break; 1608 case AArch64::ADDXrx: 1609 case AArch64::SUBXrx: 1610 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1611 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1612 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1613 break; 1614 case AArch64::ADDSXrx: 1615 case AArch64::SUBSXrx: 1616 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1617 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1618 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1619 break; 1620 case AArch64::ADDXrx64: 1621 case AArch64::SUBXrx64: 1622 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1623 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1624 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1625 break; 1626 case AArch64::SUBSXrx64: 1627 case AArch64::ADDSXrx64: 1628 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1629 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1630 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1631 break; 1632 } 1633 1634 Inst.addOperand(MCOperand::createImm(extend)); 1635 return Success; 1636 } 1637 1638 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1639 uint64_t Addr, 1640 const void *Decoder) { 1641 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1642 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1643 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1644 unsigned imm; 1645 1646 if (Datasize) { 1647 if (Inst.getOpcode() == AArch64::ANDSXri) 1648 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1649 else 1650 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1651 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1652 imm = fieldFromInstruction(insn, 10, 13); 1653 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1654 return Fail; 1655 } else { 1656 if (Inst.getOpcode() == AArch64::ANDSWri) 1657 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1658 else 1659 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1660 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1661 imm = fieldFromInstruction(insn, 10, 12); 1662 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1663 return Fail; 1664 } 1665 Inst.addOperand(MCOperand::createImm(imm)); 1666 return Success; 1667 } 1668 1669 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1670 uint64_t Addr, 1671 const void *Decoder) { 1672 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1673 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1674 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1675 imm |= fieldFromInstruction(insn, 5, 5); 1676 1677 if (Inst.getOpcode() == AArch64::MOVID) 1678 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1679 else 1680 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1681 1682 Inst.addOperand(MCOperand::createImm(imm)); 1683 1684 switch (Inst.getOpcode()) { 1685 default: 1686 break; 1687 case AArch64::MOVIv4i16: 1688 case AArch64::MOVIv8i16: 1689 case AArch64::MVNIv4i16: 1690 case AArch64::MVNIv8i16: 1691 case AArch64::MOVIv2i32: 1692 case AArch64::MOVIv4i32: 1693 case AArch64::MVNIv2i32: 1694 case AArch64::MVNIv4i32: 1695 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1696 break; 1697 case AArch64::MOVIv2s_msl: 1698 case AArch64::MOVIv4s_msl: 1699 case AArch64::MVNIv2s_msl: 1700 case AArch64::MVNIv4s_msl: 1701 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108)); 1702 break; 1703 } 1704 1705 return Success; 1706 } 1707 1708 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1709 uint64_t Addr, 1710 const void *Decoder) { 1711 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1712 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1713 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1714 imm |= fieldFromInstruction(insn, 5, 5); 1715 1716 // Tied operands added twice. 1717 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1718 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1719 1720 Inst.addOperand(MCOperand::createImm(imm)); 1721 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1722 1723 return Success; 1724 } 1725 1726 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1727 uint64_t Addr, const void *Decoder) { 1728 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1729 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1730 imm |= fieldFromInstruction(insn, 29, 2); 1731 const AArch64Disassembler *Dis = 1732 static_cast<const AArch64Disassembler *>(Decoder); 1733 1734 // Sign-extend the 21-bit immediate. 1735 if (imm & (1 << (21 - 1))) 1736 imm |= ~((1LL << 21) - 1); 1737 1738 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1739 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 1740 Inst.addOperand(MCOperand::createImm(imm)); 1741 1742 return Success; 1743 } 1744 1745 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, 1746 uint64_t Addr, const void *Decoder) { 1747 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1748 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1749 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1750 unsigned S = fieldFromInstruction(insn, 29, 1); 1751 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1752 1753 unsigned ShifterVal = (Imm >> 12) & 3; 1754 unsigned ImmVal = Imm & 0xFFF; 1755 const AArch64Disassembler *Dis = 1756 static_cast<const AArch64Disassembler *>(Decoder); 1757 1758 if (ShifterVal != 0 && ShifterVal != 1) 1759 return Fail; 1760 1761 if (Datasize) { 1762 if (Rd == 31 && !S) 1763 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1764 else 1765 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1766 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1767 } else { 1768 if (Rd == 31 && !S) 1769 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1770 else 1771 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1772 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1773 } 1774 1775 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 1776 Inst.addOperand(MCOperand::createImm(ImmVal)); 1777 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1778 return Success; 1779 } 1780 1781 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1782 uint64_t Addr, 1783 const void *Decoder) { 1784 int64_t imm = fieldFromInstruction(insn, 0, 26); 1785 const AArch64Disassembler *Dis = 1786 static_cast<const AArch64Disassembler *>(Decoder); 1787 1788 // Sign-extend the 26-bit immediate. 1789 if (imm & (1 << (26 - 1))) 1790 imm |= ~((1LL << 26) - 1); 1791 1792 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) 1793 Inst.addOperand(MCOperand::createImm(imm)); 1794 1795 return Success; 1796 } 1797 1798 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 1799 uint64_t Addr, 1800 const void *Decoder) { 1801 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1802 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1803 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1804 uint64_t pstate_field = (op1 << 3) | op2; 1805 1806 switch (pstate_field) { 1807 case 0x01: // XAFlag 1808 case 0x02: // AXFlag 1809 return Fail; 1810 } 1811 1812 if ((pstate_field == AArch64PState::PAN || 1813 pstate_field == AArch64PState::UAO || 1814 pstate_field == AArch64PState::SSBS) && crm > 1) 1815 return Fail; 1816 1817 Inst.addOperand(MCOperand::createImm(pstate_field)); 1818 Inst.addOperand(MCOperand::createImm(crm)); 1819 1820 const AArch64Disassembler *Dis = 1821 static_cast<const AArch64Disassembler *>(Decoder); 1822 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1823 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits())) 1824 return Success; 1825 return Fail; 1826 } 1827 1828 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1829 uint64_t Addr, const void *Decoder) { 1830 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1831 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1832 bit |= fieldFromInstruction(insn, 19, 5); 1833 int64_t dst = fieldFromInstruction(insn, 5, 14); 1834 const AArch64Disassembler *Dis = 1835 static_cast<const AArch64Disassembler *>(Decoder); 1836 1837 // Sign-extend 14-bit immediate. 1838 if (dst & (1 << (14 - 1))) 1839 dst |= ~((1LL << 14) - 1); 1840 1841 if (fieldFromInstruction(insn, 31, 1) == 0) 1842 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1843 else 1844 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1845 Inst.addOperand(MCOperand::createImm(bit)); 1846 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) 1847 Inst.addOperand(MCOperand::createImm(dst)); 1848 1849 return Success; 1850 } 1851 1852 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, 1853 unsigned RegClassID, 1854 unsigned RegNo, 1855 uint64_t Addr, 1856 const void *Decoder) { 1857 // Register number must be even (see CASP instruction) 1858 if (RegNo & 0x1) 1859 return Fail; 1860 1861 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); 1862 Inst.addOperand(MCOperand::createReg(Reg)); 1863 return Success; 1864 } 1865 1866 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 1867 unsigned RegNo, 1868 uint64_t Addr, 1869 const void *Decoder) { 1870 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1871 AArch64::WSeqPairsClassRegClassID, 1872 RegNo, Addr, Decoder); 1873 } 1874 1875 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 1876 unsigned RegNo, 1877 uint64_t Addr, 1878 const void *Decoder) { 1879 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1880 AArch64::XSeqPairsClassRegClassID, 1881 RegNo, Addr, Decoder); 1882 } 1883 1884 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, 1885 uint32_t insn, 1886 uint64_t Addr, 1887 const void *Decoder) { 1888 unsigned Zdn = fieldFromInstruction(insn, 0, 5); 1889 unsigned imm = fieldFromInstruction(insn, 5, 13); 1890 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1891 return Fail; 1892 1893 // The same (tied) operand is added twice to the instruction. 1894 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1895 if (Inst.getOpcode() != AArch64::DUPM_ZI) 1896 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); 1897 Inst.addOperand(MCOperand::createImm(imm)); 1898 return Success; 1899 } 1900 1901 template<int Bits> 1902 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 1903 uint64_t Address, const void *Decoder) { 1904 if (Imm & ~((1LL << Bits) - 1)) 1905 return Fail; 1906 1907 // Imm is a signed immediate, so sign extend it. 1908 if (Imm & (1 << (Bits - 1))) 1909 Imm |= ~((1LL << Bits) - 1); 1910 1911 Inst.addOperand(MCOperand::createImm(Imm)); 1912 return Success; 1913 } 1914 1915 // Decode 8-bit signed/unsigned immediate for a given element width. 1916 template <int ElementWidth> 1917 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, 1918 uint64_t Addr, const void *Decoder) { 1919 unsigned Val = (uint8_t)Imm; 1920 unsigned Shift = (Imm & 0x100) ? 8 : 0; 1921 if (ElementWidth == 8 && Shift) 1922 return Fail; 1923 Inst.addOperand(MCOperand::createImm(Val)); 1924 Inst.addOperand(MCOperand::createImm(Shift)); 1925 return Success; 1926 } 1927 1928 // Decode uimm4 ranged from 1-16. 1929 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, 1930 uint64_t Addr, const void *Decoder) { 1931 Inst.addOperand(MCOperand::createImm(Imm + 1)); 1932 return Success; 1933 } 1934