xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp (revision e9ac41698b2f322d55ccf9da50a3596edb2c1800) 
1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "AArch64TargetMachine.h"
13 #include "AArch64.h"
14 #include "AArch64LoopIdiomTransform.h"
15 #include "AArch64MachineFunctionInfo.h"
16 #include "AArch64MachineScheduler.h"
17 #include "AArch64MacroFusion.h"
18 #include "AArch64Subtarget.h"
19 #include "AArch64TargetObjectFile.h"
20 #include "AArch64TargetTransformInfo.h"
21 #include "MCTargetDesc/AArch64MCTargetDesc.h"
22 #include "TargetInfo/AArch64TargetInfo.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/Analysis/TargetTransformInfo.h"
25 #include "llvm/Analysis/ValueTracking.h"
26 #include "llvm/CodeGen/CFIFixup.h"
27 #include "llvm/CodeGen/CSEConfigBase.h"
28 #include "llvm/CodeGen/GlobalISel/CSEInfo.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/LoadStoreOpt.h"
33 #include "llvm/CodeGen/GlobalISel/Localizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/MIRParser/MIParser.h"
36 #include "llvm/CodeGen/MachineScheduler.h"
37 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/CodeGen/TargetInstrInfo.h"
39 #include "llvm/CodeGen/TargetPassConfig.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/InitializePasses.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCTargetOptions.h"
45 #include "llvm/MC/TargetRegistry.h"
46 #include "llvm/Pass.h"
47 #include "llvm/Passes/PassBuilder.h"
48 #include "llvm/Support/CodeGen.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Target/TargetLoweringObjectFile.h"
51 #include "llvm/Target/TargetOptions.h"
52 #include "llvm/TargetParser/Triple.h"
53 #include "llvm/Transforms/CFGuard.h"
54 #include "llvm/Transforms/Scalar.h"
55 #include <memory>
56 #include <optional>
57 #include <string>
58 
59 using namespace llvm;
60 
61 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
62                                 cl::desc("Enable the CCMP formation pass"),
63                                 cl::init(true), cl::Hidden);
64 
65 static cl::opt<bool>
66     EnableCondBrTuning("aarch64-enable-cond-br-tune",
67                        cl::desc("Enable the conditional branch tuning pass"),
68                        cl::init(true), cl::Hidden);
69 
70 static cl::opt<bool> EnableAArch64CopyPropagation(
71     "aarch64-enable-copy-propagation",
72     cl::desc("Enable the copy propagation with AArch64 copy instr"),
73     cl::init(true), cl::Hidden);
74 
75 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
76                                cl::desc("Enable the machine combiner pass"),
77                                cl::init(true), cl::Hidden);
78 
79 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
80                                           cl::desc("Suppress STP for AArch64"),
81                                           cl::init(true), cl::Hidden);
82 
83 static cl::opt<bool> EnableAdvSIMDScalar(
84     "aarch64-enable-simd-scalar",
85     cl::desc("Enable use of AdvSIMD scalar integer instructions"),
86     cl::init(false), cl::Hidden);
87 
88 static cl::opt<bool>
89     EnablePromoteConstant("aarch64-enable-promote-const",
90                           cl::desc("Enable the promote constant pass"),
91                           cl::init(true), cl::Hidden);
92 
93 static cl::opt<bool> EnableCollectLOH(
94     "aarch64-enable-collect-loh",
95     cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
96     cl::init(true), cl::Hidden);
97 
98 static cl::opt<bool>
99     EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
100                                   cl::desc("Enable the pass that removes dead"
101                                            " definitons and replaces stores to"
102                                            " them with stores to the zero"
103                                            " register"),
104                                   cl::init(true));
105 
106 static cl::opt<bool> EnableRedundantCopyElimination(
107     "aarch64-enable-copyelim",
108     cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
109     cl::Hidden);
110 
111 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
112                                         cl::desc("Enable the load/store pair"
113                                                  " optimization pass"),
114                                         cl::init(true), cl::Hidden);
115 
116 static cl::opt<bool> EnableAtomicTidy(
117     "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
118     cl::desc("Run SimplifyCFG after expanding atomic operations"
119              " to make use of cmpxchg flow-based information"),
120     cl::init(true));
121 
122 static cl::opt<bool>
123 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
124                         cl::desc("Run early if-conversion"),
125                         cl::init(true));
126 
127 static cl::opt<bool>
128     EnableCondOpt("aarch64-enable-condopt",
129                   cl::desc("Enable the condition optimizer pass"),
130                   cl::init(true), cl::Hidden);
131 
132 static cl::opt<bool>
133     EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
134                  cl::desc("Enable optimizations on complex GEPs"),
135                  cl::init(false));
136 
137 static cl::opt<bool>
138     EnableSelectOpt("aarch64-select-opt", cl::Hidden,
139                     cl::desc("Enable select to branch optimizations"),
140                     cl::init(true));
141 
142 static cl::opt<bool>
143     BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
144                      cl::desc("Relax out of range conditional branches"));
145 
146 static cl::opt<bool> EnableCompressJumpTables(
147     "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
148     cl::desc("Use smallest entry possible for jump tables"));
149 
150 // FIXME: Unify control over GlobalMerge.
151 static cl::opt<cl::boolOrDefault>
152     EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
153                       cl::desc("Enable the global merge pass"));
154 
155 static cl::opt<bool>
156     EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
157                            cl::desc("Enable the loop data prefetch pass"),
158                            cl::init(true));
159 
160 static cl::opt<int> EnableGlobalISelAtO(
161     "aarch64-enable-global-isel-at-O", cl::Hidden,
162     cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
163     cl::init(0));
164 
165 static cl::opt<bool>
166     EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden,
167                            cl::desc("Enable SVE intrinsic opts"),
168                            cl::init(true));
169 
170 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
171                                          cl::init(true), cl::Hidden);
172 
173 static cl::opt<bool>
174     EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
175                         cl::desc("Enable the AArch64 branch target pass"),
176                         cl::init(true));
177 
178 static cl::opt<unsigned> SVEVectorBitsMaxOpt(
179     "aarch64-sve-vector-bits-max",
180     cl::desc("Assume SVE vector registers are at most this big, "
181              "with zero meaning no maximum size is assumed."),
182     cl::init(0), cl::Hidden);
183 
184 static cl::opt<unsigned> SVEVectorBitsMinOpt(
185     "aarch64-sve-vector-bits-min",
186     cl::desc("Assume SVE vector registers are at least this big, "
187              "with zero meaning no minimum size is assumed."),
188     cl::init(0), cl::Hidden);
189 
190 extern cl::opt<bool> EnableHomogeneousPrologEpilog;
191 
192 static cl::opt<bool> EnableGISelLoadStoreOptPreLegal(
193     "aarch64-enable-gisel-ldst-prelegal",
194     cl::desc("Enable GlobalISel's pre-legalizer load/store optimization pass"),
195     cl::init(true), cl::Hidden);
196 
197 static cl::opt<bool> EnableGISelLoadStoreOptPostLegal(
198     "aarch64-enable-gisel-ldst-postlegal",
199     cl::desc("Enable GlobalISel's post-legalizer load/store optimization pass"),
200     cl::init(false), cl::Hidden);
201 
202 static cl::opt<bool>
203     EnableSinkFold("aarch64-enable-sink-fold",
204                    cl::desc("Enable sinking and folding of instruction copies"),
205                    cl::init(true), cl::Hidden);
206 
207 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() {
208   // Register the target.
209   RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
210   RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
211   RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
212   RegisterTargetMachine<AArch64leTargetMachine> W(getTheARM64_32Target());
213   RegisterTargetMachine<AArch64leTargetMachine> V(getTheAArch64_32Target());
214   auto PR = PassRegistry::getPassRegistry();
215   initializeGlobalISel(*PR);
216   initializeAArch64A53Fix835769Pass(*PR);
217   initializeAArch64A57FPLoadBalancingPass(*PR);
218   initializeAArch64AdvSIMDScalarPass(*PR);
219   initializeAArch64BranchTargetsPass(*PR);
220   initializeAArch64CollectLOHPass(*PR);
221   initializeAArch64CompressJumpTablesPass(*PR);
222   initializeAArch64ConditionalComparesPass(*PR);
223   initializeAArch64ConditionOptimizerPass(*PR);
224   initializeAArch64DeadRegisterDefinitionsPass(*PR);
225   initializeAArch64ExpandPseudoPass(*PR);
226   initializeAArch64LoadStoreOptPass(*PR);
227   initializeAArch64LoopIdiomTransformLegacyPassPass(*PR);
228   initializeAArch64MIPeepholeOptPass(*PR);
229   initializeAArch64SIMDInstrOptPass(*PR);
230   initializeAArch64O0PreLegalizerCombinerPass(*PR);
231   initializeAArch64PreLegalizerCombinerPass(*PR);
232   initializeAArch64PointerAuthPass(*PR);
233   initializeAArch64PostLegalizerCombinerPass(*PR);
234   initializeAArch64PostLegalizerLoweringPass(*PR);
235   initializeAArch64PostSelectOptimizePass(*PR);
236   initializeAArch64PromoteConstantPass(*PR);
237   initializeAArch64RedundantCopyEliminationPass(*PR);
238   initializeAArch64StorePairSuppressPass(*PR);
239   initializeFalkorHWPFFixPass(*PR);
240   initializeFalkorMarkStridedAccessesLegacyPass(*PR);
241   initializeLDTLSCleanupPass(*PR);
242   initializeKCFIPass(*PR);
243   initializeSMEABIPass(*PR);
244   initializeSVEIntrinsicOptsPass(*PR);
245   initializeAArch64SpeculationHardeningPass(*PR);
246   initializeAArch64SLSHardeningPass(*PR);
247   initializeAArch64StackTaggingPass(*PR);
248   initializeAArch64StackTaggingPreRAPass(*PR);
249   initializeAArch64LowerHomogeneousPrologEpilogPass(*PR);
250   initializeAArch64DAGToDAGISelPass(*PR);
251   initializeAArch64GlobalsTaggingPass(*PR);
252 }
253 
254 //===----------------------------------------------------------------------===//
255 // AArch64 Lowering public interface.
256 //===----------------------------------------------------------------------===//
257 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
258   if (TT.isOSBinFormatMachO())
259     return std::make_unique<AArch64_MachoTargetObjectFile>();
260   if (TT.isOSBinFormatCOFF())
261     return std::make_unique<AArch64_COFFTargetObjectFile>();
262 
263   return std::make_unique<AArch64_ELFTargetObjectFile>();
264 }
265 
266 // Helper function to build a DataLayout string
267 static std::string computeDataLayout(const Triple &TT,
268                                      const MCTargetOptions &Options,
269                                      bool LittleEndian) {
270   if (TT.isOSBinFormatMachO()) {
271     if (TT.getArch() == Triple::aarch64_32)
272       return "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128";
273     return "e-m:o-i64:64-i128:128-n32:64-S128";
274   }
275   if (TT.isOSBinFormatCOFF())
276     return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
277   std::string Endian = LittleEndian ? "e" : "E";
278   std::string Ptr32 = TT.getEnvironment() == Triple::GNUILP32 ? "-p:32:32" : "";
279   return Endian + "-m:e" + Ptr32 +
280          "-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
281 }
282 
283 static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU) {
284   if (CPU.empty() && TT.isArm64e())
285     return "apple-a12";
286   return CPU;
287 }
288 
289 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
290                                            std::optional<Reloc::Model> RM) {
291   // AArch64 Darwin and Windows are always PIC.
292   if (TT.isOSDarwin() || TT.isOSWindows())
293     return Reloc::PIC_;
294   // On ELF platforms the default static relocation model has a smart enough
295   // linker to cope with referencing external symbols defined in a shared
296   // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
297   if (!RM || *RM == Reloc::DynamicNoPIC)
298     return Reloc::Static;
299   return *RM;
300 }
301 
302 static CodeModel::Model
303 getEffectiveAArch64CodeModel(const Triple &TT,
304                              std::optional<CodeModel::Model> CM, bool JIT) {
305   if (CM) {
306     if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
307         *CM != CodeModel::Large) {
308       report_fatal_error(
309           "Only small, tiny and large code models are allowed on AArch64");
310     } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
311       report_fatal_error("tiny code model is only supported on ELF");
312     return *CM;
313   }
314   // The default MCJIT memory managers make no guarantees about where they can
315   // find an executable page; JITed code needs to be able to refer to globals
316   // no matter how far away they are.
317   // We should set the CodeModel::Small for Windows ARM64 in JIT mode,
318   // since with large code model LLVM generating 4 MOV instructions, and
319   // Windows doesn't support relocating these long branch (4 MOVs).
320   if (JIT && !TT.isOSWindows())
321     return CodeModel::Large;
322   return CodeModel::Small;
323 }
324 
325 /// Create an AArch64 architecture model.
326 ///
327 AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
328                                            StringRef CPU, StringRef FS,
329                                            const TargetOptions &Options,
330                                            std::optional<Reloc::Model> RM,
331                                            std::optional<CodeModel::Model> CM,
332                                            CodeGenOptLevel OL, bool JIT,
333                                            bool LittleEndian)
334     : LLVMTargetMachine(T,
335                         computeDataLayout(TT, Options.MCOptions, LittleEndian),
336                         TT, computeDefaultCPU(TT, CPU), FS, Options,
337                         getEffectiveRelocModel(TT, RM),
338                         getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
339       TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
340   initAsmInfo();
341 
342   if (TT.isOSBinFormatMachO()) {
343     this->Options.TrapUnreachable = true;
344     this->Options.NoTrapAfterNoreturn = true;
345   }
346 
347   if (getMCAsmInfo()->usesWindowsCFI()) {
348     // Unwinding can get confused if the last instruction in an
349     // exception-handling region (function, funclet, try block, etc.)
350     // is a call.
351     //
352     // FIXME: We could elide the trap if the next instruction would be in
353     // the same region anyway.
354     this->Options.TrapUnreachable = true;
355   }
356 
357   if (this->Options.TLSSize == 0) // default
358     this->Options.TLSSize = 24;
359   if ((getCodeModel() == CodeModel::Small ||
360        getCodeModel() == CodeModel::Kernel) &&
361       this->Options.TLSSize > 32)
362     // for the small (and kernel) code model, the maximum TLS size is 4GiB
363     this->Options.TLSSize = 32;
364   else if (getCodeModel() == CodeModel::Tiny && this->Options.TLSSize > 24)
365     // for the tiny code model, the maximum TLS size is 1MiB (< 16MiB)
366     this->Options.TLSSize = 24;
367 
368   // Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
369   // MachO/CodeModel::Large, which GlobalISel does not support.
370   if (static_cast<int>(getOptLevel()) <= EnableGlobalISelAtO &&
371       TT.getArch() != Triple::aarch64_32 &&
372       TT.getEnvironment() != Triple::GNUILP32 &&
373       !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) {
374     setGlobalISel(true);
375     setGlobalISelAbort(GlobalISelAbortMode::Disable);
376   }
377 
378   // AArch64 supports the MachineOutliner.
379   setMachineOutliner(true);
380 
381   // AArch64 supports default outlining behaviour.
382   setSupportsDefaultOutlining(true);
383 
384   // AArch64 supports the debug entry values.
385   setSupportsDebugEntryValues(true);
386 
387   // AArch64 supports fixing up the DWARF unwind information.
388   if (!getMCAsmInfo()->usesWindowsCFI())
389     setCFIFixup(true);
390 }
391 
392 AArch64TargetMachine::~AArch64TargetMachine() = default;
393 
394 const AArch64Subtarget *
395 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
396   Attribute CPUAttr = F.getFnAttribute("target-cpu");
397   Attribute TuneAttr = F.getFnAttribute("tune-cpu");
398   Attribute FSAttr = F.getFnAttribute("target-features");
399 
400   StringRef CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString() : TargetCPU;
401   StringRef TuneCPU = TuneAttr.isValid() ? TuneAttr.getValueAsString() : CPU;
402   StringRef FS = FSAttr.isValid() ? FSAttr.getValueAsString() : TargetFS;
403   bool HasMinSize = F.hasMinSize();
404 
405   bool StreamingSVEMode = F.hasFnAttribute("aarch64_pstate_sm_enabled") ||
406                           F.hasFnAttribute("aarch64_pstate_sm_body");
407   bool StreamingCompatibleSVEMode =
408       F.hasFnAttribute("aarch64_pstate_sm_compatible");
409 
410   unsigned MinSVEVectorSize = 0;
411   unsigned MaxSVEVectorSize = 0;
412   if (F.hasFnAttribute(Attribute::VScaleRange)) {
413     ConstantRange CR = getVScaleRange(&F, 64);
414     MinSVEVectorSize = CR.getUnsignedMin().getZExtValue() * 128;
415     MaxSVEVectorSize = CR.getUnsignedMax().getZExtValue() * 128;
416   } else {
417     MinSVEVectorSize = SVEVectorBitsMinOpt;
418     MaxSVEVectorSize = SVEVectorBitsMaxOpt;
419   }
420 
421   assert(MinSVEVectorSize % 128 == 0 &&
422          "SVE requires vector length in multiples of 128!");
423   assert(MaxSVEVectorSize % 128 == 0 &&
424          "SVE requires vector length in multiples of 128!");
425   assert((MaxSVEVectorSize >= MinSVEVectorSize || MaxSVEVectorSize == 0) &&
426          "Minimum SVE vector size should not be larger than its maximum!");
427 
428   // Sanitize user input in case of no asserts
429   if (MaxSVEVectorSize != 0) {
430     MinSVEVectorSize = std::min(MinSVEVectorSize, MaxSVEVectorSize);
431     MaxSVEVectorSize = std::max(MinSVEVectorSize, MaxSVEVectorSize);
432   }
433 
434   SmallString<512> Key;
435   raw_svector_ostream(Key) << "SVEMin" << MinSVEVectorSize << "SVEMax"
436                            << MaxSVEVectorSize
437                            << "StreamingSVEMode=" << StreamingSVEMode
438                            << "StreamingCompatibleSVEMode="
439                            << StreamingCompatibleSVEMode << CPU << TuneCPU << FS
440                            << "HasMinSize=" << HasMinSize;
441 
442   auto &I = SubtargetMap[Key];
443   if (!I) {
444     // This needs to be done before we create a new subtarget since any
445     // creation will depend on the TM and the code generation flags on the
446     // function that reside in TargetOptions.
447     resetTargetOptions(F);
448     I = std::make_unique<AArch64Subtarget>(
449         TargetTriple, CPU, TuneCPU, FS, *this, isLittle, MinSVEVectorSize,
450         MaxSVEVectorSize, StreamingSVEMode, StreamingCompatibleSVEMode,
451         HasMinSize);
452   }
453 
454   assert((!StreamingSVEMode || I->hasSME()) &&
455          "Expected SME to be available");
456 
457   return I.get();
458 }
459 
460 void AArch64leTargetMachine::anchor() { }
461 
462 AArch64leTargetMachine::AArch64leTargetMachine(
463     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
464     const TargetOptions &Options, std::optional<Reloc::Model> RM,
465     std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT)
466     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
467 
468 void AArch64beTargetMachine::anchor() { }
469 
470 AArch64beTargetMachine::AArch64beTargetMachine(
471     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
472     const TargetOptions &Options, std::optional<Reloc::Model> RM,
473     std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT)
474     : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
475 
476 namespace {
477 
478 /// AArch64 Code Generator Pass Configuration Options.
479 class AArch64PassConfig : public TargetPassConfig {
480 public:
481   AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
482       : TargetPassConfig(TM, PM) {
483     if (TM.getOptLevel() != CodeGenOptLevel::None)
484       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
485     setEnableSinkAndFold(EnableSinkFold);
486   }
487 
488   AArch64TargetMachine &getAArch64TargetMachine() const {
489     return getTM<AArch64TargetMachine>();
490   }
491 
492   ScheduleDAGInstrs *
493   createMachineScheduler(MachineSchedContext *C) const override {
494     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
495     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
496     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
497     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
498     if (ST.hasFusion())
499       DAG->addMutation(createAArch64MacroFusionDAGMutation());
500     return DAG;
501   }
502 
503   ScheduleDAGInstrs *
504   createPostMachineScheduler(MachineSchedContext *C) const override {
505     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
506     ScheduleDAGMI *DAG =
507         new ScheduleDAGMI(C, std::make_unique<AArch64PostRASchedStrategy>(C),
508                           /* RemoveKillFlags=*/true);
509     if (ST.hasFusion()) {
510       // Run the Macro Fusion after RA again since literals are expanded from
511       // pseudos then (v. addPreSched2()).
512       DAG->addMutation(createAArch64MacroFusionDAGMutation());
513       return DAG;
514     }
515 
516     return DAG;
517   }
518 
519   void addIRPasses()  override;
520   bool addPreISel() override;
521   void addCodeGenPrepare() override;
522   bool addInstSelector() override;
523   bool addIRTranslator() override;
524   void addPreLegalizeMachineIR() override;
525   bool addLegalizeMachineIR() override;
526   void addPreRegBankSelect() override;
527   bool addRegBankSelect() override;
528   bool addGlobalInstructionSelect() override;
529   void addMachineSSAOptimization() override;
530   bool addILPOpts() override;
531   void addPreRegAlloc() override;
532   void addPostRegAlloc() override;
533   void addPreSched2() override;
534   void addPreEmitPass() override;
535   void addPostBBSections() override;
536   void addPreEmitPass2() override;
537 
538   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
539 };
540 
541 } // end anonymous namespace
542 
543 void AArch64TargetMachine::registerPassBuilderCallbacks(
544     PassBuilder &PB, bool PopulateClassToPassNames) {
545   PB.registerLateLoopOptimizationsEPCallback(
546       [=](LoopPassManager &LPM, OptimizationLevel Level) {
547         LPM.addPass(AArch64LoopIdiomTransformPass());
548       });
549 }
550 
551 TargetTransformInfo
552 AArch64TargetMachine::getTargetTransformInfo(const Function &F) const {
553   return TargetTransformInfo(AArch64TTIImpl(this, F));
554 }
555 
556 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
557   return new AArch64PassConfig(*this, PM);
558 }
559 
560 std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
561   return getStandardCSEConfigForOpt(TM->getOptLevel());
562 }
563 
564 void AArch64PassConfig::addIRPasses() {
565   // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
566   // ourselves.
567   addPass(createAtomicExpandPass());
568 
569   // Expand any SVE vector library calls that we can't code generate directly.
570   if (EnableSVEIntrinsicOpts &&
571       TM->getOptLevel() == CodeGenOptLevel::Aggressive)
572     addPass(createSVEIntrinsicOptsPass());
573 
574   // Cmpxchg instructions are often used with a subsequent comparison to
575   // determine whether it succeeded. We can exploit existing control-flow in
576   // ldrex/strex loops to simplify this, but it needs tidying up.
577   if (TM->getOptLevel() != CodeGenOptLevel::None && EnableAtomicTidy)
578     addPass(createCFGSimplificationPass(SimplifyCFGOptions()
579                                             .forwardSwitchCondToPhi(true)
580                                             .convertSwitchRangeToICmp(true)
581                                             .convertSwitchToLookupTable(true)
582                                             .needCanonicalLoops(false)
583                                             .hoistCommonInsts(true)
584                                             .sinkCommonInsts(true)));
585 
586   // Run LoopDataPrefetch
587   //
588   // Run this before LSR to remove the multiplies involved in computing the
589   // pointer values N iterations ahead.
590   if (TM->getOptLevel() != CodeGenOptLevel::None) {
591     if (EnableLoopDataPrefetch)
592       addPass(createLoopDataPrefetchPass());
593     if (EnableFalkorHWPFFix)
594       addPass(createFalkorMarkStridedAccessesPass());
595   }
596 
597   if (TM->getOptLevel() == CodeGenOptLevel::Aggressive && EnableGEPOpt) {
598     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
599     // and lower a GEP with multiple indices to either arithmetic operations or
600     // multiple GEPs with single index.
601     addPass(createSeparateConstOffsetFromGEPPass(true));
602     // Call EarlyCSE pass to find and remove subexpressions in the lowered
603     // result.
604     addPass(createEarlyCSEPass());
605     // Do loop invariant code motion in case part of the lowered result is
606     // invariant.
607     addPass(createLICMPass());
608   }
609 
610   TargetPassConfig::addIRPasses();
611 
612   if (getOptLevel() == CodeGenOptLevel::Aggressive && EnableSelectOpt)
613     addPass(createSelectOptimizePass());
614 
615   addPass(createAArch64GlobalsTaggingPass());
616   addPass(createAArch64StackTaggingPass(
617       /*IsOptNone=*/TM->getOptLevel() == CodeGenOptLevel::None));
618 
619   // Match complex arithmetic patterns
620   if (TM->getOptLevel() >= CodeGenOptLevel::Default)
621     addPass(createComplexDeinterleavingPass(TM));
622 
623   // Match interleaved memory accesses to ldN/stN intrinsics.
624   if (TM->getOptLevel() != CodeGenOptLevel::None) {
625     addPass(createInterleavedLoadCombinePass());
626     addPass(createInterleavedAccessPass());
627   }
628 
629   // Expand any functions marked with SME attributes which require special
630   // changes for the calling convention or that require the lazy-saving
631   // mechanism specified in the SME ABI.
632   addPass(createSMEABIPass());
633 
634   // Add Control Flow Guard checks.
635   if (TM->getTargetTriple().isOSWindows()) {
636     if (TM->getTargetTriple().isWindowsArm64EC())
637       addPass(createAArch64Arm64ECCallLoweringPass());
638     else
639       addPass(createCFGuardCheckPass());
640   }
641 
642   if (TM->Options.JMCInstrument)
643     addPass(createJMCInstrumenterPass());
644 }
645 
646 // Pass Pipeline Configuration
647 bool AArch64PassConfig::addPreISel() {
648   // Run promote constant before global merge, so that the promoted constants
649   // get a chance to be merged
650   if (TM->getOptLevel() != CodeGenOptLevel::None && EnablePromoteConstant)
651     addPass(createAArch64PromoteConstantPass());
652   // FIXME: On AArch64, this depends on the type.
653   // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
654   // and the offset has to be a multiple of the related size in bytes.
655   if ((TM->getOptLevel() != CodeGenOptLevel::None &&
656        EnableGlobalMerge == cl::BOU_UNSET) ||
657       EnableGlobalMerge == cl::BOU_TRUE) {
658     bool OnlyOptimizeForSize =
659         (TM->getOptLevel() < CodeGenOptLevel::Aggressive) &&
660         (EnableGlobalMerge == cl::BOU_UNSET);
661 
662     // Merging of extern globals is enabled by default on non-Mach-O as we
663     // expect it to be generally either beneficial or harmless. On Mach-O it
664     // is disabled as we emit the .subsections_via_symbols directive which
665     // means that merging extern globals is not safe.
666     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
667 
668     // FIXME: extern global merging is only enabled when we optimise for size
669     // because there are some regressions with it also enabled for performance.
670     if (!OnlyOptimizeForSize)
671       MergeExternalByDefault = false;
672 
673     addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize,
674                                   MergeExternalByDefault));
675   }
676 
677   return false;
678 }
679 
680 void AArch64PassConfig::addCodeGenPrepare() {
681   if (getOptLevel() != CodeGenOptLevel::None)
682     addPass(createTypePromotionLegacyPass());
683   TargetPassConfig::addCodeGenPrepare();
684 }
685 
686 bool AArch64PassConfig::addInstSelector() {
687   addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
688 
689   // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
690   // references to _TLS_MODULE_BASE_ as possible.
691   if (TM->getTargetTriple().isOSBinFormatELF() &&
692       getOptLevel() != CodeGenOptLevel::None)
693     addPass(createAArch64CleanupLocalDynamicTLSPass());
694 
695   return false;
696 }
697 
698 bool AArch64PassConfig::addIRTranslator() {
699   addPass(new IRTranslator(getOptLevel()));
700   return false;
701 }
702 
703 void AArch64PassConfig::addPreLegalizeMachineIR() {
704   if (getOptLevel() == CodeGenOptLevel::None) {
705     addPass(createAArch64O0PreLegalizerCombiner());
706     addPass(new Localizer());
707   } else {
708     addPass(createAArch64PreLegalizerCombiner());
709     addPass(new Localizer());
710     if (EnableGISelLoadStoreOptPreLegal)
711       addPass(new LoadStoreOpt());
712   }
713 }
714 
715 bool AArch64PassConfig::addLegalizeMachineIR() {
716   addPass(new Legalizer());
717   return false;
718 }
719 
720 void AArch64PassConfig::addPreRegBankSelect() {
721   bool IsOptNone = getOptLevel() == CodeGenOptLevel::None;
722   if (!IsOptNone) {
723     addPass(createAArch64PostLegalizerCombiner(IsOptNone));
724     if (EnableGISelLoadStoreOptPostLegal)
725       addPass(new LoadStoreOpt());
726   }
727   addPass(createAArch64PostLegalizerLowering());
728 }
729 
730 bool AArch64PassConfig::addRegBankSelect() {
731   addPass(new RegBankSelect());
732   return false;
733 }
734 
735 bool AArch64PassConfig::addGlobalInstructionSelect() {
736   addPass(new InstructionSelect(getOptLevel()));
737   if (getOptLevel() != CodeGenOptLevel::None)
738     addPass(createAArch64PostSelectOptimize());
739   return false;
740 }
741 
742 void AArch64PassConfig::addMachineSSAOptimization() {
743   // Run default MachineSSAOptimization first.
744   TargetPassConfig::addMachineSSAOptimization();
745 
746   if (TM->getOptLevel() != CodeGenOptLevel::None)
747     addPass(createAArch64MIPeepholeOptPass());
748 }
749 
750 bool AArch64PassConfig::addILPOpts() {
751   if (EnableCondOpt)
752     addPass(createAArch64ConditionOptimizerPass());
753   if (EnableCCMP)
754     addPass(createAArch64ConditionalCompares());
755   if (EnableMCR)
756     addPass(&MachineCombinerID);
757   if (EnableCondBrTuning)
758     addPass(createAArch64CondBrTuning());
759   if (EnableEarlyIfConversion)
760     addPass(&EarlyIfConverterID);
761   if (EnableStPairSuppress)
762     addPass(createAArch64StorePairSuppressPass());
763   addPass(createAArch64SIMDInstrOptPass());
764   if (TM->getOptLevel() != CodeGenOptLevel::None)
765     addPass(createAArch64StackTaggingPreRAPass());
766   return true;
767 }
768 
769 void AArch64PassConfig::addPreRegAlloc() {
770   // Change dead register definitions to refer to the zero register.
771   if (TM->getOptLevel() != CodeGenOptLevel::None &&
772       EnableDeadRegisterElimination)
773     addPass(createAArch64DeadRegisterDefinitions());
774 
775   // Use AdvSIMD scalar instructions whenever profitable.
776   if (TM->getOptLevel() != CodeGenOptLevel::None && EnableAdvSIMDScalar) {
777     addPass(createAArch64AdvSIMDScalar());
778     // The AdvSIMD pass may produce copies that can be rewritten to
779     // be register coalescer friendly.
780     addPass(&PeepholeOptimizerID);
781   }
782 }
783 
784 void AArch64PassConfig::addPostRegAlloc() {
785   // Remove redundant copy instructions.
786   if (TM->getOptLevel() != CodeGenOptLevel::None &&
787       EnableRedundantCopyElimination)
788     addPass(createAArch64RedundantCopyEliminationPass());
789 
790   if (TM->getOptLevel() != CodeGenOptLevel::None && usingDefaultRegAlloc())
791     // Improve performance for some FP/SIMD code for A57.
792     addPass(createAArch64A57FPLoadBalancing());
793 }
794 
795 void AArch64PassConfig::addPreSched2() {
796   // Lower homogeneous frame instructions
797   if (EnableHomogeneousPrologEpilog)
798     addPass(createAArch64LowerHomogeneousPrologEpilogPass());
799   // Expand some pseudo instructions to allow proper scheduling.
800   addPass(createAArch64ExpandPseudoPass());
801   // Use load/store pair instructions when possible.
802   if (TM->getOptLevel() != CodeGenOptLevel::None) {
803     if (EnableLoadStoreOpt)
804       addPass(createAArch64LoadStoreOptimizationPass());
805   }
806   // Emit KCFI checks for indirect calls.
807   addPass(createKCFIPass());
808 
809   // The AArch64SpeculationHardeningPass destroys dominator tree and natural
810   // loop info, which is needed for the FalkorHWPFFixPass and also later on.
811   // Therefore, run the AArch64SpeculationHardeningPass before the
812   // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
813   // info.
814   addPass(createAArch64SpeculationHardeningPass());
815 
816   addPass(createAArch64IndirectThunks());
817   addPass(createAArch64SLSHardeningPass());
818 
819   if (TM->getOptLevel() != CodeGenOptLevel::None) {
820     if (EnableFalkorHWPFFix)
821       addPass(createFalkorHWPFFixPass());
822   }
823 }
824 
825 void AArch64PassConfig::addPreEmitPass() {
826   // Machine Block Placement might have created new opportunities when run
827   // at O3, where the Tail Duplication Threshold is set to 4 instructions.
828   // Run the load/store optimizer once more.
829   if (TM->getOptLevel() >= CodeGenOptLevel::Aggressive && EnableLoadStoreOpt)
830     addPass(createAArch64LoadStoreOptimizationPass());
831 
832   if (TM->getOptLevel() >= CodeGenOptLevel::Aggressive &&
833       EnableAArch64CopyPropagation)
834     addPass(createMachineCopyPropagationPass(true));
835 
836   addPass(createAArch64A53Fix835769());
837 
838   if (TM->getTargetTriple().isOSWindows()) {
839     // Identify valid longjmp targets for Windows Control Flow Guard.
840     addPass(createCFGuardLongjmpPass());
841     // Identify valid eh continuation targets for Windows EHCont Guard.
842     addPass(createEHContGuardCatchretPass());
843   }
844 
845   if (TM->getOptLevel() != CodeGenOptLevel::None && EnableCollectLOH &&
846       TM->getTargetTriple().isOSBinFormatMachO())
847     addPass(createAArch64CollectLOHPass());
848 }
849 
850 void AArch64PassConfig::addPostBBSections() {
851   addPass(createAArch64PointerAuthPass());
852   if (EnableBranchTargets)
853     addPass(createAArch64BranchTargetsPass());
854   // Relax conditional branch instructions if they're otherwise out of
855   // range of their destination.
856   if (BranchRelaxation)
857     addPass(&BranchRelaxationPassID);
858 
859   if (TM->getOptLevel() != CodeGenOptLevel::None && EnableCompressJumpTables)
860     addPass(createAArch64CompressJumpTablesPass());
861 }
862 
863 void AArch64PassConfig::addPreEmitPass2() {
864   // SVE bundles move prefixes with destructive operations. BLR_RVMARKER pseudo
865   // instructions are lowered to bundles as well.
866   addPass(createUnpackMachineBundles(nullptr));
867 }
868 
869 MachineFunctionInfo *AArch64TargetMachine::createMachineFunctionInfo(
870     BumpPtrAllocator &Allocator, const Function &F,
871     const TargetSubtargetInfo *STI) const {
872   return AArch64FunctionInfo::create<AArch64FunctionInfo>(
873       Allocator, F, static_cast<const AArch64Subtarget *>(STI));
874 }
875 
876 yaml::MachineFunctionInfo *
877 AArch64TargetMachine::createDefaultFuncInfoYAML() const {
878   return new yaml::AArch64FunctionInfo();
879 }
880 
881 yaml::MachineFunctionInfo *
882 AArch64TargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
883   const auto *MFI = MF.getInfo<AArch64FunctionInfo>();
884   return new yaml::AArch64FunctionInfo(*MFI);
885 }
886 
887 bool AArch64TargetMachine::parseMachineFunctionInfo(
888     const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,
889     SMDiagnostic &Error, SMRange &SourceRange) const {
890   const auto &YamlMFI = static_cast<const yaml::AArch64FunctionInfo &>(MFI);
891   MachineFunction &MF = PFS.MF;
892   MF.getInfo<AArch64FunctionInfo>()->initializeBaseYamlFields(YamlMFI);
893   return false;
894 }
895