xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AArch64Subtarget.h (revision 1323ec571215a77ddd21294f0871979d5ad6b992) 
1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 
16 #include "AArch64FrameLowering.h"
17 #include "AArch64ISelLowering.h"
18 #include "AArch64InstrInfo.h"
19 #include "AArch64RegisterInfo.h"
20 #include "AArch64SelectionDAGInfo.h"
21 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
22 #include "llvm/CodeGen/GlobalISel/InlineAsmLowering.h"
23 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
24 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
25 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
26 #include "llvm/CodeGen/TargetSubtargetInfo.h"
27 #include "llvm/IR/DataLayout.h"
28 #include <string>
29 
30 #define GET_SUBTARGETINFO_HEADER
31 #include "AArch64GenSubtargetInfo.inc"
32 
33 namespace llvm {
34 class GlobalValue;
35 class StringRef;
36 class Triple;
37 
38 class AArch64Subtarget final : public AArch64GenSubtargetInfo {
39 public:
40   enum ARMProcFamilyEnum : uint8_t {
41     Others,
42     A64FX,
43     AppleA7,
44     AppleA10,
45     AppleA11,
46     AppleA12,
47     AppleA13,
48     AppleA14,
49     Carmel,
50     CortexA35,
51     CortexA53,
52     CortexA55,
53     CortexA57,
54     CortexA65,
55     CortexA72,
56     CortexA73,
57     CortexA75,
58     CortexA76,
59     CortexA77,
60     CortexA78,
61     CortexA78C,
62     CortexR82,
63     CortexX1,
64     ExynosM3,
65     Falkor,
66     Kryo,
67     NeoverseE1,
68     NeoverseN1,
69     NeoverseN2,
70     NeoverseV1,
71     Saphira,
72     ThunderX2T99,
73     ThunderX,
74     ThunderXT81,
75     ThunderXT83,
76     ThunderXT88,
77     ThunderX3T110,
78     TSV110
79   };
80 
81 protected:
82   /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
83   ARMProcFamilyEnum ARMProcFamily = Others;
84 
85   bool HasV8_1aOps = false;
86   bool HasV8_2aOps = false;
87   bool HasV8_3aOps = false;
88   bool HasV8_4aOps = false;
89   bool HasV8_5aOps = false;
90   bool HasV8_6aOps = false;
91   bool HasV8_7aOps = false;
92 
93   bool HasV8_0rOps = false;
94   bool HasCONTEXTIDREL2 = false;
95 
96   bool HasFPARMv8 = false;
97   bool HasNEON = false;
98   bool HasCrypto = false;
99   bool HasDotProd = false;
100   bool HasCRC = false;
101   bool HasLSE = false;
102   bool HasRAS = false;
103   bool HasRDM = false;
104   bool HasPerfMon = false;
105   bool HasFullFP16 = false;
106   bool HasFP16FML = false;
107   bool HasSPE = false;
108 
109   // ARMv8.1 extensions
110   bool HasVH = false;
111   bool HasPAN = false;
112   bool HasLOR = false;
113 
114   // ARMv8.2 extensions
115   bool HasPsUAO = false;
116   bool HasPAN_RWV = false;
117   bool HasCCPP = false;
118 
119   // SVE extensions
120   bool HasSVE = false;
121   bool UseExperimentalZeroingPseudos = false;
122 
123   // Armv8.2 Crypto extensions
124   bool HasSM4 = false;
125   bool HasSHA3 = false;
126   bool HasSHA2 = false;
127   bool HasAES = false;
128 
129   // ARMv8.3 extensions
130   bool HasPAuth = false;
131   bool HasJS = false;
132   bool HasCCIDX = false;
133   bool HasComplxNum = false;
134 
135   // ARMv8.4 extensions
136   bool HasNV = false;
137   bool HasMPAM = false;
138   bool HasDIT = false;
139   bool HasTRACEV8_4 = false;
140   bool HasAM = false;
141   bool HasSEL2 = false;
142   bool HasPMU = false;
143   bool HasTLB_RMI = false;
144   bool HasFlagM = false;
145   bool HasRCPC_IMMO = false;
146 
147   bool HasLSLFast = false;
148   bool HasRCPC = false;
149   bool HasAggressiveFMA = false;
150 
151   // Armv8.5-A Extensions
152   bool HasAlternativeNZCV = false;
153   bool HasFRInt3264 = false;
154   bool HasSpecRestrict = false;
155   bool HasSSBS = false;
156   bool HasSB = false;
157   bool HasPredRes = false;
158   bool HasCCDP = false;
159   bool HasBTI = false;
160   bool HasRandGen = false;
161   bool HasMTE = false;
162   bool HasTME = false;
163 
164   // Armv8.6-A Extensions
165   bool HasBF16 = false;
166   bool HasMatMulInt8 = false;
167   bool HasMatMulFP32 = false;
168   bool HasMatMulFP64 = false;
169   bool HasAMVS = false;
170   bool HasFineGrainedTraps = false;
171   bool HasEnhancedCounterVirtualization = false;
172 
173   // Armv8.7-A Extensions
174   bool HasXS = false;
175   bool HasWFxT = false;
176   bool HasHCX = false;
177   bool HasLS64 = false;
178 
179   // Arm SVE2 extensions
180   bool HasSVE2 = false;
181   bool HasSVE2AES = false;
182   bool HasSVE2SM4 = false;
183   bool HasSVE2SHA3 = false;
184   bool HasSVE2BitPerm = false;
185 
186   // Armv9-A Extensions
187   bool HasRME = false;
188 
189   // Arm Scalable Matrix Extension (SME)
190   bool HasSME = false;
191   bool HasSMEF64 = false;
192   bool HasSMEI64 = false;
193 
194   // Future architecture extensions.
195   bool HasETE = false;
196   bool HasTRBE = false;
197   bool HasBRBE = false;
198   bool HasPAUTH = false;
199   bool HasSPE_EEF = false;
200 
201   // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
202   bool HasZeroCycleRegMove = false;
203 
204   // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
205   bool HasZeroCycleZeroing = false;
206   bool HasZeroCycleZeroingGP = false;
207   bool HasZeroCycleZeroingFPWorkaround = false;
208 
209   // It is generally beneficial to rewrite "fmov s0, wzr" to "movi d0, #0".
210   // as movi is more efficient across all cores. Newer cores can eliminate
211   // fmovs early and there is no difference with movi, but this not true for
212   // all implementations.
213   bool HasZeroCycleZeroingFP = true;
214 
215   // StrictAlign - Disallow unaligned memory accesses.
216   bool StrictAlign = false;
217 
218   // NegativeImmediates - transform instructions with negative immediates
219   bool NegativeImmediates = true;
220 
221   // Enable 64-bit vectorization in SLP.
222   unsigned MinVectorRegisterBitWidth = 64;
223 
224   bool OutlineAtomics = false;
225   bool PredictableSelectIsExpensive = false;
226   bool BalanceFPOps = false;
227   bool CustomAsCheapAsMove = false;
228   bool ExynosAsCheapAsMove = false;
229   bool UsePostRAScheduler = false;
230   bool Misaligned128StoreIsSlow = false;
231   bool Paired128IsSlow = false;
232   bool STRQroIsSlow = false;
233   bool UseAlternateSExtLoadCVTF32Pattern = false;
234   bool HasArithmeticBccFusion = false;
235   bool HasArithmeticCbzFusion = false;
236   bool HasCmpBccFusion = false;
237   bool HasFuseAddress = false;
238   bool HasFuseAES = false;
239   bool HasFuseArithmeticLogic = false;
240   bool HasFuseCCSelect = false;
241   bool HasFuseCryptoEOR = false;
242   bool HasFuseLiterals = false;
243   bool DisableLatencySchedHeuristic = false;
244   bool UseRSqrt = false;
245   bool Force32BitJumpTables = false;
246   bool UseEL1ForTP = false;
247   bool UseEL2ForTP = false;
248   bool UseEL3ForTP = false;
249   bool AllowTaggedGlobals = false;
250   bool HardenSlsRetBr = false;
251   bool HardenSlsBlr = false;
252   bool HardenSlsNoComdat = false;
253   uint8_t MaxInterleaveFactor = 2;
254   uint8_t VectorInsertExtractBaseCost = 3;
255   uint16_t CacheLineSize = 0;
256   uint16_t PrefetchDistance = 0;
257   uint16_t MinPrefetchStride = 1;
258   unsigned MaxPrefetchIterationsAhead = UINT_MAX;
259   unsigned PrefFunctionLogAlignment = 0;
260   unsigned PrefLoopLogAlignment = 0;
261   unsigned MaxJumpTableSize = 0;
262   unsigned WideningBaseCost = 0;
263 
264   // ReserveXRegister[i] - X#i is not available as a general purpose register.
265   BitVector ReserveXRegister;
266 
267   // CustomCallUsedXRegister[i] - X#i call saved.
268   BitVector CustomCallSavedXRegs;
269 
270   bool IsLittle;
271 
272   unsigned MinSVEVectorSizeInBits;
273   unsigned MaxSVEVectorSizeInBits;
274 
275   /// TargetTriple - What processor and OS we're targeting.
276   Triple TargetTriple;
277 
278   AArch64FrameLowering FrameLowering;
279   AArch64InstrInfo InstrInfo;
280   AArch64SelectionDAGInfo TSInfo;
281   AArch64TargetLowering TLInfo;
282 
283   /// GlobalISel related APIs.
284   std::unique_ptr<CallLowering> CallLoweringInfo;
285   std::unique_ptr<InlineAsmLowering> InlineAsmLoweringInfo;
286   std::unique_ptr<InstructionSelector> InstSelector;
287   std::unique_ptr<LegalizerInfo> Legalizer;
288   std::unique_ptr<RegisterBankInfo> RegBankInfo;
289 
290 private:
291   /// initializeSubtargetDependencies - Initializes using CPUString and the
292   /// passed in feature string so that we can use initializer lists for
293   /// subtarget initialization.
294   AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
295                                                     StringRef CPUString);
296 
297   /// Initialize properties based on the selected processor family.
298   void initializeProperties();
299 
300 public:
301   /// This constructor initializes the data members to match that
302   /// of the specified triple.
303   AArch64Subtarget(const Triple &TT, const std::string &CPU,
304                    const std::string &FS, const TargetMachine &TM,
305                    bool LittleEndian,
306                    unsigned MinSVEVectorSizeInBitsOverride = 0,
307                    unsigned MaxSVEVectorSizeInBitsOverride = 0);
308 
309   const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
310     return &TSInfo;
311   }
312   const AArch64FrameLowering *getFrameLowering() const override {
313     return &FrameLowering;
314   }
315   const AArch64TargetLowering *getTargetLowering() const override {
316     return &TLInfo;
317   }
318   const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
319   const AArch64RegisterInfo *getRegisterInfo() const override {
320     return &getInstrInfo()->getRegisterInfo();
321   }
322   const CallLowering *getCallLowering() const override;
323   const InlineAsmLowering *getInlineAsmLowering() const override;
324   InstructionSelector *getInstructionSelector() const override;
325   const LegalizerInfo *getLegalizerInfo() const override;
326   const RegisterBankInfo *getRegBankInfo() const override;
327   const Triple &getTargetTriple() const { return TargetTriple; }
328   bool enableMachineScheduler() const override { return true; }
329   bool enablePostRAScheduler() const override {
330     return UsePostRAScheduler;
331   }
332 
333   /// Returns ARM processor family.
334   /// Avoid this function! CPU specifics should be kept local to this class
335   /// and preferably modeled with SubtargetFeatures or properties in
336   /// initializeProperties().
337   ARMProcFamilyEnum getProcFamily() const {
338     return ARMProcFamily;
339   }
340 
341   bool hasV8_1aOps() const { return HasV8_1aOps; }
342   bool hasV8_2aOps() const { return HasV8_2aOps; }
343   bool hasV8_3aOps() const { return HasV8_3aOps; }
344   bool hasV8_4aOps() const { return HasV8_4aOps; }
345   bool hasV8_5aOps() const { return HasV8_5aOps; }
346   bool hasV8_0rOps() const { return HasV8_0rOps; }
347 
348   bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
349 
350   bool hasZeroCycleZeroingGP() const { return HasZeroCycleZeroingGP; }
351 
352   bool hasZeroCycleZeroingFP() const { return HasZeroCycleZeroingFP; }
353 
354   bool hasZeroCycleZeroingFPWorkaround() const {
355     return HasZeroCycleZeroingFPWorkaround;
356   }
357 
358   bool requiresStrictAlign() const { return StrictAlign; }
359 
360   bool isXRaySupported() const override { return true; }
361 
362   unsigned getMinVectorRegisterBitWidth() const {
363     return MinVectorRegisterBitWidth;
364   }
365 
366   bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
367   unsigned getNumXRegisterReserved() const { return ReserveXRegister.count(); }
368   bool isXRegCustomCalleeSaved(size_t i) const {
369     return CustomCallSavedXRegs[i];
370   }
371   bool hasCustomCallingConv() const { return CustomCallSavedXRegs.any(); }
372   bool hasFPARMv8() const { return HasFPARMv8; }
373   bool hasNEON() const { return HasNEON; }
374   bool hasCrypto() const { return HasCrypto; }
375   bool hasDotProd() const { return HasDotProd; }
376   bool hasCRC() const { return HasCRC; }
377   bool hasLSE() const { return HasLSE; }
378   bool hasRAS() const { return HasRAS; }
379   bool hasRDM() const { return HasRDM; }
380   bool hasSM4() const { return HasSM4; }
381   bool hasSHA3() const { return HasSHA3; }
382   bool hasSHA2() const { return HasSHA2; }
383   bool hasAES() const { return HasAES; }
384   bool hasCONTEXTIDREL2() const { return HasCONTEXTIDREL2; }
385   bool balanceFPOps() const { return BalanceFPOps; }
386   bool predictableSelectIsExpensive() const {
387     return PredictableSelectIsExpensive;
388   }
389   bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; }
390   bool hasExynosCheapAsMoveHandling() const { return ExynosAsCheapAsMove; }
391   bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; }
392   bool isPaired128Slow() const { return Paired128IsSlow; }
393   bool isSTRQroSlow() const { return STRQroIsSlow; }
394   bool useAlternateSExtLoadCVTF32Pattern() const {
395     return UseAlternateSExtLoadCVTF32Pattern;
396   }
397   bool hasArithmeticBccFusion() const { return HasArithmeticBccFusion; }
398   bool hasArithmeticCbzFusion() const { return HasArithmeticCbzFusion; }
399   bool hasCmpBccFusion() const { return HasCmpBccFusion; }
400   bool hasFuseAddress() const { return HasFuseAddress; }
401   bool hasFuseAES() const { return HasFuseAES; }
402   bool hasFuseArithmeticLogic() const { return HasFuseArithmeticLogic; }
403   bool hasFuseCCSelect() const { return HasFuseCCSelect; }
404   bool hasFuseCryptoEOR() const { return HasFuseCryptoEOR; }
405   bool hasFuseLiterals() const { return HasFuseLiterals; }
406 
407   /// Return true if the CPU supports any kind of instruction fusion.
408   bool hasFusion() const {
409     return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
410            hasFuseAES() || hasFuseArithmeticLogic() ||
411            hasFuseCCSelect() || hasFuseLiterals();
412   }
413 
414   bool hardenSlsRetBr() const { return HardenSlsRetBr; }
415   bool hardenSlsBlr() const { return HardenSlsBlr; }
416   bool hardenSlsNoComdat() const { return HardenSlsNoComdat; }
417 
418   bool useEL1ForTP() const { return UseEL1ForTP; }
419   bool useEL2ForTP() const { return UseEL2ForTP; }
420   bool useEL3ForTP() const { return UseEL3ForTP; }
421 
422   bool useRSqrt() const { return UseRSqrt; }
423   bool force32BitJumpTables() const { return Force32BitJumpTables; }
424   unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
425   unsigned getVectorInsertExtractBaseCost() const {
426     return VectorInsertExtractBaseCost;
427   }
428   unsigned getCacheLineSize() const override { return CacheLineSize; }
429   unsigned getPrefetchDistance() const override { return PrefetchDistance; }
430   unsigned getMinPrefetchStride(unsigned NumMemAccesses,
431                                 unsigned NumStridedMemAccesses,
432                                 unsigned NumPrefetches,
433                                 bool HasCall) const override {
434     return MinPrefetchStride;
435   }
436   unsigned getMaxPrefetchIterationsAhead() const override {
437     return MaxPrefetchIterationsAhead;
438   }
439   unsigned getPrefFunctionLogAlignment() const {
440     return PrefFunctionLogAlignment;
441   }
442   unsigned getPrefLoopLogAlignment() const { return PrefLoopLogAlignment; }
443 
444   unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
445 
446   unsigned getWideningBaseCost() const { return WideningBaseCost; }
447 
448   bool useExperimentalZeroingPseudos() const {
449     return UseExperimentalZeroingPseudos;
450   }
451 
452   /// CPU has TBI (top byte of addresses is ignored during HW address
453   /// translation) and OS enables it.
454   bool supportsAddressTopByteIgnored() const;
455 
456   bool hasPerfMon() const { return HasPerfMon; }
457   bool hasFullFP16() const { return HasFullFP16; }
458   bool hasFP16FML() const { return HasFP16FML; }
459   bool hasSPE() const { return HasSPE; }
460   bool hasLSLFast() const { return HasLSLFast; }
461   bool hasSVE() const { return HasSVE; }
462   bool hasSVE2() const { return HasSVE2; }
463   bool hasRCPC() const { return HasRCPC; }
464   bool hasAggressiveFMA() const { return HasAggressiveFMA; }
465   bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
466   bool hasFRInt3264() const { return HasFRInt3264; }
467   bool hasSpecRestrict() const { return HasSpecRestrict; }
468   bool hasSSBS() const { return HasSSBS; }
469   bool hasSB() const { return HasSB; }
470   bool hasPredRes() const { return HasPredRes; }
471   bool hasCCDP() const { return HasCCDP; }
472   bool hasBTI() const { return HasBTI; }
473   bool hasRandGen() const { return HasRandGen; }
474   bool hasMTE() const { return HasMTE; }
475   bool hasTME() const { return HasTME; }
476   bool hasPAUTH() const { return HasPAUTH; }
477   // Arm SVE2 extensions
478   bool hasSVE2AES() const { return HasSVE2AES; }
479   bool hasSVE2SM4() const { return HasSVE2SM4; }
480   bool hasSVE2SHA3() const { return HasSVE2SHA3; }
481   bool hasSVE2BitPerm() const { return HasSVE2BitPerm; }
482   bool hasMatMulInt8() const { return HasMatMulInt8; }
483   bool hasMatMulFP32() const { return HasMatMulFP32; }
484   bool hasMatMulFP64() const { return HasMatMulFP64; }
485 
486   // Armv8.6-A Extensions
487   bool hasBF16() const { return HasBF16; }
488   bool hasFineGrainedTraps() const { return HasFineGrainedTraps; }
489   bool hasEnhancedCounterVirtualization() const {
490     return HasEnhancedCounterVirtualization;
491   }
492 
493   // Arm Scalable Matrix Extension (SME)
494   bool hasSME() const { return HasSME; }
495   bool hasSMEF64() const { return HasSMEF64; }
496   bool hasSMEI64() const { return HasSMEI64; }
497 
498   bool isLittleEndian() const { return IsLittle; }
499 
500   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
501   bool isTargetIOS() const { return TargetTriple.isiOS(); }
502   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
503   bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
504   bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
505   bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
506 
507   bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
508   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
509   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
510 
511   bool isTargetILP32() const {
512     return TargetTriple.isArch32Bit() ||
513            TargetTriple.getEnvironment() == Triple::GNUILP32;
514   }
515 
516   bool useAA() const override;
517 
518   bool outlineAtomics() const { return OutlineAtomics; }
519 
520   bool hasVH() const { return HasVH; }
521   bool hasPAN() const { return HasPAN; }
522   bool hasLOR() const { return HasLOR; }
523 
524   bool hasPsUAO() const { return HasPsUAO; }
525   bool hasPAN_RWV() const { return HasPAN_RWV; }
526   bool hasCCPP() const { return HasCCPP; }
527 
528   bool hasPAuth() const { return HasPAuth; }
529   bool hasJS() const { return HasJS; }
530   bool hasCCIDX() const { return HasCCIDX; }
531   bool hasComplxNum() const { return HasComplxNum; }
532 
533   bool hasNV() const { return HasNV; }
534   bool hasMPAM() const { return HasMPAM; }
535   bool hasDIT() const { return HasDIT; }
536   bool hasTRACEV8_4() const { return HasTRACEV8_4; }
537   bool hasAM() const { return HasAM; }
538   bool hasAMVS() const { return HasAMVS; }
539   bool hasXS() const { return HasXS; }
540   bool hasWFxT() const { return HasWFxT; }
541   bool hasHCX() const { return HasHCX; }
542   bool hasLS64() const { return HasLS64; }
543   bool hasSEL2() const { return HasSEL2; }
544   bool hasPMU() const { return HasPMU; }
545   bool hasTLB_RMI() const { return HasTLB_RMI; }
546   bool hasFlagM() const { return HasFlagM; }
547   bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
548 
549   bool addrSinkUsingGEPs() const override {
550     // Keeping GEPs inbounds is important for exploiting AArch64
551     // addressing-modes in ILP32 mode.
552     return useAA() || isTargetILP32();
553   }
554 
555   bool useSmallAddressing() const {
556     switch (TLInfo.getTargetMachine().getCodeModel()) {
557       case CodeModel::Kernel:
558         // Kernel is currently allowed only for Fuchsia targets,
559         // where it is the same as Small for almost all purposes.
560       case CodeModel::Small:
561         return true;
562       default:
563         return false;
564     }
565   }
566 
567   /// ParseSubtargetFeatures - Parses features string setting specified
568   /// subtarget options.  Definition of function is auto generated by tblgen.
569   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
570 
571   /// ClassifyGlobalReference - Find the target operand flags that describe
572   /// how a global value should be referenced for the current subtarget.
573   unsigned ClassifyGlobalReference(const GlobalValue *GV,
574                                    const TargetMachine &TM) const;
575 
576   unsigned classifyGlobalFunctionReference(const GlobalValue *GV,
577                                            const TargetMachine &TM) const;
578 
579   void overrideSchedPolicy(MachineSchedPolicy &Policy,
580                            unsigned NumRegionInstrs) const override;
581 
582   bool enableEarlyIfConversion() const override;
583 
584   bool enableAdvancedRASplitCost() const override { return false; }
585 
586   std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
587 
588   bool isCallingConvWin64(CallingConv::ID CC) const {
589     switch (CC) {
590     case CallingConv::C:
591     case CallingConv::Fast:
592     case CallingConv::Swift:
593       return isTargetWindows();
594     case CallingConv::Win64:
595       return true;
596     default:
597       return false;
598     }
599   }
600 
601   void mirFileLoaded(MachineFunction &MF) const override;
602 
603   // Return the known range for the bit length of SVE data registers. A value
604   // of 0 means nothing is known about that particular limit beyong what's
605   // implied by the architecture.
606   unsigned getMaxSVEVectorSizeInBits() const {
607     assert(HasSVE && "Tried to get SVE vector length without SVE support!");
608     return MaxSVEVectorSizeInBits;
609   }
610 
611   unsigned getMinSVEVectorSizeInBits() const {
612     assert(HasSVE && "Tried to get SVE vector length without SVE support!");
613     return MinSVEVectorSizeInBits;
614   }
615 
616   bool useSVEForFixedLengthVectors() const;
617 };
618 } // End llvm namespace
619 
620 #endif
621