xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AArch64SchedThunderX.td (revision d30a1689f5b37e78ea189232a8b94a7011dc0dc8) 
1//==- AArch64SchedThunderX.td - Cavium ThunderX T8X Scheduling Definitions -*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the itinerary class data for the ARM ThunderX T8X
10// (T88, T81, T83) processors.
11// Loosely based on Cortex-A53 which is somewhat similar.
12//
13//===----------------------------------------------------------------------===//
14
15// ===---------------------------------------------------------------------===//
16// The following definitions describe the simpler per-operand machine model.
17// This works with MachineScheduler. See llvm/MC/MCSchedule.h for details.
18
19// Cavium ThunderX T8X scheduling machine model.
20def ThunderXT8XModel : SchedMachineModel {
21  let IssueWidth = 2;         // 2 micro-ops dispatched per cycle.
22  let MicroOpBufferSize = 0;  // ThunderX T88/T81/T83 are in-order.
23  let LoadLatency = 3;        // Optimistic load latency.
24  let MispredictPenalty = 8;  // Branch mispredict penalty.
25  let PostRAScheduler = 1;    // Use PostRA scheduler.
26  let CompleteModel = 1;
27
28  list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
29                                                    PAUnsupported.F,
30                                                    SMEUnsupported.F);
31  // FIXME: Remove when all errors have been fixed.
32  let FullInstRWOverlapCheck = 0;
33}
34
35// Modeling each pipeline with BufferSize == 0 since T8X is in-order.
36def THXT8XUnitALU    : ProcResource<2> { let BufferSize = 0; } // Int ALU
37def THXT8XUnitMAC    : ProcResource<1> { let BufferSize = 0; } // Int MAC
38def THXT8XUnitDiv    : ProcResource<1> { let BufferSize = 0; } // Int Division
39def THXT8XUnitLdSt   : ProcResource<1> { let BufferSize = 0; } // Load/Store
40def THXT8XUnitBr     : ProcResource<1> { let BufferSize = 0; } // Branch
41def THXT8XUnitFPALU  : ProcResource<1> { let BufferSize = 0; } // FP ALU
42def THXT8XUnitFPMDS  : ProcResource<1> { let BufferSize = 0; } // FP Mul/Div/Sqrt
43
44//===----------------------------------------------------------------------===//
45// Subtarget-specific SchedWrite types mapping the ProcResources and
46// latencies.
47
48let SchedModel = ThunderXT8XModel in {
49
50// ALU
51def : WriteRes<WriteImm, [THXT8XUnitALU]> { let Latency = 1; }
52def : WriteRes<WriteI, [THXT8XUnitALU]> { let Latency = 1; }
53def : WriteRes<WriteISReg, [THXT8XUnitALU]> { let Latency = 2; }
54def : WriteRes<WriteIEReg, [THXT8XUnitALU]> { let Latency = 2; }
55def : WriteRes<WriteIS, [THXT8XUnitALU]> { let Latency = 2; }
56def : WriteRes<WriteExtr, [THXT8XUnitALU]> { let Latency = 2; }
57
58// MAC
59def : WriteRes<WriteIM32, [THXT8XUnitMAC]> {
60  let Latency = 4;
61  let ResourceCycles = [1];
62}
63
64def : WriteRes<WriteIM64, [THXT8XUnitMAC]> {
65  let Latency = 4;
66  let ResourceCycles = [1];
67}
68
69// Div
70def : WriteRes<WriteID32, [THXT8XUnitDiv]> {
71  let Latency = 12;
72  let ResourceCycles = [6];
73}
74
75def : WriteRes<WriteID64, [THXT8XUnitDiv]> {
76  let Latency = 14;
77  let ResourceCycles = [8];
78}
79
80// Load
81def : WriteRes<WriteLD, [THXT8XUnitLdSt]> { let Latency = 3; }
82def : WriteRes<WriteLDIdx, [THXT8XUnitLdSt]> { let Latency = 3; }
83def : WriteRes<WriteLDHi, [THXT8XUnitLdSt]> { let Latency = 3; }
84
85// Vector Load
86def : WriteRes<WriteVLD, [THXT8XUnitLdSt]> {
87  let Latency = 8;
88  let ResourceCycles = [3];
89}
90
91def THXT8XWriteVLD1 : SchedWriteRes<[THXT8XUnitLdSt]> {
92  let Latency = 6;
93  let ResourceCycles = [1];
94}
95
96def THXT8XWriteVLD2 : SchedWriteRes<[THXT8XUnitLdSt]> {
97  let Latency = 11;
98  let ResourceCycles = [7];
99}
100
101def THXT8XWriteVLD3 : SchedWriteRes<[THXT8XUnitLdSt]> {
102  let Latency = 12;
103  let ResourceCycles = [8];
104}
105
106def THXT8XWriteVLD4 : SchedWriteRes<[THXT8XUnitLdSt]> {
107  let Latency = 13;
108  let ResourceCycles = [9];
109}
110
111def THXT8XWriteVLD5 : SchedWriteRes<[THXT8XUnitLdSt]> {
112  let Latency = 13;
113  let ResourceCycles = [9];
114}
115
116// Pre/Post Indexing
117def : WriteRes<WriteAdr, []> { let Latency = 0; }
118
119// Store
120def : WriteRes<WriteST, [THXT8XUnitLdSt]> { let Latency = 1; }
121def : WriteRes<WriteSTP, [THXT8XUnitLdSt]> { let Latency = 1; }
122def : WriteRes<WriteSTIdx, [THXT8XUnitLdSt]> { let Latency = 1; }
123def : WriteRes<WriteSTX, [THXT8XUnitLdSt]> { let Latency = 1; }
124
125// Vector Store
126def : WriteRes<WriteVST, [THXT8XUnitLdSt]>;
127def THXT8XWriteVST1 : SchedWriteRes<[THXT8XUnitLdSt]>;
128
129def THXT8XWriteVST2 : SchedWriteRes<[THXT8XUnitLdSt]> {
130  let Latency = 10;
131  let ResourceCycles = [9];
132}
133
134def THXT8XWriteVST3 : SchedWriteRes<[THXT8XUnitLdSt]> {
135  let Latency = 11;
136  let ResourceCycles = [10];
137}
138
139def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
140
141// Branch
142def : WriteRes<WriteBr, [THXT8XUnitBr]>;
143def THXT8XWriteBR : SchedWriteRes<[THXT8XUnitBr]>;
144def : WriteRes<WriteBrReg, [THXT8XUnitBr]>;
145def THXT8XWriteBRR : SchedWriteRes<[THXT8XUnitBr]>;
146def THXT8XWriteRET : SchedWriteRes<[THXT8XUnitALU]>;
147def : WriteRes<WriteSys, [THXT8XUnitBr]>;
148def : WriteRes<WriteBarrier, [THXT8XUnitBr]>;
149def : WriteRes<WriteHint, [THXT8XUnitBr]>;
150
151// FP ALU
152def : WriteRes<WriteF, [THXT8XUnitFPALU]> { let Latency = 6; }
153def : WriteRes<WriteFCmp, [THXT8XUnitFPALU]> { let Latency = 6; }
154def : WriteRes<WriteFCvt, [THXT8XUnitFPALU]> { let Latency = 6; }
155def : WriteRes<WriteFCopy, [THXT8XUnitFPALU]> { let Latency = 6; }
156def : WriteRes<WriteFImm, [THXT8XUnitFPALU]> { let Latency = 6; }
157def : WriteRes<WriteVd, [THXT8XUnitFPALU]> { let Latency = 6; }
158def : WriteRes<WriteVq, [THXT8XUnitFPALU]> { let Latency = 6; }
159
160// FP Mul, Div, Sqrt
161def : WriteRes<WriteFMul, [THXT8XUnitFPMDS]> { let Latency = 6; }
162def : WriteRes<WriteFDiv, [THXT8XUnitFPMDS]> {
163  let Latency = 22;
164  let ResourceCycles = [19];
165}
166
167def THXT8XWriteFMAC : SchedWriteRes<[THXT8XUnitFPMDS]> { let Latency = 10; }
168
169def THXT8XWriteFDivSP : SchedWriteRes<[THXT8XUnitFPMDS]> {
170  let Latency = 12;
171  let ResourceCycles = [9];
172}
173
174def THXT8XWriteFDivDP : SchedWriteRes<[THXT8XUnitFPMDS]> {
175  let Latency = 22;
176  let ResourceCycles = [19];
177}
178
179def THXT8XWriteFSqrtSP : SchedWriteRes<[THXT8XUnitFPMDS]> {
180  let Latency = 17;
181  let ResourceCycles = [14];
182}
183
184def THXT8XWriteFSqrtDP : SchedWriteRes<[THXT8XUnitFPMDS]> {
185  let Latency = 31;
186  let ResourceCycles = [28];
187}
188
189//===----------------------------------------------------------------------===//
190// Subtarget-specific SchedRead types.
191
192// No forwarding for these reads.
193def : ReadAdvance<ReadExtrHi, 1>;
194def : ReadAdvance<ReadAdrBase, 2>;
195def : ReadAdvance<ReadVLD, 2>;
196def : ReadAdvance<ReadST, 2>;
197
198// FIXME: This needs more targeted benchmarking.
199// ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable
200//       operands are needed one cycle later if and only if they are to be
201//       shifted. Otherwise, they too are needed two cycles later. This same
202//       ReadAdvance applies to Extended registers as well, even though there is
203//       a separate SchedPredicate for them.
204def : ReadAdvance<ReadI, 2, [WriteImm, WriteI,
205                             WriteISReg, WriteIEReg, WriteIS,
206                             WriteID32, WriteID64,
207                             WriteIM32, WriteIM64]>;
208def THXT8XReadShifted : SchedReadAdvance<1, [WriteImm, WriteI,
209                                          WriteISReg, WriteIEReg, WriteIS,
210                                          WriteID32, WriteID64,
211                                          WriteIM32, WriteIM64]>;
212def THXT8XReadNotShifted : SchedReadAdvance<2, [WriteImm, WriteI,
213                                             WriteISReg, WriteIEReg, WriteIS,
214                                             WriteID32, WriteID64,
215                                             WriteIM32, WriteIM64]>;
216def THXT8XReadISReg : SchedReadVariant<[
217	SchedVar<RegShiftedPred, [THXT8XReadShifted]>,
218	SchedVar<NoSchedPred, [THXT8XReadNotShifted]>]>;
219def : SchedAlias<ReadISReg, THXT8XReadISReg>;
220
221def THXT8XReadIEReg : SchedReadVariant<[
222	SchedVar<RegExtendedPred, [THXT8XReadShifted]>,
223	SchedVar<NoSchedPred, [THXT8XReadNotShifted]>]>;
224def : SchedAlias<ReadIEReg, THXT8XReadIEReg>;
225
226// MAC - Operands are generally needed one cycle later in the MAC pipe.
227//       Accumulator operands are needed two cycles later.
228def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
229                              WriteISReg, WriteIEReg, WriteIS,
230                              WriteID32, WriteID64,
231                              WriteIM32, WriteIM64]>;
232def : ReadAdvance<ReadIMA, 2, [WriteImm, WriteI,
233                               WriteISReg, WriteIEReg, WriteIS,
234                               WriteID32, WriteID64,
235                               WriteIM32, WriteIM64]>;
236
237// Div
238def : ReadAdvance<ReadID, 1, [WriteImm, WriteI,
239                              WriteISReg, WriteIEReg, WriteIS,
240                              WriteID32, WriteID64,
241                              WriteIM32, WriteIM64]>;
242
243//===----------------------------------------------------------------------===//
244// Subtarget-specific InstRW.
245
246//---
247// Branch
248//---
249def : InstRW<[THXT8XWriteBR], (instregex "^B$")>;
250def : InstRW<[THXT8XWriteBR], (instregex "^BL$")>;
251def : InstRW<[THXT8XWriteBR], (instregex "^B..$")>;
252def : InstRW<[THXT8XWriteBR], (instregex "^CBNZ")>;
253def : InstRW<[THXT8XWriteBR], (instregex "^CBZ")>;
254def : InstRW<[THXT8XWriteBR], (instregex "^TBNZ")>;
255def : InstRW<[THXT8XWriteBR], (instregex "^TBZ")>;
256def : InstRW<[THXT8XWriteBRR], (instregex "^BR$")>;
257def : InstRW<[THXT8XWriteBRR], (instregex "^BLR$")>;
258
259//---
260// Ret
261//---
262def : InstRW<[THXT8XWriteRET], (instregex "^RET$")>;
263
264//---
265// Miscellaneous
266//---
267def : InstRW<[WriteI], (instrs COPY)>;
268
269//---
270// Vector Loads
271//---
272def : InstRW<[THXT8XWriteVLD1], (instregex "LD1i(8|16|32|64)$")>;
273def : InstRW<[THXT8XWriteVLD1], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
274def : InstRW<[THXT8XWriteVLD1], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
275def : InstRW<[THXT8XWriteVLD2], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
276def : InstRW<[THXT8XWriteVLD3], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
277def : InstRW<[THXT8XWriteVLD4], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
278def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>;
279def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
280def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
281def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
282def : InstRW<[THXT8XWriteVLD3, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
283def : InstRW<[THXT8XWriteVLD4, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
284
285def : InstRW<[THXT8XWriteVLD1], (instregex "LD2i(8|16|32|64)$")>;
286def : InstRW<[THXT8XWriteVLD1], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
287def : InstRW<[THXT8XWriteVLD2], (instregex "LD2Twov(8b|4h|2s)$")>;
288def : InstRW<[THXT8XWriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
289def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD2i(8|16|32|64)(_POST)?$")>;
290def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
291def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD2Twov(8b|4h|2s)(_POST)?$")>;
292def : InstRW<[THXT8XWriteVLD4, WriteAdr], (instregex "LD2Twov(16b|8h|4s|2d)(_POST)?$")>;
293
294def : InstRW<[THXT8XWriteVLD2], (instregex "LD3i(8|16|32|64)$")>;
295def : InstRW<[THXT8XWriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
296def : InstRW<[THXT8XWriteVLD4], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)$")>;
297def : InstRW<[THXT8XWriteVLD3], (instregex "LD3Threev(2d)$")>;
298def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD3i(8|16|32|64)_POST$")>;
299def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
300def : InstRW<[THXT8XWriteVLD4, WriteAdr], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
301def : InstRW<[THXT8XWriteVLD3, WriteAdr], (instregex "LD3Threev(2d)_POST$")>;
302
303def : InstRW<[THXT8XWriteVLD2], (instregex "LD4i(8|16|32|64)$")>;
304def : InstRW<[THXT8XWriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
305def : InstRW<[THXT8XWriteVLD5], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>;
306def : InstRW<[THXT8XWriteVLD4], (instregex "LD4Fourv(2d)$")>;
307def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD4i(8|16|32|64)_POST$")>;
308def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
309def : InstRW<[THXT8XWriteVLD5, WriteAdr], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
310def : InstRW<[THXT8XWriteVLD4, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>;
311
312//---
313// Vector Stores
314//---
315def : InstRW<[THXT8XWriteVST1], (instregex "ST1i(8|16|32|64)$")>;
316def : InstRW<[THXT8XWriteVST1], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
317def : InstRW<[THXT8XWriteVST1], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
318def : InstRW<[THXT8XWriteVST2], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
319def : InstRW<[THXT8XWriteVST2], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
320def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST1i(8|16|32|64)_POST$")>;
321def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
322def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
323def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
324def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
325
326def : InstRW<[THXT8XWriteVST1], (instregex "ST2i(8|16|32|64)$")>;
327def : InstRW<[THXT8XWriteVST1], (instregex "ST2Twov(8b|4h|2s)$")>;
328def : InstRW<[THXT8XWriteVST2], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
329def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST2i(8|16|32|64)_POST$")>;
330def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
331def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
332
333def : InstRW<[THXT8XWriteVST2], (instregex "ST3i(8|16|32|64)$")>;
334def : InstRW<[THXT8XWriteVST3], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)$")>;
335def : InstRW<[THXT8XWriteVST2], (instregex "ST3Threev(2d)$")>;
336def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST3i(8|16|32|64)_POST$")>;
337def : InstRW<[THXT8XWriteVST3, WriteAdr], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
338def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST3Threev(2d)_POST$")>;
339
340def : InstRW<[THXT8XWriteVST2], (instregex "ST4i(8|16|32|64)$")>;
341def : InstRW<[THXT8XWriteVST3], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>;
342def : InstRW<[THXT8XWriteVST2], (instregex "ST4Fourv(2d)$")>;
343def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST4i(8|16|32|64)_POST$")>;
344def : InstRW<[THXT8XWriteVST3, WriteAdr], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
345def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>;
346
347//---
348// Floating Point MAC, DIV, SQRT
349//---
350def : InstRW<[THXT8XWriteFMAC], (instregex "^FN?M(ADD|SUB).*")>;
351def : InstRW<[THXT8XWriteFMAC], (instregex "^FML(A|S).*")>;
352def : InstRW<[THXT8XWriteFDivSP], (instrs FDIVSrr)>;
353def : InstRW<[THXT8XWriteFDivDP], (instrs FDIVDrr)>;
354def : InstRW<[THXT8XWriteFDivSP], (instregex "^FDIVv.*32$")>;
355def : InstRW<[THXT8XWriteFDivDP], (instregex "^FDIVv.*64$")>;
356def : InstRW<[THXT8XWriteFSqrtSP], (instregex "^.*SQRT.*32$")>;
357def : InstRW<[THXT8XWriteFSqrtDP], (instregex "^.*SQRT.*64$")>;
358
359}
360