xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AArch64SchedTSV110.td (revision e6bfd18d21b225af6a0ed67ceeaf1293b7b9eba5)
1//==- AArch64SchedTSV110.td - Huawei TSV110 Scheduling Definitions -*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the machine model for Huawei TSV110 to support
10// instruction scheduling and other instruction cost heuristics.
11//
12//===----------------------------------------------------------------------===//
13
14// ===---------------------------------------------------------------------===//
15// The following definitions describe the simpler per-operand machine model.
16// This works with MachineScheduler. See llvm/MC/MCSchedule.h for details.
17
18// Huawei TSV110 scheduling machine model.
19def TSV110Model : SchedMachineModel {
20  let IssueWidth            =   4; // 4 micro-ops dispatched  per cycle.
21  let MicroOpBufferSize     = 128; // 128 micro-op re-order buffer
22  let LoopMicroOpBufferSize =  16;
23  let LoadLatency           =   4; // Optimistic load latency.
24  let MispredictPenalty     =  14; // Fetch + Decode/Rename/Dispatch + Branch
25  let CompleteModel         =   1;
26
27  list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
28                                                    PAUnsupported.F,
29                                                    SMEUnsupported.F,
30                                                    [HasMTE]);
31}
32
33// Define each kind of processor resource and number available on the TSV110,
34// which has 8 pipelines, each with its own queue where micro-ops wait for
35// their operands and issue out-of-order to one of eight execution pipelines.
36let SchedModel = TSV110Model in {
37  def TSV110UnitALU  : ProcResource<1>; // Int ALU
38  def TSV110UnitAB   : ProcResource<2>; // Int ALU/BRU
39  def TSV110UnitMDU  : ProcResource<1>; // Multi-Cycle
40  def TSV110UnitFSU1 : ProcResource<1>; // FP/ASIMD
41  def TSV110UnitFSU2 : ProcResource<1>; // FP/ASIMD
42  def TSV110UnitLdSt : ProcResource<2>; // Load/Store
43
44  def TSV110UnitF     : ProcResGroup<[TSV110UnitFSU1, TSV110UnitFSU2]>;
45  def TSV110UnitALUAB : ProcResGroup<[TSV110UnitALU, TSV110UnitAB]>;
46  def TSV110UnitFLdSt : ProcResGroup<[TSV110UnitFSU1, TSV110UnitFSU2, TSV110UnitLdSt]>;
47}
48
49let SchedModel = TSV110Model in {
50
51//===----------------------------------------------------------------------===//
52// Map the target-defined scheduler read/write resources and latency for
53// TSV110
54
55// Integer ALU
56def : WriteRes<WriteImm,   [TSV110UnitALUAB]> { let Latency = 1; }
57def : WriteRes<WriteI,     [TSV110UnitALUAB]> { let Latency = 1; }
58def : WriteRes<WriteISReg, [TSV110UnitMDU]>   { let Latency = 2; }
59def : WriteRes<WriteIEReg, [TSV110UnitMDU]>   { let Latency = 2; }
60def : WriteRes<WriteExtr,  [TSV110UnitALUAB]> { let Latency = 1; }
61def : WriteRes<WriteIS,    [TSV110UnitALUAB]> { let Latency = 1; }
62
63// Integer Mul/MAC/Div
64def : WriteRes<WriteID32,  [TSV110UnitMDU]> { let Latency = 12;
65                                              let ResourceCycles = [12]; }
66def : WriteRes<WriteID64,  [TSV110UnitMDU]> { let Latency = 20;
67                                              let ResourceCycles = [20]; }
68def : WriteRes<WriteIM32,  [TSV110UnitMDU]> { let Latency = 3; }
69def : WriteRes<WriteIM64,  [TSV110UnitMDU]> { let Latency = 4; }
70
71// Load
72def : WriteRes<WriteLD,    [TSV110UnitLdSt]> { let Latency = 4; }
73def : WriteRes<WriteLDIdx, [TSV110UnitLdSt]> { let Latency = 4; }
74def : WriteRes<WriteLDHi,  []> { let Latency = 4; }
75
76// Pre/Post Indexing
77def : WriteRes<WriteAdr,   [TSV110UnitALUAB]> { let Latency = 1; }
78
79// Store
80def : WriteRes<WriteST,    [TSV110UnitLdSt]> { let Latency = 1; }
81def : WriteRes<WriteSTP,   [TSV110UnitLdSt]> { let Latency = 1; }
82def : WriteRes<WriteSTIdx, [TSV110UnitLdSt]> { let Latency = 1; }
83
84// FP
85def : WriteRes<WriteF,     [TSV110UnitF]> { let Latency = 2; }
86def : WriteRes<WriteFCmp,  [TSV110UnitF]> { let Latency = 3; }
87def : WriteRes<WriteFCvt,  [TSV110UnitF]> { let Latency = 3; }
88def : WriteRes<WriteFCopy, [TSV110UnitF]> { let Latency = 2; }
89def : WriteRes<WriteFImm,  [TSV110UnitF]> { let Latency = 2; }
90def : WriteRes<WriteFMul,  [TSV110UnitF]> { let Latency = 5; }
91
92// FP Div, Sqrt
93def : WriteRes<WriteFDiv,  [TSV110UnitFSU1]> { let Latency = 18; }
94
95def : WriteRes<WriteVd,    [TSV110UnitF]>     { let Latency = 4; }
96def : WriteRes<WriteVq,    [TSV110UnitF]>     { let Latency = 4; }
97def : WriteRes<WriteVLD,   [TSV110UnitFLdSt]> { let Latency = 5; }
98def : WriteRes<WriteVST,   [TSV110UnitF]>     { let Latency = 1; }
99
100// Branch
101def : WriteRes<WriteBr,    [TSV110UnitAB]> { let Latency = 1; }
102def : WriteRes<WriteBrReg, [TSV110UnitAB]> { let Latency = 1; }
103def : WriteRes<WriteSys,     []> { let Latency = 1; }
104def : WriteRes<WriteBarrier, []> { let Latency = 1; }
105def : WriteRes<WriteHint,    []> { let Latency = 1; }
106
107def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
108
109// Forwarding logic is modeled only for multiply and accumulate.
110def : ReadAdvance<ReadI,       0>;
111def : ReadAdvance<ReadISReg,   0>;
112def : ReadAdvance<ReadIEReg,   0>;
113def : ReadAdvance<ReadIM,      0>;
114def : ReadAdvance<ReadIMA,     2, [WriteIM32, WriteIM64]>;
115def : ReadAdvance<ReadID,      0>;
116def : ReadAdvance<ReadExtrHi,  0>;
117def : ReadAdvance<ReadAdrBase, 0>;
118def : ReadAdvance<ReadVLD,     0>;
119def : ReadAdvance<ReadST,      0>;
120
121def : InstRW<[WriteI], (instrs COPY)>;
122
123// Detailed Refinements
124//===----------------------------------------------------------------------===//
125
126// Contains all of the TSV110 specific SchedWriteRes types. The approach
127// below is to define a generic SchedWriteRes for every combination of
128// latency and microOps. The naming conventions is to use a prefix, one field
129// for latency, and one or more microOp count/type designators.
130//   Prefix: TSV110Wr
131//       Latency: #cyc
132//   MicroOp Count/Types: #(ALU|AB|MDU|FSU1|FSU2|LdSt|ALUAB|F|FLdSt)
133//
134// e.g. TSV110Wr_6cyc_1ALU_6MDU_4LdSt means the total latency is 6 and there are
135//      1 micro-ops to be issued down one ALU pipe, six MDU pipes and four LdSt pipes.
136//
137
138//===----------------------------------------------------------------------===//
139// Define Generic 1 micro-op types
140
141def TSV110Wr_1cyc_1AB    : SchedWriteRes<[TSV110UnitAB]>    { let Latency = 1; }
142def TSV110Wr_1cyc_1ALU   : SchedWriteRes<[TSV110UnitALU]>   { let Latency = 1; }
143def TSV110Wr_1cyc_1ALUAB : SchedWriteRes<[TSV110UnitALUAB]> { let Latency = 1; }
144def TSV110Wr_1cyc_1LdSt  : SchedWriteRes<[TSV110UnitLdSt]>  { let Latency = 1; }
145
146def TSV110Wr_2cyc_1AB    : SchedWriteRes<[TSV110UnitAB]>    { let Latency = 2; }
147def TSV110Wr_2cyc_1ALU   : SchedWriteRes<[TSV110UnitALU]>   { let Latency = 2; }
148def TSV110Wr_2cyc_1LdSt  : SchedWriteRes<[TSV110UnitLdSt]>  { let Latency = 2; }
149def TSV110Wr_2cyc_1MDU   : SchedWriteRes<[TSV110UnitMDU]>   { let Latency = 2; }
150def TSV110Wr_2cyc_1FSU1  : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 2; }
151def TSV110Wr_2cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 2; }
152
153def TSV110Wr_3cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 3; }
154def TSV110Wr_3cyc_1FSU1  : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 3; }
155def TSV110Wr_3cyc_1MDU   : SchedWriteRes<[TSV110UnitMDU]>   { let Latency = 3; }
156
157def TSV110Wr_4cyc_1FSU1  : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 4; }
158def TSV110Wr_4cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 4; }
159def TSV110Wr_4cyc_1LdSt  : SchedWriteRes<[TSV110UnitLdSt]>  { let Latency = 4; }
160def TSV110Wr_4cyc_1MDU   : SchedWriteRes<[TSV110UnitMDU]>   { let Latency = 4; }
161
162def TSV110Wr_5cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 5; }
163def TSV110Wr_5cyc_1FSU1  : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 5; }
164def TSV110Wr_5cyc_1FSU2  : SchedWriteRes<[TSV110UnitFSU2]>  { let Latency = 5; }
165def TSV110Wr_5cyc_1LdSt  : SchedWriteRes<[TSV110UnitLdSt]>  { let Latency = 5; }
166
167def TSV110Wr_6cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 6; }
168
169def TSV110Wr_7cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 7; }
170
171def TSV110Wr_8cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 8; }
172
173def TSV110Wr_11cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 11; }
174
175def TSV110Wr_12cyc_1MDU  : SchedWriteRes<[TSV110UnitMDU]>   { let Latency = 12; }
176
177def TSV110Wr_17cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]>  { let Latency = 17; }
178
179def TSV110Wr_18cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 18; }
180
181def TSV110Wr_20cyc_1MDU  : SchedWriteRes<[TSV110UnitMDU]>   { let Latency = 20; }
182
183def TSV110Wr_24cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 24; }
184
185def TSV110Wr_31cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]>  { let Latency = 31; }
186
187def TSV110Wr_36cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]>  { let Latency = 36; }
188
189def TSV110Wr_38cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 38; }
190
191def TSV110Wr_64cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]>  { let Latency = 64; }
192
193//===----------------------------------------------------------------------===//
194// Define Generic 2 micro-op types
195
196def TSV110Wr_1cyc_1LdSt_1ALUAB : SchedWriteRes<[TSV110UnitLdSt,
197                                                TSV110UnitALUAB]> {
198  let Latency = 1;
199  let NumMicroOps = 2;
200}
201
202def TSV110Wr_2cyc_1LdSt_1ALUAB :  SchedWriteRes<[TSV110UnitLdSt,
203                                                 TSV110UnitALUAB]> {
204  let Latency = 2;
205  let NumMicroOps = 2;
206}
207
208def TSV110Wr_2cyc_2LdSt        : SchedWriteRes<[TSV110UnitLdSt,
209                                                TSV110UnitLdSt]> {
210  let Latency = 2;
211  let NumMicroOps = 2;
212}
213
214def TSV110Wr_2cyc_2F           : SchedWriteRes<[TSV110UnitF,
215                                                TSV110UnitF]> {
216  let Latency = 2;
217  let NumMicroOps = 2;
218}
219
220def TSV110Wr_2cyc_1FSU1_1FSU2  : SchedWriteRes<[TSV110UnitFSU1,
221                                                TSV110UnitFSU2]> {
222  let Latency = 2;
223  let NumMicroOps = 2;
224}
225
226def TSV110Wr_4cyc_2F           : SchedWriteRes<[TSV110UnitF,
227                                                TSV110UnitF]> {
228  let Latency = 4;
229  let NumMicroOps = 2;
230}
231
232def TSV110Wr_4cyc_1FSU1_1FSU2  : SchedWriteRes<[TSV110UnitFSU1,
233                                                TSV110UnitFSU2]> {
234  let Latency = 4;
235  let NumMicroOps = 2;
236}
237
238def TSV110Wr_4cyc_1LdSt_1ALUAB : SchedWriteRes<[TSV110UnitLdSt,
239                                                TSV110UnitALUAB]> {
240  let Latency = 4;
241  let NumMicroOps = 2;
242}
243
244def TSV110Wr_5cyc_1ALU_1F      : SchedWriteRes<[TSV110UnitALU,
245                                                TSV110UnitF]> {
246  let Latency     = 5;
247  let NumMicroOps = 2;
248}
249
250def TSV110Wr_6cyc_2LdSt        : SchedWriteRes<[TSV110UnitLdSt,
251                                                TSV110UnitLdSt]> {
252  let Latency = 6;
253  let NumMicroOps = 2;
254}
255
256def TSV110Wr_6cyc_1LdSt_1ALUAB : SchedWriteRes<[TSV110UnitLdSt,
257                                                TSV110UnitALUAB]> {
258  let Latency = 6;
259  let NumMicroOps = 2;
260}
261
262def TSV110Wr_7cyc_1F_1LdSt     : SchedWriteRes<[TSV110UnitF,
263                                                TSV110UnitLdSt]> {
264  let Latency = 7;
265  let NumMicroOps = 2;
266}
267
268def TSV110Wr_8cyc_2FSU1        : SchedWriteRes<[TSV110UnitFSU1,
269                                                TSV110UnitFSU1]> {
270  let Latency = 8;
271  let NumMicroOps = 2;
272}
273
274
275def TSV110Wr_8cyc_1FSU1_1FSU2  : SchedWriteRes<[TSV110UnitFSU1,
276                                                TSV110UnitFSU2]> {
277  let Latency = 8;
278  let NumMicroOps = 2;
279}
280
281//===----------------------------------------------------------------------===//
282// Define Generic 3 micro-op types
283
284def TSV110Wr_6cyc_3F       : SchedWriteRes<[TSV110UnitF, TSV110UnitF,
285                                            TSV110UnitF]> {
286  let Latency     = 6;
287  let NumMicroOps = 3;
288}
289
290def TSV110Wr_6cyc_3LdSt    : SchedWriteRes<[TSV110UnitLdSt, TSV110UnitLdSt,
291                                            TSV110UnitLdSt]> {
292  let Latency = 6;
293  let NumMicroOps = 3;
294}
295
296def TSV110Wr_7cyc_2F_1LdSt : SchedWriteRes<[TSV110UnitF, TSV110UnitF,
297                                                         TSV110UnitLdSt]> {
298  let Latency = 7;
299  let NumMicroOps = 3;
300}
301
302//===----------------------------------------------------------------------===//
303// Define Generic 4 micro-op types
304
305def TSV110Wr_8cyc_4F          : SchedWriteRes<[TSV110UnitF, TSV110UnitF,
306                                               TSV110UnitF, TSV110UnitF]> {
307  let Latency = 8;
308  let NumMicroOps = 4;
309}
310
311def TSV110Wr_8cyc_3F_1LdSt    : SchedWriteRes<[TSV110UnitF, TSV110UnitF,
312                                               TSV110UnitF, TSV110UnitLdSt]> {
313  let Latency = 8;
314  let NumMicroOps = 4;
315}
316
317//===----------------------------------------------------------------------===//
318// Define Generic 5 micro-op types
319
320def TSV110Wr_8cyc_3F_2LdSt : SchedWriteRes<[TSV110UnitF, TSV110UnitF, TSV110UnitF,
321                                            TSV110UnitLdSt, TSV110UnitLdSt]> {
322  let Latency = 8;
323  let NumMicroOps = 5;
324}
325
326//===----------------------------------------------------------------------===//
327// Define Generic 8 micro-op types
328
329def TSV110Wr_10cyc_4F_4LdSt : SchedWriteRes<[TSV110UnitF, TSV110UnitF,
330                                             TSV110UnitF, TSV110UnitF,
331                                             TSV110UnitLdSt, TSV110UnitLdSt,
332                                             TSV110UnitLdSt, TSV110UnitLdSt]> {
333  let Latency = 10;
334  let NumMicroOps = 8;
335}
336
337
338// Branch Instructions
339// -----------------------------------------------------------------------------
340
341def : InstRW<[TSV110Wr_1cyc_1AB], (instrs B)>;
342def : InstRW<[TSV110Wr_1cyc_1AB], (instrs BL)>;
343def : InstRW<[TSV110Wr_1cyc_1AB], (instrs BLR)>;
344def : InstRW<[TSV110Wr_1cyc_1AB], (instregex "^(BR|RET|(CBZ|CBNZ|TBZ|TBNZ))$")>;
345
346
347// Cryptography Extensions
348// -----------------------------------------------------------------------------
349
350def : InstRW<[TSV110Wr_3cyc_1FSU1], (instregex "^AES[DE]")>;
351def : InstRW<[TSV110Wr_3cyc_1FSU1], (instregex "^AESI?MC")>;
352def : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^SHA1SU1")>;
353def : InstRW<[TSV110Wr_2cyc_2F],    (instregex "^SHA1(H|SU0)")>;
354def : InstRW<[TSV110Wr_5cyc_1FSU1], (instregex "^SHA1[CMP]")>;
355def : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^SHA256SU0")>;
356def : InstRW<[TSV110Wr_3cyc_1FSU1], (instregex "^SHA256SU1")>;
357def : InstRW<[TSV110Wr_5cyc_1FSU1], (instregex "^SHA256(H|H2)")>;
358def TSV110ReadCRC: SchedReadAdvance<1, [TSV110Wr_2cyc_1MDU]>;
359def : InstRW<[TSV110Wr_2cyc_1MDU, TSV110ReadCRC],  (instregex "^CRC32.*$")>;
360
361
362// Arithmetic and Logical Instructions
363// -----------------------------------------------------------------------------
364
365def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "(BIC|EON|ORN)[WX]rr")>;
366def : InstRW<[TSV110Wr_1cyc_1AB],    (instregex "(BIC)S[WX]rr")>;
367
368def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "(ADD|AND|EOR|ORR|SUB)[WX]r(r|i)")>;
369def : InstRW<[TSV110Wr_1cyc_1AB],    (instregex "(ADD|AND|EOR|ORR|SUB)S[WX]r(r|i)")>;
370
371def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(ADC|SBC|BIC)[WX]r$")>;
372def : InstRW<[TSV110Wr_1cyc_1AB],    (instregex "^(ADC|SBC)S[WX]r$")>;
373
374def : InstRW<[TSV110Wr_2cyc_1MDU],   (instregex "^(AND|BIC|EON|EOR|ORN|ORR)[WX]rs$")>;
375def : InstRW<[TSV110Wr_2cyc_1AB],    (instregex "^(AND|BIC|EON|EOR|ORN|ORR)S[WX]rs$")>;
376def : InstRW<[TSV110Wr_2cyc_1MDU],   (instregex "^(ADD|SUB)[WX]r(s|x|x64)$")>;
377def : InstRW<[TSV110Wr_2cyc_1AB],    (instregex "^(ADD|SUB)S[WX]r(s|x|x64)$")>;
378
379def : InstRW<[TSV110Wr_1cyc_1AB],    (instregex "^(CCMN|CCMP)(W|X)(r|i)$")>;
380def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
381
382
383// Move and Shift Instructions
384// -----------------------------------------------------------------------------
385
386def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instrs ADR, ADRP)>;
387def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^MOV[NZK][WX]i")>;
388def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "(LSLV|LSRV|ASRV|RORV)(W|X)r")>;
389
390
391// Divide and Multiply Instructions
392// -----------------------------------------------------------------------------
393
394def : InstRW<[TSV110Wr_12cyc_1MDU],  (instregex "^(S|U)DIVWr$")>;
395def : InstRW<[TSV110Wr_20cyc_1MDU],  (instregex "^(S|U)DIVXr$")>;
396
397def TSV110ReadMAW : SchedReadAdvance<2, [TSV110Wr_3cyc_1MDU]>;
398def : InstRW<[TSV110Wr_3cyc_1MDU, TSV110ReadMAW], (instrs MADDWrrr, MSUBWrrr)>;
399def TSV110ReadMAQ : SchedReadAdvance<3, [TSV110Wr_4cyc_1MDU]>;
400def : InstRW<[TSV110Wr_4cyc_1MDU, TSV110ReadMAQ], (instrs MADDXrrr, MSUBXrrr)>;
401def : InstRW<[TSV110Wr_3cyc_1MDU, TSV110ReadMAW], (instregex "(S|U)(MADDL|MSUBL)rrr")>;
402def : InstRW<[TSV110Wr_4cyc_1MDU], (instregex "^(S|U)MULHrr$")>;
403
404
405// Miscellaneous Data-Processing Instructions
406// -----------------------------------------------------------------------------
407
408def : InstRW<[TSV110Wr_1cyc_1ALUAB],    (instregex "^EXTR(W|X)rri$")>;
409def : InstRW<[TSV110Wr_1cyc_1ALUAB],    (instregex "^(S|U)?BFM(W|X)ri$")>;
410def : InstRW<[TSV110Wr_1cyc_1ALUAB],    (instregex "^(CLS|CLZ|RBIT|REV(16|32)?)(W|X)r$")>;
411
412
413// Load Instructions
414// -----------------------------------------------------------------------------
415
416def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^LDR(W|X)l$")>;
417def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instrs LDRSWl)>;
418
419def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^LDR(BB|HH|W|X)ui$")>;
420def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>;
421
422def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteAdr],     (instregex "^LDR(BB|HH|W|X)(post|pre)$")>;
423def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteAdr],     (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
424
425def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^LDTR(B|H|W|X)i$")>;
426def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^LDUR(BB|HH|W|X)i$")>;
427def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>;
428def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^LDURS(BW|BX|HW|HX|W)i$")>;
429
430def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteLDHi],     (instregex "^LDNP(W|X)i$")>;
431def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteLDHi],     (instregex "^LDP(W|X)i$")>;
432def : InstRW<[TSV110Wr_4cyc_1LdSt_1ALUAB, WriteLDHi, WriteAdr],(instregex "^LDP(W|X)(post|pre)$")>;
433
434def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteLDHi],           (instrs LDPSWi)>;
435def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteLDHi, WriteAdr], (instrs LDPSWpost)>;
436def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteLDHi, WriteAdr], (instrs LDPSWpre)>;
437
438def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instrs PRFMl)>;
439def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instrs PRFUMi)>;
440def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^PRFMui$")>;
441def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^PRFMro(W|X)$")>;
442
443
444// Store Instructions
445// -----------------------------------------------------------------------------
446
447def : InstRW<[TSV110Wr_1cyc_1LdSt],            (instregex "^STN?P(W|X)i$")>;
448def : InstRW<[TSV110Wr_1cyc_1LdSt, WriteAdr],  (instregex "^STP(W|X)(post|pre)$")>;
449def : InstRW<[TSV110Wr_1cyc_1LdSt],            (instregex "^STUR(BB|HH|W|X)i$")>;
450def : InstRW<[TSV110Wr_1cyc_1LdSt],            (instregex "^STTR(B|H|W|X)i$")>;
451def : InstRW<[TSV110Wr_1cyc_1LdSt],            (instregex "^STR(BB|HH|W|X)ui$")>;
452
453def : InstRW<[TSV110Wr_1cyc_1LdSt, WriteAdr],  (instregex "^STR(BB|HH|W|X)(post|pre)$")>;
454def : InstRW<[TSV110Wr_1cyc_1LdSt, WriteAdr],  (instregex "^STR(BB|HH|W|X)ro(W|X)$")>;
455
456
457// FP Data Processing Instructions
458// -----------------------------------------------------------------------------
459
460def : InstRW<[TSV110Wr_2cyc_1F], (instregex "F(ABS|NEG)(D|S)r")>;
461def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FCCMP(E)?(S|D)rr$")>;
462def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FCMP(E)?(S|D)r(r|i)$")>;
463def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FCSEL(S|D)rrr$")>;
464
465def : InstRW<[TSV110Wr_11cyc_1FSU1], (instrs FDIVSrr)>;
466def : InstRW<[TSV110Wr_18cyc_1FSU1], (instrs FDIVDrr)>;
467def : InstRW<[TSV110Wr_17cyc_1FSU2], (instrs FSQRTSr)>;
468def : InstRW<[TSV110Wr_31cyc_1FSU2], (instrs FSQRTDr)>;
469
470def : InstRW<[TSV110Wr_2cyc_1F], (instregex "^F(MAX|MIN).+rr")>;
471
472def : InstRW<[TSV110Wr_4cyc_1F], (instregex "^FN?M(ADD|SUB)Hrrr")>;
473def : InstRW<[TSV110Wr_5cyc_1F], (instregex "^FN?M(ADD|SUB)Srrr")>;
474def : InstRW<[TSV110Wr_7cyc_1F], (instregex "^FN?M(ADD|SUB)Drrr")>;
475
476def : InstRW<[TSV110Wr_4cyc_1F], (instregex "^F(ADD|SUB)Hrr")>;
477def : InstRW<[TSV110Wr_5cyc_1F], (instregex "^F(ADD|SUB)Srr")>;
478def : InstRW<[TSV110Wr_4cyc_1F], (instregex "^F(ADD|SUB)Drr")>;
479
480def : InstRW<[TSV110Wr_4cyc_1F], (instregex "^F(N)?MULHrr$")>;
481def : InstRW<[TSV110Wr_5cyc_1F], (instregex "^F(N)?MULSrr$")>;
482def : InstRW<[TSV110Wr_5cyc_1F], (instregex "^F(N)?MULDrr$")>;
483
484def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FRINT.+r")>;
485
486
487// FP Miscellaneous Instructions
488// -----------------------------------------------------------------------------
489
490def : InstRW<[TSV110Wr_5cyc_1ALU_1F], (instregex "^[SU]CVTF[SU][WX][SD]ri")>;
491def : InstRW<[TSV110Wr_4cyc_1FSU1],   (instregex "^FCVT(A|M|N|P|Z)(S|U)U(W|X)(S|D)r$")>;
492def : InstRW<[TSV110Wr_3cyc_1F],      (instregex "^FCVT[HSD][HSD]r")>;
493
494def : InstRW<[TSV110Wr_2cyc_1FSU1],   (instregex "^FMOV(DX|WS|XD|SW|DXHigh|XDHigh)r$")>;
495def : InstRW<[TSV110Wr_2cyc_1F],      (instregex "^FMOV[SD][ir]$")>;
496
497
498// FP Load Instructions
499// -----------------------------------------------------------------------------
500
501def : InstRW<[TSV110Wr_5cyc_1LdSt],                      (instregex "^LDR[DSQ]l")>;
502def : InstRW<[TSV110Wr_5cyc_1LdSt],                      (instregex "^LDUR[BDHSQ]i")>;
503def : InstRW<[TSV110Wr_5cyc_1LdSt, WriteAdr],            (instregex "^LDR[BDHSQ](post|pre)")>;
504def : InstRW<[TSV110Wr_5cyc_1LdSt],                      (instregex "^LDR[BDHSQ]ui")>;
505def : InstRW<[TSV110Wr_6cyc_1LdSt_1ALUAB, ReadAdrBase],  (instregex "^LDR(Q|D|H|S|B)ro(W|X)$")>;
506def : InstRW<[TSV110Wr_5cyc_1LdSt, WriteLDHi],           (instregex "^LDN?P[DQS]i")>;
507def : InstRW<[TSV110Wr_5cyc_1LdSt, WriteLDHi, WriteAdr], (instregex "^LDP[DQS](post|pre)")>;
508
509
510// FP Store Instructions
511// -----------------------------------------------------------------------------
512
513def : InstRW<[TSV110Wr_1cyc_1LdSt],                     (instregex "^STUR[BHSDQ]i")>;
514def : InstRW<[TSV110Wr_1cyc_1LdSt_1ALUAB, ReadAdrBase], (instregex "^STR[BHSDQ](post|pre)")>;
515def : InstRW<[TSV110Wr_1cyc_1LdSt],                     (instregex "^STR[BHSDQ]ui")>;
516def : InstRW<[TSV110Wr_2cyc_1LdSt_1ALUAB, ReadAdrBase], (instregex "^STR[BHSDQ]ro[WX]")>;
517def : InstRW<[TSV110Wr_2cyc_2LdSt],                     (instregex "^STN?P[SDQ]i")>;
518def : InstRW<[TSV110Wr_2cyc_2LdSt, WriteAdr],           (instregex "^STP[SDQ](post|pre)")>;
519
520
521// ASIMD Integer Instructions
522// -----------------------------------------------------------------------------
523
524// Reference for forms in this group
525//   D form - v8i8, v4i16, v2i32
526//   Q form - v16i8, v8i16, v4i32
527//   D form - v1i8, v1i16, v1i32, v1i64
528//   Q form - v16i8, v8i16, v4i32, v2i64
529//   D form - v8i8_v8i16, v4i16_v4i32, v2i32_v2i64
530//   Q form - v16i8_v8i16, v8i16_v4i32, v4i32_v2i64
531
532// ASIMD simple arithmetic
533def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(ABS|ADD(P)?|NEG|SUB)v")>;
534def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^[SU](ADD(L|LP|W)|SUB(L|W))v")>;
535
536// ASIMD complex arithmetic
537def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]H(ADD|SUB)v")>;
538def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^R?(ADD|SUB)HN2?v")>;
539def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]Q(ADD|SUB)v")>;
540def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^(SU|US)QADDv")>;
541def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]RHADDv")>;
542def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]ABAL?v")>;
543def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]ABDL?v")>;
544def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]ADALPv")>;
545def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^((SQ)(ABS|NEG))v")>;
546
547// ASIMD compare
548def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT|TST)v")>;
549
550// ASIMD max/min
551def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^[SU](MIN|MAX)P?v")>;
552
553// ASIMD logical
554def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(AND|BIC|BIF|BIT|BSL|EOR|MVN|NOT|ORN|ORR)v")>;
555
556// ASIMD multiply accumulate, D-form
557def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^(MUL|ML[AS]|SQR?D(MULH))(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)")>;
558// ASIMD multiply accumulate, Q-form
559def : InstRW<[TSV110Wr_8cyc_2FSU1], (instregex "^(MUL|ML[AS]|SQR?D(MULH))(v16i8|v8i16|v4i32)")>;
560
561// ASIMD multiply accumulate long
562def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "(S|U|SQD)(MLAL|MLSL|MULL)v.*")>;
563def : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^PMULL(v8i8|v16i8)")>;
564def : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^PMULL(v1i64|v2i64)")>;
565
566// ASIMD shift
567// ASIMD shift accumulate
568def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^(S|SR|U|UR)SRA")>;
569// ASIMD shift by immed, basic
570def : InstRW<[TSV110Wr_4cyc_1FSU1],
571            (instregex "SHLv","SLIv","SRIv","SHRNv","SQXTNv","SQXTUNv","UQXTNv")>;
572// ASIMD shift by immed, complex
573def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^[SU]?(Q|R){1,2}SHR")>;
574def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^SQSHLU")>;
575// ASIMD shift by register, basic, Q-form
576def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>;
577// ASIMD shift by register, complex, D-form
578def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
579// ASIMD shift by register, complex, Q-form
580def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i64)")>;
581
582// ASIMD reduction
583// ASIMD arith, reduce, 4H/4S
584def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
585// ASIMD arith, reduce, 8B/8H
586def : InstRW<[TSV110Wr_8cyc_1FSU1_1FSU2], (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>;
587// ASIMD arith, reduce, 16B
588def : InstRW<[TSV110Wr_8cyc_1FSU1_1FSU2], (instregex "^[SU]?ADDL?Vv16i8v$")>;
589
590// ASIMD max/min, reduce, 4H/4S
591def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v$")>;
592// ASIMD max/min, reduce, 8B/8H
593def : InstRW<[TSV110Wr_8cyc_1FSU1_1FSU2], (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>;
594// ASIMD max/min, reduce, 16B
595def : InstRW<[TSV110Wr_8cyc_1FSU1_1FSU2], (instregex "^[SU](MIN|MAX)Vv16i8v$")>;
596
597
598// Vector - Floating Point
599// -----------------------------------------------------------------------------
600
601// Reference for forms in this group
602//   D form - v2f32
603//   Q form - v4f32, v2f64
604//   D form - 32, 64
605//   D form - v1i32, v1i64
606//   D form - v2i32
607//   Q form - v4i32, v2i64
608
609// ASIMD FP sign manipulation
610def : InstRW<[TSV110Wr_2cyc_1F],  (instregex "^FABSv")>;
611def : InstRW<[TSV110Wr_2cyc_1F],  (instregex "^FNEGv")>;
612
613// ASIMD FP compare
614def : InstRW<[TSV110Wr_2cyc_1F],  (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v")>;
615
616// ASIMD FP convert
617def : InstRW<[TSV110Wr_2cyc_1F],  (instregex "^FCVT[AMNPZ][SU]v")>;
618def : InstRW<[TSV110Wr_3cyc_1F],  (instregex "^FCVT(L)v")>;
619def : InstRW<[TSV110Wr_5cyc_1F],  (instregex "^FCVT(N|XN)v")>;
620
621// ASIMD FP divide, D-form, F32
622def : InstRW<[TSV110Wr_11cyc_1FSU1], (instregex "FDIVv2f32")>;
623// ASIMD FP divide, Q-form, F32
624def : InstRW<[TSV110Wr_24cyc_1FSU1], (instregex "FDIVv4f32")>;
625// ASIMD FP divide, Q-form, F64
626def : InstRW<[TSV110Wr_38cyc_1FSU1], (instregex "FDIVv2f64")>;
627
628// ASIMD FP SQRT
629def : InstRW<[TSV110Wr_17cyc_1FSU2], (instrs FSQRTv2f32)>;
630def : InstRW<[TSV110Wr_36cyc_1FSU2], (instrs FSQRTv4f32)>;
631def : InstRW<[TSV110Wr_64cyc_1FSU2], (instrs FSQRTv2f64)>;
632
633// ASIMD FP max,min
634def : InstRW<[TSV110Wr_2cyc_1F],  (instregex "^F(MAX|MIN)(NM)?v")>;
635def : InstRW<[TSV110Wr_2cyc_1F],  (instregex "^F(MAX|MIN)(NM)?Pv")>;
636def : InstRW<[TSV110Wr_4cyc_1F],  (instregex "^F(MAX|MIN)(NM)?Vv")>;
637
638// ASIMD FP add
639def : InstRW<[TSV110Wr_5cyc_1F],  (instregex "^F(ADD|ADDP|SUB)v")>;
640
641// ASIMD FP multiply
642def : InstRW<[TSV110Wr_5cyc_1F],  (instregex "^FMULX?v")>;
643
644
645// ASIMD Miscellaneous Instructions
646// -----------------------------------------------------------------------------
647
648def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(CLS|CLZ|CNT)v")>;
649def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(DUP|INS)v.+lane")>;
650def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^REV(16|32|64)v")>;
651def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(UZP|ZIP)[12]v")>;
652
653def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^EXTv")>;
654def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^XTNv")>;
655def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^RBITv")>;
656
657def : InstRW<[TSV110Wr_4cyc_1F], (instregex "^(INS|DUP)v.+gpr")>;
658
659def : InstRW<[TSV110Wr_3cyc_1FSU1], (instregex "^[SU]MOVv")>;
660
661// ASIMD table lookup, D-form
662def : InstRW<[TSV110Wr_2cyc_1F], (instregex "^TB[LX]v8i8One")>;
663def : InstRW<[TSV110Wr_4cyc_2F], (instregex "^TB[LX]v8i8Two")>;
664def : InstRW<[TSV110Wr_6cyc_3F], (instregex "^TB[LX]v8i8Three")>;
665def : InstRW<[TSV110Wr_8cyc_4F], (instregex "^TB[LX]v8i8Four")>;
666// ASIMD table lookup, Q-form
667def : InstRW<[TSV110Wr_2cyc_1F], (instregex "^TB[LX]v16i8One")>;
668def : InstRW<[TSV110Wr_4cyc_2F], (instregex "^TB[LX]v16i8Two")>;
669def : InstRW<[TSV110Wr_6cyc_3F], (instregex "^TB[LX]v16i8Three")>;
670def : InstRW<[TSV110Wr_8cyc_4F], (instregex "^TB[LX]v16i8Four")>;
671
672def : InstRW<[TSV110Wr_2cyc_1F], (instregex "^FMOVv")>;
673
674def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FRINT[AIMNPXZ]v")>;
675def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^[SU]CVTFv")>;
676def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^[FU](RECP|RSQRT)(E|X)v")>;
677
678
679// ASIMD Load Instructions
680// -----------------------------------------------------------------------------
681
682def : InstRW<[TSV110Wr_7cyc_1F_1LdSt],            (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
683def : InstRW<[TSV110Wr_7cyc_1F_1LdSt, WriteAdr],  (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
684def : InstRW<[TSV110Wr_7cyc_2F_1LdSt],            (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
685def : InstRW<[TSV110Wr_7cyc_2F_1LdSt, WriteAdr],  (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
686def : InstRW<[TSV110Wr_8cyc_3F_1LdSt],            (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
687def : InstRW<[TSV110Wr_8cyc_3F_1LdSt, WriteAdr],  (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
688def : InstRW<[TSV110Wr_8cyc_3F_2LdSt],            (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
689def : InstRW<[TSV110Wr_8cyc_3F_2LdSt, WriteAdr],  (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
690
691def  : InstRW<[TSV110Wr_7cyc_1F_1LdSt],           (instregex "LD1i(8|16|32|64)$")>;
692def  : InstRW<[TSV110Wr_7cyc_1F_1LdSt, WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>;
693def  : InstRW<[TSV110Wr_7cyc_2F_1LdSt],           (instregex "LD2i(8|16|32|64)$")>;
694def  : InstRW<[TSV110Wr_7cyc_2F_1LdSt, WriteAdr], (instregex "LD2i(8|16|32|64)_POST$")>;
695def  : InstRW<[TSV110Wr_8cyc_3F_1LdSt],           (instregex "LD3i(8|16|32|64)$")>;
696def  : InstRW<[TSV110Wr_8cyc_3F_1LdSt, WriteAdr], (instregex "LD3i(8|16|32|64)_POST$")>;
697def  : InstRW<[TSV110Wr_8cyc_3F_2LdSt],           (instregex "LD4i(8|16|32|64)$")>;
698def  : InstRW<[TSV110Wr_8cyc_3F_2LdSt, WriteAdr], (instregex "LD4i(8|16|32|64)_POST$")>;
699
700def : InstRW<[TSV110Wr_5cyc_1LdSt],               (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
701def : InstRW<[TSV110Wr_5cyc_1LdSt, WriteAdr],     (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
702def : InstRW<[TSV110Wr_5cyc_1LdSt],               (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
703def : InstRW<[TSV110Wr_5cyc_1LdSt, WriteAdr],     (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
704def : InstRW<[TSV110Wr_6cyc_3LdSt],               (instregex "^LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
705def : InstRW<[TSV110Wr_6cyc_3LdSt, WriteAdr],     (instregex "^LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
706def : InstRW<[TSV110Wr_6cyc_2LdSt],               (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
707def : InstRW<[TSV110Wr_6cyc_2LdSt, WriteAdr],     (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
708
709def : InstRW<[TSV110Wr_7cyc_2F_1LdSt],            (instregex "^LD2Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
710def : InstRW<[TSV110Wr_7cyc_2F_1LdSt, WriteAdr],  (instregex "^LD2Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
711
712def : InstRW<[TSV110Wr_8cyc_3F_1LdSt],            (instregex "^LD3Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
713def : InstRW<[TSV110Wr_8cyc_3F_1LdSt, WriteAdr],  (instregex "^LD3Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
714
715def : InstRW<[TSV110Wr_10cyc_4F_4LdSt],           (instregex "^LD4Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
716def : InstRW<[TSV110Wr_10cyc_4F_4LdSt, WriteAdr], (instregex "^LD4Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
717
718
719// ASIMD Store Instructions
720// -----------------------------------------------------------------------------
721
722def  : InstRW<[TSV110Wr_3cyc_1F],             (instregex "ST1i(8|16|32|64)$")>;
723def  : InstRW<[TSV110Wr_3cyc_1F, WriteAdr],   (instregex "ST1i(8|16|32|64)_POST$")>;
724def  : InstRW<[TSV110Wr_4cyc_1F],             (instregex "ST2i(8|16|32|64)$")>;
725def  : InstRW<[TSV110Wr_4cyc_1F, WriteAdr],   (instregex "ST2i(8|16|32|64)_POST$")>;
726def  : InstRW<[TSV110Wr_5cyc_1F],             (instregex "ST3i(8|16|32|64)$")>;
727def  : InstRW<[TSV110Wr_5cyc_1F, WriteAdr],   (instregex "ST3i(8|16|32|64)_POST$")>;
728def  : InstRW<[TSV110Wr_6cyc_1F],             (instregex "ST4i(8|16|32|64)$")>;
729def  : InstRW<[TSV110Wr_6cyc_1F, WriteAdr],   (instregex "ST4i(8|16|32|64)_POST$")>;
730
731def : InstRW<[TSV110Wr_3cyc_1F],              (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
732def : InstRW<[TSV110Wr_3cyc_1F, WriteAdr],    (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
733def : InstRW<[TSV110Wr_4cyc_1F],              (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
734def : InstRW<[TSV110Wr_4cyc_1F, WriteAdr],    (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
735def : InstRW<[TSV110Wr_5cyc_1F],              (instregex "^ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
736def : InstRW<[TSV110Wr_5cyc_1F, WriteAdr],    (instregex "^ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
737def : InstRW<[TSV110Wr_6cyc_1F],              (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
738def : InstRW<[TSV110Wr_6cyc_1F, WriteAdr],    (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
739
740def : InstRW<[TSV110Wr_4cyc_1F],              (instregex "^ST2Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
741def : InstRW<[TSV110Wr_4cyc_1F, WriteAdr],    (instregex "^ST2Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
742
743def : InstRW<[TSV110Wr_5cyc_1F],              (instregex "^ST3Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
744def : InstRW<[TSV110Wr_5cyc_1F, WriteAdr],    (instregex "^ST3Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
745
746def : InstRW<[TSV110Wr_8cyc_1F],              (instregex "^ST4Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
747def : InstRW<[TSV110Wr_8cyc_1F, WriteAdr],    (instregex "^ST4Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
748
749} // SchedModel = TSV110Model
750