xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AArch64SchedTSV110.td (revision 924226fba12cc9a228c73b956e1b7fa24c60b055)
1//==- AArch64SchedTSV110.td - Huawei TSV110 Scheduling Definitions -*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the machine model for Huawei TSV110 to support
10// instruction scheduling and other instruction cost heuristics.
11//
12//===----------------------------------------------------------------------===//
13
14// ===---------------------------------------------------------------------===//
15// The following definitions describe the simpler per-operand machine model.
16// This works with MachineScheduler. See llvm/MC/MCSchedule.h for details.
17
18// Huawei TSV110 scheduling machine model.
19def TSV110Model : SchedMachineModel {
20  let IssueWidth            =   4; // 4 micro-ops dispatched  per cycle.
21  let MicroOpBufferSize     = 128; // 128 micro-op re-order buffer
22  let LoopMicroOpBufferSize =  16;
23  let LoadLatency           =   4; // Optimistic load latency.
24  let MispredictPenalty     =  14; // Fetch + Decode/Rename/Dispatch + Branch
25  let CompleteModel         =   1;
26
27  list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
28                                                    PAUnsupported.F);
29}
30
31// Define each kind of processor resource and number available on the TSV110,
32// which has 8 pipelines, each with its own queue where micro-ops wait for
33// their operands and issue out-of-order to one of eight execution pipelines.
34let SchedModel = TSV110Model in {
35  def TSV110UnitALU  : ProcResource<1>; // Int ALU
36  def TSV110UnitAB   : ProcResource<2>; // Int ALU/BRU
37  def TSV110UnitMDU  : ProcResource<1>; // Multi-Cycle
38  def TSV110UnitFSU1 : ProcResource<1>; // FP/ASIMD
39  def TSV110UnitFSU2 : ProcResource<1>; // FP/ASIMD
40  def TSV110UnitLdSt : ProcResource<2>; // Load/Store
41
42  def TSV110UnitF     : ProcResGroup<[TSV110UnitFSU1, TSV110UnitFSU2]>;
43  def TSV110UnitALUAB : ProcResGroup<[TSV110UnitALU, TSV110UnitAB]>;
44  def TSV110UnitFLdSt : ProcResGroup<[TSV110UnitFSU1, TSV110UnitFSU2, TSV110UnitLdSt]>;
45}
46
47let SchedModel = TSV110Model in {
48
49//===----------------------------------------------------------------------===//
50// Map the target-defined scheduler read/write resources and latency for
51// TSV110
52
53// Integer ALU
54def : WriteRes<WriteImm,   [TSV110UnitALUAB]> { let Latency = 1; }
55def : WriteRes<WriteI,     [TSV110UnitALUAB]> { let Latency = 1; }
56def : WriteRes<WriteISReg, [TSV110UnitMDU]>   { let Latency = 2; }
57def : WriteRes<WriteIEReg, [TSV110UnitMDU]>   { let Latency = 2; }
58def : WriteRes<WriteExtr,  [TSV110UnitALUAB]> { let Latency = 1; }
59def : WriteRes<WriteIS,    [TSV110UnitALUAB]> { let Latency = 1; }
60
61// Integer Mul/MAC/Div
62def : WriteRes<WriteID32,  [TSV110UnitMDU]> { let Latency = 12;
63                                              let ResourceCycles = [12]; }
64def : WriteRes<WriteID64,  [TSV110UnitMDU]> { let Latency = 20;
65                                              let ResourceCycles = [20]; }
66def : WriteRes<WriteIM32,  [TSV110UnitMDU]> { let Latency = 3; }
67def : WriteRes<WriteIM64,  [TSV110UnitMDU]> { let Latency = 4; }
68
69// Load
70def : WriteRes<WriteLD,    [TSV110UnitLdSt]> { let Latency = 4; }
71def : WriteRes<WriteLDIdx, [TSV110UnitLdSt]> { let Latency = 4; }
72def : WriteRes<WriteLDHi,  []> { let Latency = 4; }
73
74// Pre/Post Indexing
75def : WriteRes<WriteAdr,   [TSV110UnitALUAB]> { let Latency = 1; }
76
77// Store
78def : WriteRes<WriteST,    [TSV110UnitLdSt]> { let Latency = 1; }
79def : WriteRes<WriteSTP,   [TSV110UnitLdSt]> { let Latency = 1; }
80def : WriteRes<WriteSTIdx, [TSV110UnitLdSt]> { let Latency = 1; }
81
82// FP
83def : WriteRes<WriteF,     [TSV110UnitF]> { let Latency = 2; }
84def : WriteRes<WriteFCmp,  [TSV110UnitF]> { let Latency = 3; }
85def : WriteRes<WriteFCvt,  [TSV110UnitF]> { let Latency = 3; }
86def : WriteRes<WriteFCopy, [TSV110UnitF]> { let Latency = 2; }
87def : WriteRes<WriteFImm,  [TSV110UnitF]> { let Latency = 2; }
88def : WriteRes<WriteFMul,  [TSV110UnitF]> { let Latency = 5; }
89
90// FP Div, Sqrt
91def : WriteRes<WriteFDiv,  [TSV110UnitFSU1]> { let Latency = 18; }
92
93def : WriteRes<WriteVd,    [TSV110UnitF]>     { let Latency = 4; }
94def : WriteRes<WriteVq,    [TSV110UnitF]>     { let Latency = 4; }
95def : WriteRes<WriteVLD,   [TSV110UnitFLdSt]> { let Latency = 5; }
96def : WriteRes<WriteVST,   [TSV110UnitF]>     { let Latency = 1; }
97
98// Branch
99def : WriteRes<WriteBr,    [TSV110UnitAB]> { let Latency = 1; }
100def : WriteRes<WriteBrReg, [TSV110UnitAB]> { let Latency = 1; }
101def : WriteRes<WriteSys,     []> { let Latency = 1; }
102def : WriteRes<WriteBarrier, []> { let Latency = 1; }
103def : WriteRes<WriteHint,    []> { let Latency = 1; }
104
105def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
106
107// Forwarding logic is modeled only for multiply and accumulate.
108def : ReadAdvance<ReadI,       0>;
109def : ReadAdvance<ReadISReg,   0>;
110def : ReadAdvance<ReadIEReg,   0>;
111def : ReadAdvance<ReadIM,      0>;
112def : ReadAdvance<ReadIMA,     2, [WriteIM32, WriteIM64]>;
113def : ReadAdvance<ReadID,      0>;
114def : ReadAdvance<ReadExtrHi,  0>;
115def : ReadAdvance<ReadAdrBase, 0>;
116def : ReadAdvance<ReadVLD,     0>;
117def : ReadAdvance<ReadST,      0>;
118
119def : InstRW<[WriteI], (instrs COPY)>;
120
121// Detailed Refinements
122//===----------------------------------------------------------------------===//
123
124// Contains all of the TSV110 specific SchedWriteRes types. The approach
125// below is to define a generic SchedWriteRes for every combination of
126// latency and microOps. The naming conventions is to use a prefix, one field
127// for latency, and one or more microOp count/type designators.
128//   Prefix: TSV110Wr
129//       Latency: #cyc
130//   MicroOp Count/Types: #(ALU|AB|MDU|FSU1|FSU2|LdSt|ALUAB|F|FLdSt)
131//
132// e.g. TSV110Wr_6cyc_1ALU_6MDU_4LdSt means the total latency is 6 and there are
133//      1 micro-ops to be issued down one ALU pipe, six MDU pipes and four LdSt pipes.
134//
135
136//===----------------------------------------------------------------------===//
137// Define Generic 1 micro-op types
138
139def TSV110Wr_1cyc_1AB    : SchedWriteRes<[TSV110UnitAB]>    { let Latency = 1; }
140def TSV110Wr_1cyc_1ALU   : SchedWriteRes<[TSV110UnitALU]>   { let Latency = 1; }
141def TSV110Wr_1cyc_1ALUAB : SchedWriteRes<[TSV110UnitALUAB]> { let Latency = 1; }
142def TSV110Wr_1cyc_1LdSt  : SchedWriteRes<[TSV110UnitLdSt]>  { let Latency = 1; }
143
144def TSV110Wr_2cyc_1AB    : SchedWriteRes<[TSV110UnitAB]>    { let Latency = 2; }
145def TSV110Wr_2cyc_1ALU   : SchedWriteRes<[TSV110UnitALU]>   { let Latency = 2; }
146def TSV110Wr_2cyc_1LdSt  : SchedWriteRes<[TSV110UnitLdSt]>  { let Latency = 2; }
147def TSV110Wr_2cyc_1MDU   : SchedWriteRes<[TSV110UnitMDU]>   { let Latency = 2; }
148def TSV110Wr_2cyc_1FSU1  : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 2; }
149def TSV110Wr_2cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 2; }
150
151def TSV110Wr_3cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 3; }
152def TSV110Wr_3cyc_1FSU1  : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 3; }
153def TSV110Wr_3cyc_1MDU   : SchedWriteRes<[TSV110UnitMDU]>   { let Latency = 3; }
154
155def TSV110Wr_4cyc_1FSU1  : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 4; }
156def TSV110Wr_4cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 4; }
157def TSV110Wr_4cyc_1LdSt  : SchedWriteRes<[TSV110UnitLdSt]>  { let Latency = 4; }
158def TSV110Wr_4cyc_1MDU   : SchedWriteRes<[TSV110UnitMDU]>   { let Latency = 4; }
159
160def TSV110Wr_5cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 5; }
161def TSV110Wr_5cyc_1FSU1  : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 5; }
162def TSV110Wr_5cyc_1FSU2  : SchedWriteRes<[TSV110UnitFSU2]>  { let Latency = 5; }
163def TSV110Wr_5cyc_1LdSt  : SchedWriteRes<[TSV110UnitLdSt]>  { let Latency = 5; }
164
165def TSV110Wr_6cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 6; }
166
167def TSV110Wr_7cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 7; }
168
169def TSV110Wr_8cyc_1F     : SchedWriteRes<[TSV110UnitF]>     { let Latency = 8; }
170
171def TSV110Wr_11cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 11; }
172
173def TSV110Wr_12cyc_1MDU  : SchedWriteRes<[TSV110UnitMDU]>   { let Latency = 12; }
174
175def TSV110Wr_17cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]>  { let Latency = 17; }
176
177def TSV110Wr_18cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 18; }
178
179def TSV110Wr_20cyc_1MDU  : SchedWriteRes<[TSV110UnitMDU]>   { let Latency = 20; }
180
181def TSV110Wr_24cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 24; }
182
183def TSV110Wr_31cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]>  { let Latency = 31; }
184
185def TSV110Wr_36cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]>  { let Latency = 36; }
186
187def TSV110Wr_38cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]>  { let Latency = 38; }
188
189def TSV110Wr_64cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]>  { let Latency = 64; }
190
191//===----------------------------------------------------------------------===//
192// Define Generic 2 micro-op types
193
194def TSV110Wr_1cyc_1LdSt_1ALUAB : SchedWriteRes<[TSV110UnitLdSt,
195                                                TSV110UnitALUAB]> {
196  let Latency = 1;
197  let NumMicroOps = 2;
198}
199
200def TSV110Wr_2cyc_1LdSt_1ALUAB :  SchedWriteRes<[TSV110UnitLdSt,
201                                                 TSV110UnitALUAB]> {
202  let Latency = 2;
203  let NumMicroOps = 2;
204}
205
206def TSV110Wr_2cyc_2LdSt        : SchedWriteRes<[TSV110UnitLdSt,
207                                                TSV110UnitLdSt]> {
208  let Latency = 2;
209  let NumMicroOps = 2;
210}
211
212def TSV110Wr_2cyc_2F           : SchedWriteRes<[TSV110UnitF,
213                                                TSV110UnitF]> {
214  let Latency = 2;
215  let NumMicroOps = 2;
216}
217
218def TSV110Wr_2cyc_1FSU1_1FSU2  : SchedWriteRes<[TSV110UnitFSU1,
219                                                TSV110UnitFSU2]> {
220  let Latency = 2;
221  let NumMicroOps = 2;
222}
223
224def TSV110Wr_4cyc_2F           : SchedWriteRes<[TSV110UnitF,
225                                                TSV110UnitF]> {
226  let Latency = 4;
227  let NumMicroOps = 2;
228}
229
230def TSV110Wr_4cyc_1FSU1_1FSU2  : SchedWriteRes<[TSV110UnitFSU1,
231                                                TSV110UnitFSU2]> {
232  let Latency = 4;
233  let NumMicroOps = 2;
234}
235
236def TSV110Wr_4cyc_1LdSt_1ALUAB : SchedWriteRes<[TSV110UnitLdSt,
237                                                TSV110UnitALUAB]> {
238  let Latency = 4;
239  let NumMicroOps = 2;
240}
241
242def TSV110Wr_5cyc_1ALU_1F      : SchedWriteRes<[TSV110UnitALU,
243                                                TSV110UnitF]> {
244  let Latency     = 5;
245  let NumMicroOps = 2;
246}
247
248def TSV110Wr_6cyc_2LdSt        : SchedWriteRes<[TSV110UnitLdSt,
249                                                TSV110UnitLdSt]> {
250  let Latency = 6;
251  let NumMicroOps = 2;
252}
253
254def TSV110Wr_6cyc_1LdSt_1ALUAB : SchedWriteRes<[TSV110UnitLdSt,
255                                                TSV110UnitALUAB]> {
256  let Latency = 6;
257  let NumMicroOps = 2;
258}
259
260def TSV110Wr_7cyc_1F_1LdSt     : SchedWriteRes<[TSV110UnitF,
261                                                TSV110UnitLdSt]> {
262  let Latency = 7;
263  let NumMicroOps = 2;
264}
265
266def TSV110Wr_8cyc_2FSU1        : SchedWriteRes<[TSV110UnitFSU1,
267                                                TSV110UnitFSU1]> {
268  let Latency = 8;
269  let NumMicroOps = 2;
270}
271
272
273def TSV110Wr_8cyc_1FSU1_1FSU2  : SchedWriteRes<[TSV110UnitFSU1,
274                                                TSV110UnitFSU2]> {
275  let Latency = 8;
276  let NumMicroOps = 2;
277}
278
279//===----------------------------------------------------------------------===//
280// Define Generic 3 micro-op types
281
282def TSV110Wr_6cyc_3F       : SchedWriteRes<[TSV110UnitF, TSV110UnitF,
283                                            TSV110UnitF]> {
284  let Latency     = 6;
285  let NumMicroOps = 3;
286}
287
288def TSV110Wr_6cyc_3LdSt    : SchedWriteRes<[TSV110UnitLdSt, TSV110UnitLdSt,
289                                            TSV110UnitLdSt]> {
290  let Latency = 6;
291  let NumMicroOps = 3;
292}
293
294def TSV110Wr_7cyc_2F_1LdSt : SchedWriteRes<[TSV110UnitF, TSV110UnitF,
295                                                         TSV110UnitLdSt]> {
296  let Latency = 7;
297  let NumMicroOps = 3;
298}
299
300//===----------------------------------------------------------------------===//
301// Define Generic 4 micro-op types
302
303def TSV110Wr_8cyc_4F          : SchedWriteRes<[TSV110UnitF, TSV110UnitF,
304                                               TSV110UnitF, TSV110UnitF]> {
305  let Latency = 8;
306  let NumMicroOps = 4;
307}
308
309def TSV110Wr_8cyc_3F_1LdSt    : SchedWriteRes<[TSV110UnitF, TSV110UnitF,
310                                               TSV110UnitF, TSV110UnitLdSt]> {
311  let Latency = 8;
312  let NumMicroOps = 4;
313}
314
315//===----------------------------------------------------------------------===//
316// Define Generic 5 micro-op types
317
318def TSV110Wr_8cyc_3F_2LdSt : SchedWriteRes<[TSV110UnitF, TSV110UnitF, TSV110UnitF,
319                                            TSV110UnitLdSt, TSV110UnitLdSt]> {
320  let Latency = 8;
321  let NumMicroOps = 5;
322}
323
324//===----------------------------------------------------------------------===//
325// Define Generic 8 micro-op types
326
327def TSV110Wr_10cyc_4F_4LdSt : SchedWriteRes<[TSV110UnitF, TSV110UnitF,
328                                             TSV110UnitF, TSV110UnitF,
329                                             TSV110UnitLdSt, TSV110UnitLdSt,
330                                             TSV110UnitLdSt, TSV110UnitLdSt]> {
331  let Latency = 10;
332  let NumMicroOps = 8;
333}
334
335
336// Branch Instructions
337// -----------------------------------------------------------------------------
338
339def : InstRW<[TSV110Wr_1cyc_1AB], (instrs B)>;
340def : InstRW<[TSV110Wr_1cyc_1AB], (instrs BL)>;
341def : InstRW<[TSV110Wr_1cyc_1AB], (instrs BLR)>;
342def : InstRW<[TSV110Wr_1cyc_1AB], (instregex "^(BR|RET|(CBZ|CBNZ|TBZ|TBNZ))$")>;
343
344
345// Cryptography Extensions
346// -----------------------------------------------------------------------------
347
348def : InstRW<[TSV110Wr_3cyc_1FSU1], (instregex "^AES[DE]")>;
349def : InstRW<[TSV110Wr_3cyc_1FSU1], (instregex "^AESI?MC")>;
350def : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^SHA1SU1")>;
351def : InstRW<[TSV110Wr_2cyc_2F],    (instregex "^SHA1(H|SU0)")>;
352def : InstRW<[TSV110Wr_5cyc_1FSU1], (instregex "^SHA1[CMP]")>;
353def : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^SHA256SU0")>;
354def : InstRW<[TSV110Wr_3cyc_1FSU1], (instregex "^SHA256SU1")>;
355def : InstRW<[TSV110Wr_5cyc_1FSU1], (instregex "^SHA256(H|H2)")>;
356def TSV110ReadCRC: SchedReadAdvance<1, [TSV110Wr_2cyc_1MDU]>;
357def : InstRW<[TSV110Wr_2cyc_1MDU, TSV110ReadCRC],  (instregex "^CRC32.*$")>;
358
359
360// Arithmetic and Logical Instructions
361// -----------------------------------------------------------------------------
362
363def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "(BIC|EON|ORN)[WX]rr")>;
364def : InstRW<[TSV110Wr_1cyc_1AB],    (instregex "(BIC)S[WX]rr")>;
365
366def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "(ADD|AND|EOR|ORR|SUB)[WX]r(r|i)")>;
367def : InstRW<[TSV110Wr_1cyc_1AB],    (instregex "(ADD|AND|EOR|ORR|SUB)S[WX]r(r|i)")>;
368
369def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(ADC|SBC|BIC)[WX]r$")>;
370def : InstRW<[TSV110Wr_1cyc_1AB],    (instregex "^(ADC|SBC)S[WX]r$")>;
371
372def : InstRW<[TSV110Wr_2cyc_1MDU],   (instregex "^(AND|BIC|EON|EOR|ORN|ORR)[WX]rs$")>;
373def : InstRW<[TSV110Wr_2cyc_1AB],    (instregex "^(AND|BIC|EON|EOR|ORN|ORR)S[WX]rs$")>;
374def : InstRW<[TSV110Wr_2cyc_1MDU],   (instregex "^(ADD|SUB)[WX]r(s|x|x64)$")>;
375def : InstRW<[TSV110Wr_2cyc_1AB],    (instregex "^(ADD|SUB)S[WX]r(s|x|x64)$")>;
376
377def : InstRW<[TSV110Wr_1cyc_1AB],    (instregex "^(CCMN|CCMP)(W|X)(r|i)$")>;
378def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
379
380
381// Move and Shift Instructions
382// -----------------------------------------------------------------------------
383
384def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instrs ADR, ADRP)>;
385def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^MOV[NZK][WX]i")>;
386def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "(LSLV|LSRV|ASRV|RORV)(W|X)r")>;
387
388
389// Divide and Multiply Instructions
390// -----------------------------------------------------------------------------
391
392def : InstRW<[TSV110Wr_12cyc_1MDU],  (instregex "^(S|U)DIVWr$")>;
393def : InstRW<[TSV110Wr_20cyc_1MDU],  (instregex "^(S|U)DIVXr$")>;
394
395def TSV110ReadMAW : SchedReadAdvance<2, [TSV110Wr_3cyc_1MDU]>;
396def : InstRW<[TSV110Wr_3cyc_1MDU, TSV110ReadMAW], (instrs MADDWrrr, MSUBWrrr)>;
397def TSV110ReadMAQ : SchedReadAdvance<3, [TSV110Wr_4cyc_1MDU]>;
398def : InstRW<[TSV110Wr_4cyc_1MDU, TSV110ReadMAQ], (instrs MADDXrrr, MSUBXrrr)>;
399def : InstRW<[TSV110Wr_3cyc_1MDU, TSV110ReadMAW], (instregex "(S|U)(MADDL|MSUBL)rrr")>;
400def : InstRW<[TSV110Wr_4cyc_1MDU], (instregex "^(S|U)MULHrr$")>;
401
402
403// Miscellaneous Data-Processing Instructions
404// -----------------------------------------------------------------------------
405
406def : InstRW<[TSV110Wr_1cyc_1ALUAB],    (instregex "^EXTR(W|X)rri$")>;
407def : InstRW<[TSV110Wr_1cyc_1ALUAB],    (instregex "^(S|U)?BFM(W|X)ri$")>;
408def : InstRW<[TSV110Wr_1cyc_1ALUAB],    (instregex "^(CLS|CLZ|RBIT|REV(16|32)?)(W|X)r$")>;
409
410
411// Load Instructions
412// -----------------------------------------------------------------------------
413
414def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^LDR(W|X)l$")>;
415def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instrs LDRSWl)>;
416
417def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^LDR(BB|HH|W|X)ui$")>;
418def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>;
419
420def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteAdr],     (instregex "^LDR(BB|HH|W|X)(post|pre)$")>;
421def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteAdr],     (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
422
423def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^LDTR(B|H|W|X)i$")>;
424def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^LDUR(BB|HH|W|X)i$")>;
425def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>;
426def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^LDURS(BW|BX|HW|HX|W)i$")>;
427
428def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteLDHi],     (instregex "^LDNP(W|X)i$")>;
429def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteLDHi],     (instregex "^LDP(W|X)i$")>;
430def : InstRW<[TSV110Wr_4cyc_1LdSt_1ALUAB, WriteLDHi, WriteAdr],(instregex "^LDP(W|X)(post|pre)$")>;
431
432def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteLDHi],           (instrs LDPSWi)>;
433def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteLDHi, WriteAdr], (instrs LDPSWpost)>;
434def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteLDHi, WriteAdr], (instrs LDPSWpre)>;
435
436def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instrs PRFMl)>;
437def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instrs PRFUMi)>;
438def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^PRFMui$")>;
439def : InstRW<[TSV110Wr_4cyc_1LdSt],     (instregex "^PRFMro(W|X)$")>;
440
441
442// Store Instructions
443// -----------------------------------------------------------------------------
444
445def : InstRW<[TSV110Wr_1cyc_1LdSt],            (instregex "^STN?P(W|X)i$")>;
446def : InstRW<[TSV110Wr_1cyc_1LdSt, WriteAdr],  (instregex "^STP(W|X)(post|pre)$")>;
447def : InstRW<[TSV110Wr_1cyc_1LdSt],            (instregex "^STUR(BB|HH|W|X)i$")>;
448def : InstRW<[TSV110Wr_1cyc_1LdSt],            (instregex "^STTR(B|H|W|X)i$")>;
449def : InstRW<[TSV110Wr_1cyc_1LdSt],            (instregex "^STR(BB|HH|W|X)ui$")>;
450
451def : InstRW<[TSV110Wr_1cyc_1LdSt, WriteAdr],  (instregex "^STR(BB|HH|W|X)(post|pre)$")>;
452def : InstRW<[TSV110Wr_1cyc_1LdSt, WriteAdr],  (instregex "^STR(BB|HH|W|X)ro(W|X)$")>;
453
454
455// FP Data Processing Instructions
456// -----------------------------------------------------------------------------
457
458def : InstRW<[TSV110Wr_2cyc_1F], (instregex "F(ABS|NEG)(D|S)r")>;
459def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FCCMP(E)?(S|D)rr$")>;
460def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FCMP(E)?(S|D)r(r|i)$")>;
461def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FCSEL(S|D)rrr$")>;
462
463def : InstRW<[TSV110Wr_11cyc_1FSU1], (instrs FDIVSrr)>;
464def : InstRW<[TSV110Wr_18cyc_1FSU1], (instrs FDIVDrr)>;
465def : InstRW<[TSV110Wr_17cyc_1FSU2], (instrs FSQRTSr)>;
466def : InstRW<[TSV110Wr_31cyc_1FSU2], (instrs FSQRTDr)>;
467
468def : InstRW<[TSV110Wr_2cyc_1F], (instregex "^F(MAX|MIN).+rr")>;
469
470def : InstRW<[TSV110Wr_4cyc_1F], (instregex "^FN?M(ADD|SUB)Hrrr")>;
471def : InstRW<[TSV110Wr_5cyc_1F], (instregex "^FN?M(ADD|SUB)Srrr")>;
472def : InstRW<[TSV110Wr_7cyc_1F], (instregex "^FN?M(ADD|SUB)Drrr")>;
473
474def : InstRW<[TSV110Wr_4cyc_1F], (instregex "^F(ADD|SUB)Hrr")>;
475def : InstRW<[TSV110Wr_5cyc_1F], (instregex "^F(ADD|SUB)Srr")>;
476def : InstRW<[TSV110Wr_4cyc_1F], (instregex "^F(ADD|SUB)Drr")>;
477
478def : InstRW<[TSV110Wr_4cyc_1F], (instregex "^F(N)?MULHrr$")>;
479def : InstRW<[TSV110Wr_5cyc_1F], (instregex "^F(N)?MULSrr$")>;
480def : InstRW<[TSV110Wr_5cyc_1F], (instregex "^F(N)?MULDrr$")>;
481
482def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FRINT.+r")>;
483
484
485// FP Miscellaneous Instructions
486// -----------------------------------------------------------------------------
487
488def : InstRW<[TSV110Wr_5cyc_1ALU_1F], (instregex "^[SU]CVTF[SU][WX][SD]ri")>;
489def : InstRW<[TSV110Wr_4cyc_1FSU1],   (instregex "^FCVT(A|M|N|P|Z)(S|U)U(W|X)(S|D)r$")>;
490def : InstRW<[TSV110Wr_3cyc_1F],      (instregex "^FCVT[HSD][HSD]r")>;
491
492def : InstRW<[TSV110Wr_2cyc_1FSU1],   (instregex "^FMOV(DX|WS|XD|SW|DXHigh|XDHigh)r$")>;
493def : InstRW<[TSV110Wr_2cyc_1F],      (instregex "^FMOV[SD][ir]$")>;
494
495
496// FP Load Instructions
497// -----------------------------------------------------------------------------
498
499def : InstRW<[TSV110Wr_5cyc_1LdSt],                      (instregex "^LDR[DSQ]l")>;
500def : InstRW<[TSV110Wr_5cyc_1LdSt],                      (instregex "^LDUR[BDHSQ]i")>;
501def : InstRW<[TSV110Wr_5cyc_1LdSt, WriteAdr],            (instregex "^LDR[BDHSQ](post|pre)")>;
502def : InstRW<[TSV110Wr_5cyc_1LdSt],                      (instregex "^LDR[BDHSQ]ui")>;
503def : InstRW<[TSV110Wr_6cyc_1LdSt_1ALUAB, ReadAdrBase],  (instregex "^LDR(Q|D|H|S|B)ro(W|X)$")>;
504def : InstRW<[TSV110Wr_5cyc_1LdSt, WriteLDHi],           (instregex "^LDN?P[DQS]i")>;
505def : InstRW<[TSV110Wr_5cyc_1LdSt, WriteLDHi, WriteAdr], (instregex "^LDP[DQS](post|pre)")>;
506
507
508// FP Store Instructions
509// -----------------------------------------------------------------------------
510
511def : InstRW<[TSV110Wr_1cyc_1LdSt],                     (instregex "^STUR[BHSDQ]i")>;
512def : InstRW<[TSV110Wr_1cyc_1LdSt_1ALUAB, ReadAdrBase], (instregex "^STR[BHSDQ](post|pre)")>;
513def : InstRW<[TSV110Wr_1cyc_1LdSt],                     (instregex "^STR[BHSDQ]ui")>;
514def : InstRW<[TSV110Wr_2cyc_1LdSt_1ALUAB, ReadAdrBase], (instregex "^STR[BHSDQ]ro[WX]")>;
515def : InstRW<[TSV110Wr_2cyc_2LdSt],                     (instregex "^STN?P[SDQ]i")>;
516def : InstRW<[TSV110Wr_2cyc_2LdSt, WriteAdr],           (instregex "^STP[SDQ](post|pre)")>;
517
518
519// ASIMD Integer Instructions
520// -----------------------------------------------------------------------------
521
522// Reference for forms in this group
523//   D form - v8i8, v4i16, v2i32
524//   Q form - v16i8, v8i16, v4i32
525//   D form - v1i8, v1i16, v1i32, v1i64
526//   Q form - v16i8, v8i16, v4i32, v2i64
527//   D form - v8i8_v8i16, v4i16_v4i32, v2i32_v2i64
528//   Q form - v16i8_v8i16, v8i16_v4i32, v4i32_v2i64
529
530// ASIMD simple arithmetic
531def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(ABS|ADD(P)?|NEG|SUB)v")>;
532def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^[SU](ADD(L|LP|W)|SUB(L|W))v")>;
533
534// ASIMD complex arithmetic
535def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]H(ADD|SUB)v")>;
536def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^R?(ADD|SUB)HN2?v")>;
537def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]Q(ADD|SUB)v")>;
538def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^(SU|US)QADDv")>;
539def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]RHADDv")>;
540def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]ABAL?v")>;
541def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]ABDL?v")>;
542def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]ADALPv")>;
543def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^((SQ)(ABS|NEG))v")>;
544
545// ASIMD compare
546def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT|TST)v")>;
547
548// ASIMD max/min
549def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^[SU](MIN|MAX)P?v")>;
550
551// ASIMD logical
552def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(AND|BIC|BIF|BIT|BSL|EOR|MVN|NOT|ORN|ORR)v")>;
553
554// ASIMD multiply accumulate, D-form
555def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^(MUL|ML[AS]|SQR?D(MULH))(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)")>;
556// ASIMD multiply accumulate, Q-form
557def : InstRW<[TSV110Wr_8cyc_2FSU1], (instregex "^(MUL|ML[AS]|SQR?D(MULH))(v16i8|v8i16|v4i32)")>;
558
559// ASIMD multiply accumulate long
560def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "(S|U|SQD)(MLAL|MLSL|MULL)v.*")>;
561def : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^PMULL(v8i8|v16i8)")>;
562def : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^PMULL(v1i64|v2i64)")>;
563
564// ASIMD shift
565// ASIMD shift accumulate
566def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^(S|SR|U|UR)SRA")>;
567// ASIMD shift by immed, basic
568def : InstRW<[TSV110Wr_4cyc_1FSU1],
569            (instregex "SHLv","SLIv","SRIv","SHRNv","SQXTNv","SQXTUNv","UQXTNv")>;
570// ASIMD shift by immed, complex
571def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^[SU]?(Q|R){1,2}SHR")>;
572def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^SQSHLU")>;
573// ASIMD shift by register, basic, Q-form
574def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>;
575// ASIMD shift by register, complex, D-form
576def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
577// ASIMD shift by register, complex, Q-form
578def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i64)")>;
579
580// ASIMD reduction
581// ASIMD arith, reduce, 4H/4S
582def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
583// ASIMD arith, reduce, 8B/8H
584def : InstRW<[TSV110Wr_8cyc_1FSU1_1FSU2], (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>;
585// ASIMD arith, reduce, 16B
586def : InstRW<[TSV110Wr_8cyc_1FSU1_1FSU2], (instregex "^[SU]?ADDL?Vv16i8v$")>;
587
588// ASIMD max/min, reduce, 4H/4S
589def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v$")>;
590// ASIMD max/min, reduce, 8B/8H
591def : InstRW<[TSV110Wr_8cyc_1FSU1_1FSU2], (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>;
592// ASIMD max/min, reduce, 16B
593def : InstRW<[TSV110Wr_8cyc_1FSU1_1FSU2], (instregex "^[SU](MIN|MAX)Vv16i8v$")>;
594
595
596// Vector - Floating Point
597// -----------------------------------------------------------------------------
598
599// Reference for forms in this group
600//   D form - v2f32
601//   Q form - v4f32, v2f64
602//   D form - 32, 64
603//   D form - v1i32, v1i64
604//   D form - v2i32
605//   Q form - v4i32, v2i64
606
607// ASIMD FP sign manipulation
608def : InstRW<[TSV110Wr_2cyc_1F],  (instregex "^FABSv")>;
609def : InstRW<[TSV110Wr_2cyc_1F],  (instregex "^FNEGv")>;
610
611// ASIMD FP compare
612def : InstRW<[TSV110Wr_2cyc_1F],  (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v")>;
613
614// ASIMD FP convert
615def : InstRW<[TSV110Wr_2cyc_1F],  (instregex "^FCVT[AMNPZ][SU]v")>;
616def : InstRW<[TSV110Wr_3cyc_1F],  (instregex "^FCVT(L)v")>;
617def : InstRW<[TSV110Wr_5cyc_1F],  (instregex "^FCVT(N|XN)v")>;
618
619// ASIMD FP divide, D-form, F32
620def : InstRW<[TSV110Wr_11cyc_1FSU1], (instregex "FDIVv2f32")>;
621// ASIMD FP divide, Q-form, F32
622def : InstRW<[TSV110Wr_24cyc_1FSU1], (instregex "FDIVv4f32")>;
623// ASIMD FP divide, Q-form, F64
624def : InstRW<[TSV110Wr_38cyc_1FSU1], (instregex "FDIVv2f64")>;
625
626// ASIMD FP SQRT
627def : InstRW<[TSV110Wr_17cyc_1FSU2], (instrs FSQRTv2f32)>;
628def : InstRW<[TSV110Wr_36cyc_1FSU2], (instrs FSQRTv4f32)>;
629def : InstRW<[TSV110Wr_64cyc_1FSU2], (instrs FSQRTv2f64)>;
630
631// ASIMD FP max,min
632def : InstRW<[TSV110Wr_2cyc_1F],  (instregex "^F(MAX|MIN)(NM)?v")>;
633def : InstRW<[TSV110Wr_2cyc_1F],  (instregex "^F(MAX|MIN)(NM)?Pv")>;
634def : InstRW<[TSV110Wr_4cyc_1F],  (instregex "^F(MAX|MIN)(NM)?Vv")>;
635
636// ASIMD FP add
637def : InstRW<[TSV110Wr_5cyc_1F],  (instregex "^F(ADD|ADDP|SUB)v")>;
638
639// ASIMD FP multiply
640def : InstRW<[TSV110Wr_5cyc_1F],  (instregex "^FMULX?v")>;
641
642
643// ASIMD Miscellaneous Instructions
644// -----------------------------------------------------------------------------
645
646def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(CLS|CLZ|CNT)v")>;
647def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(DUP|INS)v.+lane")>;
648def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^REV(16|32|64)v")>;
649def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(UZP|ZIP)[12]v")>;
650
651def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^EXTv")>;
652def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^XTNv")>;
653def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^RBITv")>;
654
655def : InstRW<[TSV110Wr_4cyc_1F], (instregex "^(INS|DUP)v.+gpr")>;
656
657def : InstRW<[TSV110Wr_3cyc_1FSU1], (instregex "^[SU]MOVv")>;
658
659// ASIMD table lookup, D-form
660def : InstRW<[TSV110Wr_2cyc_1F], (instregex "^TB[LX]v8i8One")>;
661def : InstRW<[TSV110Wr_4cyc_2F], (instregex "^TB[LX]v8i8Two")>;
662def : InstRW<[TSV110Wr_6cyc_3F], (instregex "^TB[LX]v8i8Three")>;
663def : InstRW<[TSV110Wr_8cyc_4F], (instregex "^TB[LX]v8i8Four")>;
664// ASIMD table lookup, Q-form
665def : InstRW<[TSV110Wr_2cyc_1F], (instregex "^TB[LX]v16i8One")>;
666def : InstRW<[TSV110Wr_4cyc_2F], (instregex "^TB[LX]v16i8Two")>;
667def : InstRW<[TSV110Wr_6cyc_3F], (instregex "^TB[LX]v16i8Three")>;
668def : InstRW<[TSV110Wr_8cyc_4F], (instregex "^TB[LX]v16i8Four")>;
669
670def : InstRW<[TSV110Wr_2cyc_1F], (instregex "^FMOVv")>;
671
672def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FRINT[AIMNPXZ]v")>;
673def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^[SU]CVTFv")>;
674def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^[FU](RECP|RSQRT)(E|X)v")>;
675
676
677// ASIMD Load Instructions
678// -----------------------------------------------------------------------------
679
680def : InstRW<[TSV110Wr_7cyc_1F_1LdSt],            (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
681def : InstRW<[TSV110Wr_7cyc_1F_1LdSt, WriteAdr],  (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
682def : InstRW<[TSV110Wr_7cyc_2F_1LdSt],            (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
683def : InstRW<[TSV110Wr_7cyc_2F_1LdSt, WriteAdr],  (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
684def : InstRW<[TSV110Wr_8cyc_3F_1LdSt],            (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
685def : InstRW<[TSV110Wr_8cyc_3F_1LdSt, WriteAdr],  (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
686def : InstRW<[TSV110Wr_8cyc_3F_2LdSt],            (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
687def : InstRW<[TSV110Wr_8cyc_3F_2LdSt, WriteAdr],  (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
688
689def  : InstRW<[TSV110Wr_7cyc_1F_1LdSt],           (instregex "LD1i(8|16|32|64)$")>;
690def  : InstRW<[TSV110Wr_7cyc_1F_1LdSt, WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>;
691def  : InstRW<[TSV110Wr_7cyc_2F_1LdSt],           (instregex "LD2i(8|16|32|64)$")>;
692def  : InstRW<[TSV110Wr_7cyc_2F_1LdSt, WriteAdr], (instregex "LD2i(8|16|32|64)_POST$")>;
693def  : InstRW<[TSV110Wr_8cyc_3F_1LdSt],           (instregex "LD3i(8|16|32|64)$")>;
694def  : InstRW<[TSV110Wr_8cyc_3F_1LdSt, WriteAdr], (instregex "LD3i(8|16|32|64)_POST$")>;
695def  : InstRW<[TSV110Wr_8cyc_3F_2LdSt],           (instregex "LD4i(8|16|32|64)$")>;
696def  : InstRW<[TSV110Wr_8cyc_3F_2LdSt, WriteAdr], (instregex "LD4i(8|16|32|64)_POST$")>;
697
698def : InstRW<[TSV110Wr_5cyc_1LdSt],               (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
699def : InstRW<[TSV110Wr_5cyc_1LdSt, WriteAdr],     (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
700def : InstRW<[TSV110Wr_5cyc_1LdSt],               (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
701def : InstRW<[TSV110Wr_5cyc_1LdSt, WriteAdr],     (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
702def : InstRW<[TSV110Wr_6cyc_3LdSt],               (instregex "^LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
703def : InstRW<[TSV110Wr_6cyc_3LdSt, WriteAdr],     (instregex "^LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
704def : InstRW<[TSV110Wr_6cyc_2LdSt],               (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
705def : InstRW<[TSV110Wr_6cyc_2LdSt, WriteAdr],     (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
706
707def : InstRW<[TSV110Wr_7cyc_2F_1LdSt],            (instregex "^LD2Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
708def : InstRW<[TSV110Wr_7cyc_2F_1LdSt, WriteAdr],  (instregex "^LD2Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
709
710def : InstRW<[TSV110Wr_8cyc_3F_1LdSt],            (instregex "^LD3Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
711def : InstRW<[TSV110Wr_8cyc_3F_1LdSt, WriteAdr],  (instregex "^LD3Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
712
713def : InstRW<[TSV110Wr_10cyc_4F_4LdSt],           (instregex "^LD4Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
714def : InstRW<[TSV110Wr_10cyc_4F_4LdSt, WriteAdr], (instregex "^LD4Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
715
716
717// ASIMD Store Instructions
718// -----------------------------------------------------------------------------
719
720def  : InstRW<[TSV110Wr_3cyc_1F],             (instregex "ST1i(8|16|32|64)$")>;
721def  : InstRW<[TSV110Wr_3cyc_1F, WriteAdr],   (instregex "ST1i(8|16|32|64)_POST$")>;
722def  : InstRW<[TSV110Wr_4cyc_1F],             (instregex "ST2i(8|16|32|64)$")>;
723def  : InstRW<[TSV110Wr_4cyc_1F, WriteAdr],   (instregex "ST2i(8|16|32|64)_POST$")>;
724def  : InstRW<[TSV110Wr_5cyc_1F],             (instregex "ST3i(8|16|32|64)$")>;
725def  : InstRW<[TSV110Wr_5cyc_1F, WriteAdr],   (instregex "ST3i(8|16|32|64)_POST$")>;
726def  : InstRW<[TSV110Wr_6cyc_1F],             (instregex "ST4i(8|16|32|64)$")>;
727def  : InstRW<[TSV110Wr_6cyc_1F, WriteAdr],   (instregex "ST4i(8|16|32|64)_POST$")>;
728
729def : InstRW<[TSV110Wr_3cyc_1F],              (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
730def : InstRW<[TSV110Wr_3cyc_1F, WriteAdr],    (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
731def : InstRW<[TSV110Wr_4cyc_1F],              (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
732def : InstRW<[TSV110Wr_4cyc_1F, WriteAdr],    (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
733def : InstRW<[TSV110Wr_5cyc_1F],              (instregex "^ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
734def : InstRW<[TSV110Wr_5cyc_1F, WriteAdr],    (instregex "^ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
735def : InstRW<[TSV110Wr_6cyc_1F],              (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
736def : InstRW<[TSV110Wr_6cyc_1F, WriteAdr],    (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
737
738def : InstRW<[TSV110Wr_4cyc_1F],              (instregex "^ST2Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
739def : InstRW<[TSV110Wr_4cyc_1F, WriteAdr],    (instregex "^ST2Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
740
741def : InstRW<[TSV110Wr_5cyc_1F],              (instregex "^ST3Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
742def : InstRW<[TSV110Wr_5cyc_1F, WriteAdr],    (instregex "^ST3Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
743
744def : InstRW<[TSV110Wr_8cyc_1F],              (instregex "^ST4Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
745def : InstRW<[TSV110Wr_8cyc_1F, WriteAdr],    (instregex "^ST4Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
746
747} // SchedModel = TSV110Model
748