1//==- AArch64SchedKryo.td - Qualcomm Kryo Scheduling Defs ---*- tablegen -*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Qualcomm Kryo to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// The issue width is set to five, matching the five issue queues for expanded 16// uops. Now, the latency spreadsheet has information based on fragmented uops, 17// but these do not actually take up an issue queue. 18 19def KryoModel : SchedMachineModel { 20 let IssueWidth = 5; // 5-wide issue for expanded uops 21 let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer 22 let LoadLatency = 4; // Optimistic load latency 23 let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch 24 25 // Enable partial & runtime unrolling. The magic number is chosen based on 26 // experiments and benchmarking data. 27 let LoopMicroOpBufferSize = 16; 28 let CompleteModel = 1; 29 30 list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F, 31 PAUnsupported.F); 32 // FIXME: Remove when all errors have been fixed. 33 let FullInstRWOverlapCheck = 0; 34} 35 36//===----------------------------------------------------------------------===// 37// Define each kind of processor resource and number available on Kryo. 38 39let SchedModel = KryoModel in { 40 def KryoUnitXA : ProcResource<1>; // Type X(A) micro-ops 41 def KryoUnitXB : ProcResource<1>; // Type X(B) micro-ops 42 def KryoUnitYA : ProcResource<1>; // Type Y(A) micro-ops 43 def KryoUnitYB : ProcResource<1>; // Type Y(B) micro-ops 44 def KryoUnitX : ProcResGroup<[KryoUnitXA, // Type X micro-ops 45 KryoUnitXB]>; 46 def KryoUnitY : ProcResGroup<[KryoUnitYA, // Type Y micro-ops 47 KryoUnitYB]>; 48 def KryoUnitXY : ProcResGroup<[KryoUnitXA, // Type XY micro-ops 49 KryoUnitXB, 50 KryoUnitYA, 51 KryoUnitYB]>; 52 def KryoUnitLSA : ProcResource<1>; // Type LS(A) micro-ops 53 def KryoUnitLSB : ProcResource<1>; // Type LS(B) micro-ops 54 def KryoUnitLS : ProcResGroup<[KryoUnitLSA, // Type LS micro-ops 55 KryoUnitLSB]>; 56} 57 58let SchedModel = KryoModel in { 59 60//===----------------------------------------------------------------------===// 61// Map the target-defined scheduler read/write resources and latency for 62// Kryo. 63 64def : WriteRes<WriteImm, [KryoUnitXY]> { let Latency = 1; } 65def : WriteRes<WriteI, [KryoUnitXY]> { let Latency = 1; } 66def : WriteRes<WriteISReg, [KryoUnitXY, KryoUnitXY]> 67 { let Latency = 2; let NumMicroOps = 2; } 68def : WriteRes<WriteIEReg, [KryoUnitXY, KryoUnitXY]> 69 { let Latency = 2; let NumMicroOps = 2; } 70def : WriteRes<WriteExtr, [KryoUnitXY, KryoUnitX]> 71 { let Latency = 2; let NumMicroOps = 2; } 72def : WriteRes<WriteIS, [KryoUnitXY]> { let Latency = 2; } 73def : WriteRes<WriteID32, [KryoUnitXA, KryoUnitY]> 74 { let Latency = 8; let NumMicroOps = 1; } // Fragent -1 75def : WriteRes<WriteID64, [KryoUnitXA, KryoUnitY]> 76 { let Latency = 8; let NumMicroOps = 1; } // Fragent -1 77def : WriteRes<WriteIM32, [KryoUnitX]> { let Latency = 5; } 78def : WriteRes<WriteIM64, [KryoUnitX]> { let Latency = 5; } 79def : WriteRes<WriteBr, [KryoUnitXY]> { let Latency = 1; } 80def : WriteRes<WriteBrReg, [KryoUnitXY]> { let Latency = 1; } 81def : WriteRes<WriteLD, [KryoUnitLS]> { let Latency = 4; } 82def : WriteRes<WriteST, [KryoUnitLS]> { let Latency = 4; } 83def : WriteRes<WriteSTP, [KryoUnitLS]> { let Latency = 4; } 84def : WriteRes<WriteAdr, [KryoUnitXY]> { let Latency = 6; } 85def : WriteRes<WriteLDIdx, [KryoUnitLS]> { let Latency = 4; } 86def : WriteRes<WriteSTIdx, [KryoUnitLS]> { let Latency = 4; } 87def : WriteRes<WriteF, [KryoUnitXY, KryoUnitXY]> 88 { let Latency = 3; let NumMicroOps = 2; } 89def : WriteRes<WriteFCmp, [KryoUnitXY]> { let Latency = 2; } 90def : WriteRes<WriteFCvt, [KryoUnitX]> { let Latency = 4; } 91def : WriteRes<WriteFCopy, [KryoUnitXY]> { let Latency = 6; } 92def : WriteRes<WriteFImm, [KryoUnitXY]> { let Latency = 6; } 93def : WriteRes<WriteFMul, [KryoUnitX, KryoUnitX]> 94 { let Latency = 6; let NumMicroOps = 2; } 95def : WriteRes<WriteFDiv, [KryoUnitXA, KryoUnitY]> 96 { let Latency = 12; let NumMicroOps = 2; } // Fragent -1 / NoRSV +1 97def : WriteRes<WriteV, [KryoUnitXY]> { let Latency = 6; } 98def : WriteRes<WriteVLD, [KryoUnitLS]> { let Latency = 4; } 99def : WriteRes<WriteVST, [KryoUnitLS]> { let Latency = 4; } 100 101def : WriteRes<WriteSys, []> { let Latency = 1; } 102def : WriteRes<WriteBarrier, []> { let Latency = 1; } 103def : WriteRes<WriteHint, []> { let Latency = 1; } 104 105def : WriteRes<WriteLDHi, []> { let Latency = 4; } 106 107def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 108 109// No forwarding logic is modelled yet. 110def : ReadAdvance<ReadI, 0>; 111def : ReadAdvance<ReadISReg, 0>; 112def : ReadAdvance<ReadIEReg, 0>; 113def : ReadAdvance<ReadIM, 0>; 114def : ReadAdvance<ReadIMA, 0>; 115def : ReadAdvance<ReadID, 0>; 116def : ReadAdvance<ReadExtrHi, 0>; 117def : ReadAdvance<ReadAdrBase, 0>; 118def : ReadAdvance<ReadVLD, 0>; 119 120 121//===----------------------------------------------------------------------===// 122// Specialize the coarse model by associating instruction groups with the 123// subtarget-defined types. As the modeled is refined, this will override most 124// of the above SchedWriteRes and SchedAlias mappings. 125 126// Miscellaneous 127// ----------------------------------------------------------------------------- 128 129def : InstRW<[WriteI], (instrs COPY)>; 130 131 132// Detailed Refinedments 133// ----------------------------------------------------------------------------- 134include "AArch64SchedKryoDetails.td" 135 136 137} // SchedModel = KryoModel 138