1//==- AArch64SchedFalkor.td - Falkor Scheduling Definitions -*- tablegen -*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Qualcomm Falkor to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Define the SchedMachineModel and provide basic properties for coarse grained 16// instruction cost model. 17 18def FalkorModel : SchedMachineModel { 19 let IssueWidth = 8; // 8 uops are dispatched per cycle. 20 let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer. 21 let LoopMicroOpBufferSize = 16; 22 let LoadLatency = 3; // Optimistic load latency. 23 let MispredictPenalty = 11; // Minimum branch misprediction penalty. 24 let CompleteModel = 1; 25 26 list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F, 27 PAUnsupported.F, 28 SMEUnsupported.F); 29 // FIXME: Remove when all errors have been fixed. 30 let FullInstRWOverlapCheck = 0; 31} 32 33//===----------------------------------------------------------------------===// 34// Define each kind of processor resource and number available on Falkor. 35 36let SchedModel = FalkorModel in { 37 38 def FalkorUnitB : ProcResource<1>; // Branch 39 def FalkorUnitLD : ProcResource<1>; // Load pipe 40 def FalkorUnitSD : ProcResource<1>; // Store data 41 def FalkorUnitST : ProcResource<1>; // Store pipe 42 def FalkorUnitX : ProcResource<1>; // Complex arithmetic 43 def FalkorUnitY : ProcResource<1>; // Simple arithmetic 44 def FalkorUnitZ : ProcResource<1>; // Simple arithmetic 45 46 def FalkorUnitVSD : ProcResource<1>; // Vector store data 47 def FalkorUnitVX : ProcResource<1>; // Vector X-pipe 48 def FalkorUnitVY : ProcResource<1>; // Vector Y-pipe 49 50 def FalkorUnitGTOV : ProcResource<1>; // Scalar to Vector 51 def FalkorUnitVTOG : ProcResource<1>; // Vector to Scalar 52 53 // Define the resource groups. 54 def FalkorUnitXY : ProcResGroup<[FalkorUnitX, FalkorUnitY]>; 55 def FalkorUnitXYZ : ProcResGroup<[FalkorUnitX, FalkorUnitY, FalkorUnitZ]>; 56 def FalkorUnitXYZB : ProcResGroup<[FalkorUnitX, FalkorUnitY, FalkorUnitZ, 57 FalkorUnitB]>; 58 def FalkorUnitZB : ProcResGroup<[FalkorUnitZ, FalkorUnitB]>; 59 def FalkorUnitVXVY : ProcResGroup<[FalkorUnitVX, FalkorUnitVY]>; 60 61} 62 63//===----------------------------------------------------------------------===// 64// Map the target-defined scheduler read/write resources and latency for 65// Falkor. 66 67let SchedModel = FalkorModel in { 68 69// These WriteRes entries are not used in the Falkor sched model. 70def : WriteRes<WriteImm, []> { let Unsupported = 1; } 71def : WriteRes<WriteI, []> { let Unsupported = 1; } 72def : WriteRes<WriteISReg, []> { let Unsupported = 1; } 73def : WriteRes<WriteIEReg, []> { let Unsupported = 1; } 74def : WriteRes<WriteExtr, []> { let Unsupported = 1; } 75def : WriteRes<WriteIS, []> { let Unsupported = 1; } 76def : WriteRes<WriteID32, []> { let Unsupported = 1; } 77def : WriteRes<WriteID64, []> { let Unsupported = 1; } 78def : WriteRes<WriteIM32, []> { let Unsupported = 1; } 79def : WriteRes<WriteIM64, []> { let Unsupported = 1; } 80def : WriteRes<WriteBr, []> { let Unsupported = 1; } 81def : WriteRes<WriteBrReg, []> { let Unsupported = 1; } 82def : WriteRes<WriteLD, []> { let Unsupported = 1; } 83def : WriteRes<WriteST, []> { let Unsupported = 1; } 84def : WriteRes<WriteSTP, []> { let Unsupported = 1; } 85def : WriteRes<WriteAdr, []> { let Unsupported = 1; } 86def : WriteRes<WriteLDIdx, []> { let Unsupported = 1; } 87def : WriteRes<WriteSTIdx, []> { let Unsupported = 1; } 88def : WriteRes<WriteF, []> { let Unsupported = 1; } 89def : WriteRes<WriteFCmp, []> { let Unsupported = 1; } 90def : WriteRes<WriteFCvt, []> { let Unsupported = 1; } 91def : WriteRes<WriteFCopy, []> { let Unsupported = 1; } 92def : WriteRes<WriteFImm, []> { let Unsupported = 1; } 93def : WriteRes<WriteFMul, []> { let Unsupported = 1; } 94def : WriteRes<WriteFDiv, []> { let Unsupported = 1; } 95def : WriteRes<WriteV, []> { let Unsupported = 1; } 96def : WriteRes<WriteVLD, []> { let Unsupported = 1; } 97def : WriteRes<WriteVST, []> { let Unsupported = 1; } 98def : WriteRes<WriteSys, []> { let Unsupported = 1; } 99def : WriteRes<WriteBarrier, []> { let Unsupported = 1; } 100def : WriteRes<WriteHint, []> { let Unsupported = 1; } 101def : WriteRes<WriteLDHi, []> { let Unsupported = 1; } 102def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 103 104// These ReadAdvance entries are not used in the Falkor sched model. 105def : ReadAdvance<ReadI, 0>; 106def : ReadAdvance<ReadISReg, 0>; 107def : ReadAdvance<ReadIEReg, 0>; 108def : ReadAdvance<ReadIM, 0>; 109def : ReadAdvance<ReadIMA, 0>; 110def : ReadAdvance<ReadID, 0>; 111def : ReadAdvance<ReadExtrHi, 0>; 112def : ReadAdvance<ReadAdrBase, 0>; 113def : ReadAdvance<ReadVLD, 0>; 114 115// Detailed Refinements 116// ----------------------------------------------------------------------------- 117include "AArch64SchedFalkorDetails.td" 118 119} 120