xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td (revision 95eb4b873b6a8b527c5bd78d7191975dfca38998)
1//=- AArch64SchedExynosM5.td - Samsung Exynos M5 Sched Defs --*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the machine model for the Samsung Exynos M5 to support
10// instruction scheduling and other instruction cost heuristics.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// The Exynos-M5 is an advanced superscalar microprocessor with a 6-wide
16// in-order stage for decode and dispatch and a wider issue stage.
17// The execution units and loads and stores are out-of-order.
18
19def ExynosM5Model : SchedMachineModel {
20  let IssueWidth            =   6; // Up to 6 uops per cycle.
21  let MicroOpBufferSize     = 228; // ROB size.
22  let LoopMicroOpBufferSize =  60; // Based on the instruction queue size.
23  let LoadLatency           =   4; // Optimistic load cases.
24  let MispredictPenalty     =  15; // Minimum branch misprediction penalty.
25  let CompleteModel         =   1; // Use the default model otherwise.
26
27  list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
28                                                    PAUnsupported.F,
29                                                    SMEUnsupported.F,
30                                                    [HasMTE, HasCSSC]);
31}
32
33//===----------------------------------------------------------------------===//
34// Define each kind of processor resource and number available on the Exynos-M5.
35
36let SchedModel = ExynosM5Model in {
37
38def M5UnitA  : ProcResource<2>; // Simple integer
39def M5UnitC  : ProcResource<2>; // Simple and complex integer
40let Super =  M5UnitC, BufferSize = 1 in
41def M5UnitD  : ProcResource<1>; // Integer division (inside C0, serialized)
42def M5UnitE  : ProcResource<2>; // Simple 32-bit integer
43let Super =  M5UnitC in
44def M5UnitF  : ProcResource<2>; // CRC (inside C)
45def M5UnitB  : ProcResource<1>; // Branch
46def M5UnitL0 : ProcResource<1>; // Load
47def M5UnitS0 : ProcResource<1>; // Store
48def M5PipeLS : ProcResource<1>; // Load/Store
49let Super = M5PipeLS in {
50  def M5UnitL1 : ProcResource<1>;
51  def M5UnitS1 : ProcResource<1>;
52}
53def M5PipeF0 : ProcResource<1>; // FP #0
54let Super = M5PipeF0 in {
55  def M5UnitFMAC0 : ProcResource<1>; // FP multiplication
56  def M5UnitFADD0 : ProcResource<1>; // Simple FP
57  def M5UnitNALU0 : ProcResource<1>; // Simple vector
58  def M5UnitNDOT0 : ProcResource<1>; // Dot product vector
59  def M5UnitNHAD  : ProcResource<1>; // Horizontal vector
60  def M5UnitNMSC  : ProcResource<1>; // FP and vector miscellanea
61  def M5UnitNMUL0 : ProcResource<1>; // Vector multiplication
62  def M5UnitNSHT0 : ProcResource<1>; // Vector shifting
63  def M5UnitNSHF0 : ProcResource<1>; // Vector shuffling
64  def M5UnitNCRY0 : ProcResource<1>; // Cryptographic
65}
66def M5PipeF1 : ProcResource<1>; // FP #1
67let Super = M5PipeF1 in {
68  def M5UnitFMAC1 : ProcResource<1>; // FP multiplication
69  def M5UnitFADD1 : ProcResource<1>; // Simple FP
70  def M5UnitFCVT0 : ProcResource<1>; // FP conversion
71  def M5UnitFDIV0 : ProcResource<2>; // FP division (serialized)
72  def M5UnitFSQR0 : ProcResource<2>; // FP square root (serialized)
73  def M5UnitFST0  : ProcResource<1>; // FP store
74  def M5UnitNALU1 : ProcResource<1>; // Simple vector
75  def M5UnitNDOT1 : ProcResource<1>; // Dot product vector
76  def M5UnitNSHT1 : ProcResource<1>; // Vector shifting
77  def M5UnitNSHF1 : ProcResource<1>; // Vector shuffling
78}
79def M5PipeF2 : ProcResource<1>; // FP #2
80let Super = M5PipeF2 in {
81  def M5UnitFMAC2 : ProcResource<1>; // FP multiplication
82  def M5UnitFADD2 : ProcResource<1>; // Simple FP
83  def M5UnitFCVT1 : ProcResource<1>; // FP conversion
84  def M5UnitFDIV1 : ProcResource<2>; // FP division (serialized)
85  def M5UnitFSQR1 : ProcResource<2>; // FP square root (serialized)
86  def M5UnitFST1  : ProcResource<1>; // FP store
87  def M5UnitNALU2 : ProcResource<1>; // Simple vector
88  def M5UnitNDOT2 : ProcResource<1>; // Dot product vector
89  def M5UnitNMUL1 : ProcResource<1>; // Vector multiplication
90  def M5UnitNSHT2 : ProcResource<1>; // Vector shifting
91  def M5UnitNCRY1 : ProcResource<1>; // Cryptographic
92}
93
94def M5UnitAX    : ProcResGroup<[M5UnitA,
95                                M5UnitC]>;
96def M5UnitAW    : ProcResGroup<[M5UnitA,
97                                M5UnitC,
98                                M5UnitE]>;
99def M5UnitL     : ProcResGroup<[M5UnitL0,
100                                M5UnitL1]>;
101def M5UnitS     : ProcResGroup<[M5UnitS0,
102                                M5UnitS1]>;
103def M5UnitFMAC  : ProcResGroup<[M5UnitFMAC0,
104                                M5UnitFMAC1,
105                                M5UnitFMAC2]>;
106def M5UnitFADD  : ProcResGroup<[M5UnitFADD0,
107                                M5UnitFADD1,
108                                M5UnitFADD2]>;
109def M5UnitFCVT  : ProcResGroup<[M5UnitFCVT0,
110                                M5UnitFCVT1]>;
111def M5UnitFDIV  : ProcResGroup<[M5UnitFDIV0,
112                                M5UnitFDIV1]>;
113def M5UnitFSQR  : ProcResGroup<[M5UnitFSQR0,
114                                M5UnitFSQR1]>;
115def M5UnitFST   : ProcResGroup<[M5UnitFST0,
116                                M5UnitFST1]>;
117def M5UnitNALU  : ProcResGroup<[M5UnitNALU0,
118                                M5UnitNALU1,
119                                M5UnitNALU2]>;
120def M5UnitNDOT  : ProcResGroup<[M5UnitNDOT0,
121                                M5UnitNDOT1,
122                                M5UnitNDOT2]>;
123def M5UnitNMUL  : ProcResGroup<[M5UnitNMUL0,
124                                M5UnitNMUL1]>;
125def M5UnitNSHT  : ProcResGroup<[M5UnitNSHT0,
126                                M5UnitNSHT1,
127                                M5UnitNSHT2]>;
128def M5UnitNSHF  : ProcResGroup<[M5UnitNSHF0,
129                                M5UnitNSHF1]>;
130def M5UnitNCRY  : ProcResGroup<[M5UnitNCRY0,
131                                M5UnitNCRY1]>;
132
133//===----------------------------------------------------------------------===//
134// Resources details.
135
136def M5WriteZ0 : SchedWriteRes<[]> { let Latency = 0; }
137def M5WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
138                                    let NumMicroOps = 0; }
139def M5WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
140                                    let NumMicroOps = 0; }
141
142def M5WriteA1W : SchedWriteRes<[M5UnitAW]> { let Latency = 1; }
143def M5WriteA1X : SchedWriteRes<[M5UnitAX]> { let Latency = 1; }
144def M5WriteAAW : SchedWriteRes<[M5UnitAW]> { let Latency = 2;
145                                             let ReleaseAtCycles = [2]; }
146def M5WriteAAX : SchedWriteRes<[M5UnitAX]> { let Latency = 2;
147                                             let ReleaseAtCycles = [2]; }
148def M5WriteAB  : SchedWriteRes<[M5UnitAX,
149                                M5UnitC,
150                                M5UnitE]>  { let Latency = 2;
151                                             let NumMicroOps = 2; }
152def M5WriteAC  : SchedWriteRes<[M5UnitAX,
153                                M5UnitAX,
154                                M5UnitC]>  { let Latency = 3;
155                                             let NumMicroOps = 3; }
156def M5WriteAD  : SchedWriteRes<[M5UnitAW,
157                                M5UnitC]>  { let Latency = 2;
158                                              let NumMicroOps = 2; }
159def M5WriteAFW : SchedWriteRes<[M5UnitAW]> { let Latency = 2;
160                                             let NumMicroOps = 2; }
161def M5WriteAFX : SchedWriteRes<[M5UnitAX]> { let Latency = 2;
162                                             let NumMicroOps = 2; }
163def M5WriteAUW : SchedWriteVariant<[SchedVar<IsCopyIdiomPred,   [M5WriteZ0]>,
164                                    SchedVar<ExynosArithPred,   [M5WriteA1W]>,
165                                    SchedVar<ExynosLogicExPred, [M5WriteA1W]>,
166                                    SchedVar<NoSchedPred,       [M5WriteAAW]>]>;
167def M5WriteAUX : SchedWriteVariant<[SchedVar<IsCopyIdiomPred,   [M5WriteZ0]>,
168                                    SchedVar<ExynosArithPred,   [M5WriteA1X]>,
169                                    SchedVar<ExynosLogicExPred, [M5WriteA1X]>,
170                                    SchedVar<NoSchedPred,       [M5WriteAAX]>]>;
171def M5WriteAVW : SchedWriteVariant<[SchedVar<ExynosResetPred,   [M5WriteZ0]>,
172                                    SchedVar<ExynosArithPred,   [M5WriteA1W]>,
173                                    SchedVar<ExynosLogicExPred, [M5WriteA1W]>,
174                                    SchedVar<NoSchedPred,       [M5WriteAAW]>]>;
175def M5WriteAVX : SchedWriteVariant<[SchedVar<ExynosResetPred,   [M5WriteZ0]>,
176                                    SchedVar<ExynosArithPred,   [M5WriteA1X]>,
177                                    SchedVar<ExynosLogicExPred, [M5WriteA1X]>,
178                                    SchedVar<NoSchedPred,       [M5WriteAAX]>]>;
179def M5WriteAXW : SchedWriteVariant<[SchedVar<ExynosArithPred,   [M5WriteA1W]>,
180                                    SchedVar<ExynosLogicExPred, [M5WriteA1W]>,
181                                    SchedVar<NoSchedPred,       [M5WriteAAW]>]>;
182def M5WriteAXX : SchedWriteVariant<[SchedVar<ExynosArithPred,   [M5WriteA1X]>,
183                                    SchedVar<ExynosLogicExPred, [M5WriteA1X]>,
184                                    SchedVar<NoSchedPred,       [M5WriteAAX]>]>;
185def M5WriteAYW : SchedWriteVariant<[SchedVar<IsRORImmIdiomPred, [M5WriteA1W]>,
186                                    SchedVar<NoSchedPred,       [M5WriteAFW]>]>;
187def M5WriteAYX : SchedWriteVariant<[SchedVar<IsRORImmIdiomPred, [M5WriteA1X]>,
188                                    SchedVar<NoSchedPred,       [M5WriteAFX]>]>;
189
190def M5WriteB1 : SchedWriteRes<[M5UnitB]> { let Latency = 1; }
191def M5WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M5WriteAC]>,
192                                   SchedVar<NoSchedPred,            [M5WriteAB]>]>;
193
194def M5WriteC1 : SchedWriteRes<[M5UnitC]> { let Latency = 1; }
195def M5WriteC2 : SchedWriteRes<[M5UnitC]> { let Latency = 2; }
196def M5WriteCA : SchedWriteRes<[M5UnitC]> { let Latency = 3;
197                                           let ReleaseAtCycles = [2]; }
198
199def M5WriteD10 : SchedWriteRes<[M5UnitD]> { let Latency = 10;
200                                            let ReleaseAtCycles = [10]; }
201def M5WriteD16 : SchedWriteRes<[M5UnitD]> { let Latency = 16;
202                                            let ReleaseAtCycles = [16]; }
203
204def M5WriteF2 : SchedWriteRes<[M5UnitF]> { let Latency = 2; }
205
206def M5WriteL4 : SchedWriteRes<[M5UnitL]> { let Latency = 4; }
207def M5WriteL5 : SchedWriteRes<[M5UnitL]> { let Latency = 5; }
208def M5WriteL6 : SchedWriteRes<[M5UnitL]> { let Latency = 6; }
209def M5WriteLA : SchedWriteRes<[M5UnitL,
210                               M5UnitL]> { let Latency = 6;
211                                           let NumMicroOps = 1; }
212def M5WriteLB : SchedWriteRes<[M5UnitAX,
213                               M5UnitL]> { let Latency = 6;
214                                           let NumMicroOps = 2; }
215def M5WriteLC : SchedWriteRes<[M5UnitAX,
216                               M5UnitL,
217                               M5UnitL]> { let Latency = 6;
218                                           let NumMicroOps = 2; }
219def M5WriteLD : SchedWriteRes<[M5UnitAX,
220                               M5UnitL]> { let Latency = 4;
221                                           let NumMicroOps = 2; }
222def M5WriteLE : SchedWriteRes<[M5UnitAX,
223                               M5UnitL]> { let Latency = 7;
224                                           let NumMicroOps = 2; }
225def M5WriteLFW : SchedWriteRes<[M5UnitAW,
226                                M5UnitAW,
227                                M5UnitAW,
228                                M5UnitAW,
229                                M5UnitL]>  { let Latency = 15;
230                                             let NumMicroOps = 6;
231                                             let ReleaseAtCycles = [1, 1, 1, 1, 15]; }
232def M5WriteLFX : SchedWriteRes<[M5UnitAX,
233                                M5UnitAX,
234                                M5UnitAX,
235                                M5UnitAX,
236                                M5UnitL]>  { let Latency = 15;
237                                             let NumMicroOps = 6;
238                                             let ReleaseAtCycles = [1, 1, 1, 1, 15]; }
239def M5WriteLGW : SchedWriteRes<[M5UnitAW,
240                                M5UnitL]>  { let Latency = 13;
241                                             let NumMicroOps = 1;
242                                             let ReleaseAtCycles = [1, 13]; }
243def M5WriteLGX : SchedWriteRes<[M5UnitAX,
244                                M5UnitL]>  { let Latency = 13;
245                                             let NumMicroOps = 1;
246                                             let ReleaseAtCycles = [1, 13]; }
247def M5WriteLH : SchedWriteRes<[]>        { let Latency = 6;
248                                           let NumMicroOps = 0; }
249def M5WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteL5]>,
250                                   SchedVar<NoSchedPred,         [M5WriteL4]>]>;
251def M5WriteLY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteLE]>,
252                                   SchedVar<NoSchedPred,         [M5WriteL6]>]>;
253
254def M5WriteS1  : SchedWriteRes<[M5UnitS]>  { let Latency = 1; }
255def M5WriteSA  : SchedWriteRes<[M5UnitS0]> { let Latency = 4; }
256def M5WriteSB  : SchedWriteRes<[M5UnitAX,
257                                M5UnitS]>  { let Latency = 2;
258                                             let NumMicroOps = 1; }
259def M5WriteSX  : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteSB]>,
260                                    SchedVar<NoSchedPred,         [M5WriteS1]>]>;
261
262def M5ReadAdrBase : SchedReadVariant<[SchedVar<
263                                        MCSchedPredicate<
264                                          CheckAny<
265                                            [ScaledIdxFn,
266                                             ExynosScaledIdxFn]>>, [ReadDefault]>,
267                                      SchedVar<NoSchedPred,        [ReadDefault]>]>;
268
269def M5WriteNEONB   : SchedWriteRes<[M5UnitNALU,
270                                    M5UnitS0]>    { let Latency = 5;
271                                                    let NumMicroOps = 2; }
272def M5WriteNEONH   : SchedWriteRes<[M5UnitNALU,
273                                    M5UnitS0]>    { let Latency = 2;
274                                                    let NumMicroOps = 2; }
275def M5WriteNEONI   : SchedWriteRes<[M5UnitS0,
276                                    M5UnitNSHF]>  { let Latency = 6;
277                                                    let NumMicroOps = 2; }
278def M5WriteNEONK   : SchedWriteRes<[M5UnitNSHF,
279                                    M5UnitFCVT0,
280                                    M5UnitS0]>    { let Latency = 5;
281                                                    let NumMicroOps = 2; }
282def M5WriteNEONN   : SchedWriteRes<[M5UnitNMSC,
283                                    M5UnitNMSC]>  { let Latency = 5;
284                                                    let NumMicroOps = 2;
285                                                    let ReleaseAtCycles = [7, 7]; }
286def M5WriteNEONO   : SchedWriteRes<[M5UnitNMSC,
287                                    M5UnitNMSC,
288                                    M5UnitNMSC]>  { let Latency = 8;
289                                                    let NumMicroOps = 3;
290                                                    let ReleaseAtCycles = [10, 10, 10]; }
291def M5WriteNEONP   : SchedWriteRes<[M5UnitNSHF,
292                                    M5UnitS0,
293                                    M5UnitFCVT]>  { let Latency = 7;
294                                                    let NumMicroOps = 2; }
295def M5WriteNEONQ   : SchedWriteRes<[M5UnitNMSC,
296                                    M5UnitC]>     { let Latency = 3;
297                                                    let NumMicroOps = 1; }
298def M5WriteNEONU   : SchedWriteRes<[M5UnitFSQR,
299                                    M5UnitFSQR]>  { let Latency = 7;
300                                                    let ReleaseAtCycles = [4, 4]; }
301def M5WriteNEONV   : SchedWriteRes<[M5UnitFDIV,
302                                    M5UnitFDIV]>  { let Latency = 7;
303                                                    let ReleaseAtCycles = [6, 6]; }
304def M5WriteNEONW   : SchedWriteRes<[M5UnitFDIV,
305                                    M5UnitFDIV]>  { let Latency = 12;
306                                                    let ReleaseAtCycles = [9, 9]; }
307def M5WriteNEONX   : SchedWriteRes<[M5UnitFSQR,
308                                    M5UnitFSQR]>  { let Latency = 8;
309                                                    let ReleaseAtCycles = [5, 5]; }
310def M5WriteNEONY   : SchedWriteRes<[M5UnitFSQR,
311                                    M5UnitFSQR]>  { let Latency = 12;
312                                                    let ReleaseAtCycles = [9, 9]; }
313def M5WriteNEONZ   : SchedWriteVariant<[SchedVar<ExynosQFormPred, [M5WriteNEONO]>,
314                                        SchedVar<NoSchedPred,     [M5WriteNEONN]>]>;
315
316def M5WriteFADD2   : SchedWriteRes<[M5UnitFADD]>  { let Latency = 2; }
317
318def M5WriteFCVT2   : SchedWriteRes<[M5UnitFCVT]>  { let Latency = 2; }
319def M5WriteFCVT2A  : SchedWriteRes<[M5UnitFCVT0]> { let Latency = 2; }
320def M5WriteFCVT3   : SchedWriteRes<[M5UnitFCVT]>  { let Latency = 3; }
321def M5WriteFCVT3A  : SchedWriteRes<[M5UnitFCVT0]> { let Latency = 3; }
322def M5WriteFCVTA   : SchedWriteRes<[M5UnitFCVT0,
323                                    M5UnitS0]>    { let Latency = 3;
324                                                    let NumMicroOps = 1; }
325def M5WriteFCVTB   : SchedWriteRes<[M5UnitFCVT,
326                                    M5UnitS0]>    { let Latency = 4;
327                                                    let NumMicroOps = 1; }
328def M5WriteFCVTC   : SchedWriteRes<[M5UnitFCVT,
329                                    M5UnitS0]>    { let Latency = 6;
330                                                    let NumMicroOps = 1; }
331
332def M5WriteFDIV5   : SchedWriteRes<[M5UnitFDIV]>  { let Latency = 5;
333                                                    let ReleaseAtCycles = [2]; }
334def M5WriteFDIV7   : SchedWriteRes<[M5UnitFDIV]>  { let Latency = 7;
335                                                    let ReleaseAtCycles = [4]; }
336def M5WriteFDIV12  : SchedWriteRes<[M5UnitFDIV]>  { let Latency = 12;
337                                                    let ReleaseAtCycles = [9]; }
338
339def M5WriteFMAC3   : SchedWriteRes<[M5UnitFMAC]>  { let Latency = 3; }
340def M5WriteFMAC4   : SchedWriteRes<[M5UnitFMAC]>  { let Latency = 4; }
341def M5WriteFMAC5   : SchedWriteRes<[M5UnitFMAC]>  { let Latency = 5; }
342
343def M5WriteFSQR5   : SchedWriteRes<[M5UnitFSQR]>  { let Latency = 5;
344                                                    let ReleaseAtCycles = [2]; }
345def M5WriteFSQR7   : SchedWriteRes<[M5UnitFSQR]>  { let Latency = 7;
346                                                    let ReleaseAtCycles = [4]; }
347def M5WriteFSQR8   : SchedWriteRes<[M5UnitFSQR]>  { let Latency = 8;
348                                                    let ReleaseAtCycles = [5]; }
349def M5WriteFSQR12  : SchedWriteRes<[M5UnitFSQR]>  { let Latency = 12;
350                                                    let ReleaseAtCycles = [9]; }
351
352def M5WriteNALU1   : SchedWriteRes<[M5UnitNALU]>  { let Latency = 1; }
353def M5WriteNALU2   : SchedWriteRes<[M5UnitNALU]>  { let Latency = 2; }
354
355def M5WriteNDOT2   : SchedWriteRes<[M5UnitNDOT]>  { let Latency = 2; }
356
357def M5WriteNCRY2   : SchedWriteRes<[M5UnitNCRY]>  { let Latency = 2; }
358def M5WriteNCRY1A  : SchedWriteRes<[M5UnitNCRY0]> { let Latency = 1; }
359def M5WriteNCRY2A  : SchedWriteRes<[M5UnitNCRY0]> { let Latency = 2; }
360def M5WriteNCRY3A  : SchedWriteRes<[M5UnitNCRY0]> { let Latency = 3; }
361def M5WriteNCRY5A  : SchedWriteRes<[M5UnitNCRY]>  { let Latency = 5; }
362
363def M5WriteNHAD1   : SchedWriteRes<[M5UnitNHAD]>  { let Latency = 1; }
364def M5WriteNHAD3   : SchedWriteRes<[M5UnitNHAD]>  { let Latency = 3; }
365
366def M5WriteNMSC1   : SchedWriteRes<[M5UnitNMSC]>  { let Latency = 1; }
367def M5WriteNMSC2   : SchedWriteRes<[M5UnitNMSC]>  { let Latency = 2; }
368
369def M5WriteNMUL3   : SchedWriteRes<[M5UnitNMUL]>  { let Latency = 3; }
370
371def M5WriteNSHF1   : SchedWriteRes<[M5UnitNSHF]>  { let Latency = 1; }
372def M5WriteNSHF2   : SchedWriteRes<[M5UnitNSHF]>  { let Latency = 2; }
373def M5WriteNSHFA   : SchedWriteRes<[M5UnitNSHF]>  { let Latency = 2; }
374def M5WriteNSHFB   : SchedWriteRes<[M5UnitNSHF]>  { let Latency = 4;
375                                                    let NumMicroOps = 2; }
376def M5WriteNSHFC   : SchedWriteRes<[M5UnitNSHF]>  { let Latency = 6;
377                                                    let NumMicroOps = 3; }
378def M5WriteNSHFD   : SchedWriteRes<[M5UnitNSHF]>  { let Latency = 8;
379                                                    let NumMicroOps = 4; }
380
381def M5WriteNSHT2   : SchedWriteRes<[M5UnitNSHT]>  { let Latency = 2; }
382def M5WriteNSHT4A  : SchedWriteRes<[M5UnitNSHT1]> { let Latency = 4; }
383
384def M5WriteVLDA    : SchedWriteRes<[M5UnitL,
385                                    M5UnitL]>     { let Latency = 6;
386                                                    let NumMicroOps = 2; }
387def M5WriteVLDB    : SchedWriteRes<[M5UnitL,
388                                    M5UnitL,
389                                    M5UnitL]>     { let Latency = 7;
390                                                    let NumMicroOps = 3; }
391def M5WriteVLDC    : SchedWriteRes<[M5UnitL,
392                                    M5UnitL,
393                                    M5UnitL,
394                                    M5UnitL]>     { let Latency = 7;
395                                                    let NumMicroOps = 4; }
396def M5WriteVLDD    : SchedWriteRes<[M5UnitL,
397                                    M5UnitNSHF]>  { let Latency = 7;
398                                                    let NumMicroOps = 2;
399                                                    let ReleaseAtCycles = [2, 1]; }
400def M5WriteVLDF    : SchedWriteRes<[M5UnitL,
401                                    M5UnitL]>     { let Latency = 11;
402                                                    let NumMicroOps = 2;
403                                                    let ReleaseAtCycles = [6, 5]; }
404def M5WriteVLDG    : SchedWriteRes<[M5UnitL,
405                                    M5UnitNSHF,
406                                    M5UnitNSHF]>  { let Latency = 7;
407                                                    let NumMicroOps = 3;
408                                                    let ReleaseAtCycles = [2, 1, 1]; }
409def M5WriteVLDI    : SchedWriteRes<[M5UnitL,
410                                    M5UnitL,
411                                    M5UnitL]>     { let Latency = 13;
412                                                    let NumMicroOps = 3; }
413def M5WriteVLDJ    : SchedWriteRes<[M5UnitL,
414                                    M5UnitNSHF,
415                                    M5UnitNSHF,
416                                    M5UnitNSHF]>  { let Latency = 8;
417                                                    let NumMicroOps = 4; }
418def M5WriteVLDK    : SchedWriteRes<[M5UnitL,
419                                    M5UnitNSHF,
420                                    M5UnitNSHF,
421                                    M5UnitNSHF,
422                                    M5UnitNSHF]>  { let Latency = 8;
423                                                    let NumMicroOps = 5; }
424def M5WriteVLDL    : SchedWriteRes<[M5UnitL,
425                                    M5UnitNSHF,
426                                    M5UnitNSHF,
427                                    M5UnitL,
428                                    M5UnitNSHF]>  { let Latency = 8;
429                                                    let NumMicroOps = 5; }
430def M5WriteVLDM    : SchedWriteRes<[M5UnitL,
431                                    M5UnitNSHF,
432                                    M5UnitNSHF,
433                                    M5UnitL,
434                                    M5UnitNSHF,
435                                    M5UnitNSHF]>  { let Latency = 8;
436                                                    let NumMicroOps = 6; }
437def M5WriteVLDN    : SchedWriteRes<[M5UnitL,
438                                    M5UnitL,
439                                    M5UnitL,
440                                    M5UnitL]>     { let Latency = 15;
441                                                    let NumMicroOps = 4;
442                                                    let ReleaseAtCycles = [2, 2, 2, 2]; }
443
444def M5WriteVST1    : SchedWriteRes<[M5UnitS,
445                                    M5UnitFST]> { let Latency = 1;
446                                                  let NumMicroOps = 1; }
447def M5WriteVSTA    : SchedWriteRes<[M5UnitS,
448                                    M5UnitFST,
449                                    M5UnitS,
450                                    M5UnitFST]> { let Latency = 2;
451                                                  let NumMicroOps = 2; }
452def M5WriteVSTB    : SchedWriteRes<[M5UnitS,
453                                    M5UnitFST,
454                                    M5UnitS,
455                                    M5UnitFST,
456                                    M5UnitS,
457                                    M5UnitFST]> { let Latency = 3;
458                                                  let NumMicroOps = 3; }
459def M5WriteVSTC    : SchedWriteRes<[M5UnitS,
460                                    M5UnitFST,
461                                    M5UnitS,
462                                    M5UnitFST,
463                                    M5UnitS,
464                                    M5UnitFST,
465                                    M5UnitS,
466                                    M5UnitFST]> { let Latency = 4;
467                                                  let NumMicroOps = 4; }
468def M5WriteVSTD    : SchedWriteRes<[M5UnitS,
469                                    M5UnitFST]> { let Latency = 2; }
470def M5WriteVSTE    : SchedWriteRes<[M5UnitS,
471                                    M5UnitFST,
472                                    M5UnitS,
473                                    M5UnitFST]> { let Latency = 2;
474                                                  let NumMicroOps = 1; }
475def M5WriteVSTF    : SchedWriteRes<[M5UnitNSHF,
476                                    M5UnitNSHF,
477                                    M5UnitS,
478                                    M5UnitFST]> { let Latency = 4;
479                                                  let NumMicroOps = 3; }
480def M5WriteVSTG    : SchedWriteRes<[M5UnitNSHF,
481                                    M5UnitNSHF,
482                                    M5UnitNSHF,
483                                    M5UnitS,
484                                    M5UnitFST,
485                                    M5UnitS,
486                                    M5UnitFST]> { let Latency = 4;
487                                                  let NumMicroOps = 5; }
488def M5WriteVSTH    : SchedWriteRes<[M5UnitS0,
489                                    M5UnitFST]> { let Latency = 1;
490                                                  let NumMicroOps = 1; }
491def M5WriteVSTI    : SchedWriteRes<[M5UnitNSHF,
492                                    M5UnitNSHF,
493                                    M5UnitNSHF,
494                                    M5UnitNSHF,
495                                    M5UnitS,
496                                    M5UnitFST,
497                                    M5UnitS,
498                                    M5UnitFST,
499                                    M5UnitS,
500                                    M5UnitFST,
501                                    M5UnitS,
502                                    M5UnitFST]> { let Latency = 8;
503                                                  let NumMicroOps = 5;
504                                                  let ReleaseAtCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; }
505def M5WriteVSTJ    : SchedWriteRes<[M5UnitA,
506                                    M5UnitS0,
507                                    M5UnitFST]> { let Latency = 1;
508                                                  let NumMicroOps = 1; }
509def M5WriteVSTK    : SchedWriteRes<[M5UnitAX,
510                                    M5UnitS,
511                                    M5UnitFST]> { let Latency = 3;
512                                                  let NumMicroOps = 2; }
513def M5WriteVSTL    : SchedWriteRes<[M5UnitNSHF,
514                                    M5UnitNSHF,
515                                    M5UnitS,
516                                    M5UnitFST,
517                                    M5UnitS,
518                                    M5UnitFST]> { let Latency = 4;
519                                                    let NumMicroOps = 4;
520                                                    let ReleaseAtCycles = [1, 1, 2, 1, 2, 1]; }
521def M5WriteVSTY   : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteVSTK]>,
522                                       SchedVar<NoSchedPred,         [WriteVST]>]>;
523
524// Special cases.
525def M5WriteCOPY    : SchedWriteVariant<[SchedVar<ExynosFPPred, [M5WriteNALU2]>,
526                                        SchedVar<NoSchedPred,  [M5WriteZ0]>]>;
527def M5WriteMOVI    : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M5WriteZ0]>,
528                                        SchedVar<NoSchedPred,       [M5WriteNALU1]>]>;
529
530// Fast forwarding.
531def M5ReadFM1      : SchedReadAdvance<+1, [M5WriteF2]>;
532def M5ReadAESM2    : SchedReadAdvance<+2, [M5WriteNCRY2]>;
533def M5ReadFMACM1   : SchedReadAdvance<+1, [M5WriteFMAC4,
534                                           M5WriteFMAC5]>;
535def M5ReadNMULM1   : SchedReadAdvance<+1, [M5WriteNMUL3]>;
536
537//===----------------------------------------------------------------------===//
538// Coarse scheduling model.
539
540// Branch instructions.
541def : SchedAlias<WriteBr,    M5WriteZ0>;
542def : SchedAlias<WriteBrReg, M5WriteC1>;
543
544// Arithmetic and logical integer instructions.
545def : SchedAlias<WriteI,     M5WriteA1W>;
546def : SchedAlias<WriteIEReg, M5WriteA1W>; // FIXME: M5WriteAX crashes TableGen.
547def : SchedAlias<WriteISReg, M5WriteA1W>; // FIXME: M5WriteAX crashes TableGen.
548def : SchedAlias<WriteIS,    M5WriteA1W>;
549
550// Move instructions.
551def : SchedAlias<WriteImm, M5WriteA1W>;
552
553// Divide and multiply instructions.
554def : SchedAlias<WriteID32, M5WriteD10>;
555def : SchedAlias<WriteID64, M5WriteD16>;
556def : SchedAlias<WriteIM32, M5WriteC2>;
557def : SchedAlias<WriteIM64, M5WriteCA>;
558
559// Miscellaneous instructions.
560def : SchedAlias<WriteExtr, M5WriteAYW>;
561
562// Addressing modes.
563def : SchedAlias<WriteAdr,    M5WriteZ1>;
564def : SchedAlias<ReadAdrBase, M5ReadAdrBase>;
565
566// Load instructions.
567def : SchedAlias<WriteLD,    M5WriteL4>;
568def : SchedAlias<WriteLDHi,  M5WriteZ4>;
569def : SchedAlias<WriteLDIdx, M5WriteLX>;
570
571// Store instructions.
572def : SchedAlias<WriteST,    M5WriteS1>;
573def : SchedAlias<WriteSTP,   M5WriteS1>;
574def : SchedAlias<WriteSTX,   M5WriteS1>;
575def : SchedAlias<WriteSTIdx, M5WriteSX>;
576
577// Atomic load and store instructions.
578def : SchedAlias<WriteAtomic, M5WriteLGW>;
579
580// FP data instructions.
581def : SchedAlias<WriteF,    M5WriteFADD2>;
582def : SchedAlias<WriteFCmp, M5WriteNMSC2>;
583def : SchedAlias<WriteFDiv, M5WriteFDIV12>;
584def : SchedAlias<WriteFMul, M5WriteFMAC3>;
585
586// FP miscellaneous instructions.
587def : SchedAlias<WriteFCvt,  M5WriteFCVT2>;
588def : SchedAlias<WriteFImm,  M5WriteNALU1>;
589def : SchedAlias<WriteFCopy, M5WriteNALU2>;
590
591// FP load instructions.
592def : SchedAlias<WriteVLD, M5WriteL6>;
593
594// FP store instructions.
595def : SchedAlias<WriteVST, M5WriteVST1>;
596
597// ASIMD FP instructions.
598def : SchedAlias<WriteVd, M5WriteNALU1>;
599def : SchedAlias<WriteVq, M5WriteNALU1>;
600
601// Other miscellaneous instructions.
602def : WriteRes<WriteBarrier, []> { let Latency = 1; }
603def : WriteRes<WriteHint,    []> { let Latency = 1; }
604def : WriteRes<WriteSys,     []> { let Latency = 1; }
605
606//===----------------------------------------------------------------------===//
607// Generic fast forwarding.
608
609// TODO: Add FP register forwarding rules.
610
611def : ReadAdvance<ReadI,       0>;
612def : ReadAdvance<ReadISReg,   0>;
613def : ReadAdvance<ReadIEReg,   0>;
614def : ReadAdvance<ReadIM,      0>;
615// TODO: The forwarding for 32 bits actually saves 2 cycles.
616def : ReadAdvance<ReadIMA,     3, [WriteIM32, WriteIM64]>;
617def : ReadAdvance<ReadID,      0>;
618def : ReadAdvance<ReadExtrHi,  0>;
619def : ReadAdvance<ReadAdrBase, 0>;
620def : ReadAdvance<ReadVLD,     0>;
621def : ReadAdvance<ReadST,      0>;
622
623//===----------------------------------------------------------------------===//
624// Finer scheduling model.
625
626// Branch instructions
627def : InstRW<[M5WriteB1],  (instrs Bcc)>;
628def : InstRW<[M5WriteAFX], (instrs BL)>;
629def : InstRW<[M5WriteBX],  (instrs BLR)>;
630def : InstRW<[M5WriteC1],  (instregex "^CBN?Z[WX]")>;
631def : InstRW<[M5WriteAD],  (instregex "^TBN?ZW")>;
632def : InstRW<[M5WriteAB],  (instregex "^TBN?ZX")>;
633
634// Arithmetic and logical integer instructions.
635def : InstRW<[M5WriteA1W], (instregex "^(ADC|SBC)S?Wr$")>;
636def : InstRW<[M5WriteA1X], (instregex "^(ADC|SBC)S?Xr$")>;
637def : InstRW<[M5WriteAXW], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)Wrs$")>;
638def : InstRW<[M5WriteAXX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)Xrs$")>;
639def : InstRW<[M5WriteAUW], (instrs ORRWrs)>;
640def : InstRW<[M5WriteAUX], (instrs ORRXrs)>;
641def : InstRW<[M5WriteAXW], (instregex "^(ADD|AND|BIC|SUB)SWrs$")>;
642def : InstRW<[M5WriteAXX], (instregex "^(ADD|AND|BIC|SUB)SXrs$")>;
643def : InstRW<[M5WriteAXW], (instregex "^(ADD|SUB)S?Wrx(64)?$")>;
644def : InstRW<[M5WriteAXX], (instregex "^(ADD|SUB)S?Xrx(64)?$")>;
645def : InstRW<[M5WriteAVW], (instrs ADDWri, ORRWri)>;
646def : InstRW<[M5WriteAVX], (instrs ADDXri, ORRXri)>;
647def : InstRW<[M5WriteA1W], (instregex "^CCM[NP]W[ir]$")>;
648def : InstRW<[M5WriteA1X], (instregex "^CCM[NP]X[ir]$")>;
649def : InstRW<[M5WriteA1W], (instrs CSELWr, CSINCWr, CSINVWr, CSNEGWr)>;
650def : InstRW<[M5WriteA1X], (instrs CSELXr, CSINCXr, CSINVXr, CSNEGXr)>;
651
652// Move instructions.
653def : InstRW<[M5WriteCOPY], (instrs COPY)>;
654def : InstRW<[M5WriteZ0],   (instrs ADR, ADRP)>;
655def : InstRW<[M5WriteZ0],   (instregex "^MOV[NZ][WX]i$")>;
656
657// Shift instructions.
658def : InstRW<[M5WriteA1W], (instrs ASRVWr, LSLVWr, LSRVWr, RORVWr)>;
659def : InstRW<[M5WriteA1X], (instrs ASRVXr, LSLVXr, LSRVXr, RORVXr)>;
660
661// Miscellaneous instructions.
662def : InstRW<[M5WriteAYW], (instrs EXTRWrri)>;
663def : InstRW<[M5WriteAYX], (instrs EXTRXrri)>;
664def : InstRW<[M5WriteA1W], (instrs BFMWri, SBFMWri, UBFMWri)>;
665def : InstRW<[M5WriteA1X], (instrs BFMXri, SBFMXri, UBFMXri)>;
666def : InstRW<[M5WriteA1W], (instrs CLSWr, CLZWr)>;
667def : InstRW<[M5WriteA1X], (instrs CLSXr, CLZXr)>;
668def : InstRW<[M5WriteA1W], (instrs RBITWr, REVWr, REV16Wr)>;
669def : InstRW<[M5WriteA1X], (instrs RBITXr, REVXr, REV16Xr, REV32Xr)>;
670
671// Load instructions.
672def : InstRW<[M5WriteLD,
673              WriteLDHi,
674              WriteAdr],    (instregex "^LDP(SW|W|X)(post|pre)")>;
675def : InstRW<[M5WriteL5,
676              ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
677def : InstRW<[WriteLDIdx,
678              ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
679def : InstRW<[M5WriteL5,
680              ReadAdrBase], (instrs PRFMroW)>;
681def : InstRW<[WriteLDIdx,
682              ReadAdrBase], (instrs PRFMroX)>;
683
684// Store instructions.
685def : InstRW<[M5WriteSB,
686              ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>;
687def : InstRW<[WriteST,
688              ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>;
689
690// Atomic load and store instructions.
691def : InstRW<[M5WriteLGW], (instregex "^CAS(A|AL|L)?[BHW]$")>;
692def : InstRW<[M5WriteLGX], (instregex "^CAS(A|AL|L)?X$")>;
693def : InstRW<[M5WriteLFW], (instregex "^CASP(A|AL|L)?W$")>;
694def : InstRW<[M5WriteLFX], (instregex "^CASP(A|AL|L)?X$")>;
695def : InstRW<[M5WriteLGW], (instregex "^LD(ADD|CLR|EOR|SET|[SU]MAX|[SU]MIN)(A|AL|L)?[BHW]$")>;
696def : InstRW<[M5WriteLGX], (instregex "^LD(ADD|CLR|EOR|SET|[SU]MAX|[SU]MIN)(A|AL|L)?X$")>;
697def : InstRW<[M5WriteLGW], (instregex "^SWP(A|AL|L)?[BHW]$")>;
698def : InstRW<[M5WriteLGX], (instregex "^SWP(A|AL|L)?X$")>;
699
700// FP data instructions.
701def : InstRW<[M5WriteNSHF1],  (instrs FABSHr, FABSSr,FABSDr)>;
702def : InstRW<[M5WriteFADD2],  (instregex "^F(ADD|SUB)[HSD]rr")>;
703def : InstRW<[M5WriteFADD2],  (instregex "^FADDPv.i(16|32|64)")>;
704def : InstRW<[M5WriteNEONQ],  (instregex "^FCCMPE?[HSD]rr")>;
705def : InstRW<[M5WriteNMSC2],  (instregex "^FCMPE?[HSD]r[ir]")>;
706def : InstRW<[M5WriteNMSC1],  (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)(16|32|64|v1)")>;
707def : InstRW<[M5WriteFDIV5],  (instrs FDIVHrr)>;
708def : InstRW<[M5WriteFDIV7],  (instrs FDIVSrr)>;
709def : InstRW<[M5WriteFDIV12], (instrs FDIVDrr)>;
710def : InstRW<[M5WriteNMSC1],  (instregex "^F(MAX|MIN)(NM)?[HSD]rr")>;
711def : InstRW<[M5WriteFMAC3],  (instregex "^FN?MUL[HSD]rr")>;
712def : InstRW<[M5WriteFMAC3],  (instrs FMULX16, FMULX32, FMULX64)>;
713def : InstRW<[M5WriteFMAC4,
714              M5ReadFMACM1],  (instregex "^FN?M(ADD|SUB)[HSD]rrr")>;
715def : InstRW<[M5WriteNALU2],  (instrs FNEGHr, FNEGSr, FNEGDr)>;
716def : InstRW<[M5WriteFCVT3A], (instregex "^FRINT.+r")>;
717def : InstRW<[M5WriteNEONH],  (instregex "^FCSEL[HSD]rrr")>;
718def : InstRW<[M5WriteFSQR5],  (instrs FSQRTHr)>;
719def : InstRW<[M5WriteFSQR8],  (instrs FSQRTSr)>;
720def : InstRW<[M5WriteFSQR12], (instrs FSQRTDr)>;
721
722// FP miscellaneous instructions.
723def : InstRW<[M5WriteFCVT2],  (instregex "^FCVT[HSD][HSD]r")>;
724def : InstRW<[M5WriteFCVTC],  (instregex "^[SU]CVTF[SU][XW][HSD]ri")>;
725def : InstRW<[M5WriteFCVTB],  (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>;
726def : InstRW<[M5WriteNALU1],  (instregex "^FMOV[HSD]i")>;
727def : InstRW<[M5WriteNALU2],  (instregex "^FMOV[HSD]r")>;
728def : InstRW<[M5WriteSA],     (instregex "^FMOV[WX][HSD]r")>;
729def : InstRW<[M5WriteFCVTA],  (instregex "^FMOV[HSD][WX]r")>;
730def : InstRW<[M5WriteNEONI],  (instregex "^FMOVXDHighr")>;
731def : InstRW<[M5WriteNEONK],  (instregex "^FMOVDXHighr")>;
732def : InstRW<[M5WriteFCVT3],  (instregex "^F(RECP|RSQRT)Ev1(f16|i32|i64)")>;
733def : InstRW<[M5WriteNMSC1],  (instregex "^FRECPXv1")>;
734def : InstRW<[M5WriteFMAC4],  (instregex "^F(RECP|RSQRT)S(16|32|64)")>;
735
736// FP load instructions.
737def : InstRW<[WriteVLD],    (instregex "^LDR[SDQ]l")>;
738def : InstRW<[WriteVLD],    (instregex "^LDUR[BHSDQ]i")>;
739def : InstRW<[WriteVLD,
740              WriteAdr],    (instregex "^LDR[BHSDQ](post|pre)")>;
741def : InstRW<[WriteVLD],    (instregex "^LDR[BHSDQ]ui")>;
742def : InstRW<[M5WriteLE,
743              ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>;
744def : InstRW<[WriteVLD,
745              ReadAdrBase], (instregex "^LDR[BHSD]roX")>;
746def : InstRW<[M5WriteLY,
747              ReadAdrBase], (instrs LDRQroX)>;
748def : InstRW<[WriteVLD,
749              M5WriteLH],   (instregex "^LDN?P[SD]i")>;
750def : InstRW<[M5WriteLA,
751              M5WriteLH],   (instregex "^LDN?PQi")>;
752def : InstRW<[M5WriteLB,
753              M5WriteLH,
754              WriteAdr],    (instregex "^LDP[SD](post|pre)")>;
755def : InstRW<[M5WriteLC,
756              M5WriteLH,
757              WriteAdr],    (instregex "^LDPQ(post|pre)")>;
758
759// FP store instructions.
760def : InstRW<[WriteVST],    (instregex "^STUR[BHSDQ]i")>;
761def : InstRW<[WriteVST,
762              WriteAdr],    (instregex "^STR[BHSDQ](post|pre)")>;
763def : InstRW<[WriteVST],    (instregex "^STR[BHSDQ]ui")>;
764def : InstRW<[WriteVST,
765              ReadAdrBase], (instregex "^STR[BHSD]ro[WX]")>;
766def : InstRW<[M5WriteVSTK,
767              ReadAdrBase], (instregex "^STRQroW")>;
768def : InstRW<[M5WriteVSTY,
769              ReadAdrBase], (instregex "^STRQroX")>;
770def : InstRW<[WriteVST],    (instregex "^STN?P[SD]i")>;
771def : InstRW<[M5WriteVSTH], (instregex "^STN?PQi")>;
772def : InstRW<[WriteVST,
773              WriteAdr],    (instregex "^STP[SD](post|pre)")>;
774def : InstRW<[M5WriteVSTJ,
775              WriteAdr],    (instregex "^STPQ(post|pre)")>;
776
777// ASIMD instructions.
778def : InstRW<[M5WriteNHAD1],  (instregex "^[SU]ABDL?v")>;
779def : InstRW<[M5WriteNHAD3],  (instregex "^[SU]ABAL?v")>;
780def : InstRW<[M5WriteNMSC1],  (instregex "^ABSv")>;
781def : InstRW<[M5WriteNALU2],  (instregex "^(ADD|NEG|SUB)v")>;
782def : InstRW<[M5WriteNHAD3],  (instregex "^[SU]?ADDL?Pv")>;
783def : InstRW<[M5WriteNHAD3],  (instregex "^[SU]H(ADD|SUB)v")>;
784def : InstRW<[M5WriteNHAD3],  (instregex "^[SU](ADD|SUB)[LW]v")>;
785def : InstRW<[M5WriteNHAD3],  (instregex "^R?(ADD|SUB)HN2?v")>;
786def : InstRW<[M5WriteNHAD3],  (instregex "^[SU]Q(ADD|SUB)v")>;
787def : InstRW<[M5WriteNHAD3],  (instregex "^(SU|US)QADDv")>;
788def : InstRW<[M5WriteNHAD3],  (instregex "^[SU]RHADDv")>;
789def : InstRW<[M5WriteNMSC1],  (instregex "^SQ(ABS|NEG)v")>;
790def : InstRW<[M5WriteNHAD3],  (instregex "^[SU]?ADDL?Vv")>;
791def : InstRW<[M5WriteNMSC1],  (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>;
792def : InstRW<[M5WriteNALU2],  (instregex "^CMTSTv")>;
793def : InstRW<[M5WriteNALU2],  (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>;
794def : InstRW<[M5WriteNMSC1],  (instregex "^[SU](MIN|MAX)v")>;
795def : InstRW<[M5WriteNMSC2],  (instregex "^[SU](MIN|MAX)Pv")>;
796def : InstRW<[M5WriteNHAD3],  (instregex "^[SU](MIN|MAX)Vv")>;
797def : InstRW<[M5WriteNMUL3],  (instregex "^(SQR?D)?MULH?v")>;
798def : InstRW<[M5WriteNMUL3,
799              M5ReadNMULM1],  (instregex "^ML[AS]v")>;
800def : InstRW<[M5WriteNMUL3,
801              M5ReadNMULM1],  (instregex "^SQRDML[AS]H")>;
802def : InstRW<[M5WriteNMUL3],  (instregex "^(S|U|SQD)ML[AS]L(v1(i32|i64)|v2i32|v4i16|v8i8)")>;
803def : InstRW<[M5WriteNMUL3,
804              M5ReadNMULM1],  (instregex "^(S|U|SQD)ML[AS]L(v4i32|v8i16|v16i8)")>;
805def : InstRW<[M5WriteNMUL3,
806              M5ReadNMULM1],  (instregex "^(S|U|SQD)MULL(v1(i32|i64)|v2i32|v4i16|v8i8)")>;
807def : InstRW<[M5WriteNMUL3,
808              M5ReadNMULM1],  (instregex "^(S|U|SQD)MULL(v4i32|v8i16|v16i8)")>;
809def : InstRW<[M5WriteNDOT2],  (instregex "^[SU]DOT(lane)?v")>;
810def : InstRW<[M5WriteNHAD3],  (instregex "^[SU]ADALPv")>;
811def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]R?SRA[dv]")>;
812def : InstRW<[M5WriteNSHT2],  (instregex "^SHL[dv]")>;
813def : InstRW<[M5WriteNSHT2],  (instregex "^S[LR]I[dv]")>;
814def : InstRW<[M5WriteNSHT2],  (instregex "^[SU]SH[LR][dv]")>;
815def : InstRW<[M5WriteNSHT2],  (instregex "^[SU]?SHLLv")>;
816def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]?Q?R?SHRU?N[bhsv]")>;
817def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]RSH[LR][dv]")>;
818def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]QR?SHLU?[bhsdv]")>;
819
820// ASIMD FP instructions.
821def : InstRW<[M5WriteNSHF2],  (instregex "^FABSv.f(16|32|64)")>;
822def : InstRW<[M5WriteFADD2],  (instregex "^F(ABD|ADD|SUB)v.f(16|32|64)")>;
823def : InstRW<[M5WriteFADD2],  (instregex "^FADDPv.f(16|32|64)")>;
824def : InstRW<[M5WriteNMSC1],  (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>;
825def : InstRW<[M5WriteFCVT2],  (instregex "^FCVT(L|N|XN)v")>;
826def : InstRW<[M5WriteFCVT2A], (instregex "^FCVT[AMNPZ][SU]v")>;
827def : InstRW<[M5WriteFCVT2],  (instregex "^[SU]CVTFv.[fi](16|32|64)")>;
828def : InstRW<[M5WriteFDIV7],  (instrs FDIVv4f16)>;
829def : InstRW<[M5WriteNEONV],  (instrs FDIVv8f16)>;
830def : InstRW<[M5WriteFDIV7],  (instrs FDIVv2f32)>;
831def : InstRW<[M5WriteNEONV],  (instrs FDIVv4f32)>;
832def : InstRW<[M5WriteNEONW],  (instrs FDIVv2f64)>;
833def : InstRW<[M5WriteNMSC1],  (instregex "^F(MAX|MIN)(NM)?v")>;
834def : InstRW<[M5WriteNMSC2],  (instregex "^F(MAX|MIN)(NM)?Pv")>;
835def : InstRW<[M5WriteNEONZ],  (instregex "^F(MAX|MIN)(NM)?Vv")>;
836def : InstRW<[M5WriteFMAC3],  (instregex "^FMULX?v.[fi](16|32|64)")>;
837def : InstRW<[M5WriteFMAC4,
838              M5ReadFMACM1],  (instregex "^FML[AS]v.[fi](16|32|64)")>;
839def : InstRW<[M5WriteNALU2],  (instregex "^FNEGv.f(16|32|64)")>;
840def : InstRW<[M5WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
841def : InstRW<[M5WriteFSQR7],  (instrs FSQRTv4f16)>;
842def : InstRW<[M5WriteNEONU],  (instrs FSQRTv8f16)>;
843def : InstRW<[M5WriteFSQR8],  (instrs FSQRTv2f32)>;
844def : InstRW<[M5WriteNEONX],  (instrs FSQRTv4f32)>;
845def : InstRW<[M5WriteNEONY],  (instrs FSQRTv2f64)>;
846
847// ASIMD miscellaneous instructions.
848def : InstRW<[M5WriteNALU2],  (instregex "^RBITv")>;
849def : InstRW<[M5WriteNALU2],  (instregex "^(BIF|BIT|BSL|BSP)v")>;
850def : InstRW<[M5WriteNALU2],  (instregex "^CL[STZ]v")>;
851def : InstRW<[M5WriteNEONB],  (instregex "^DUPv.+gpr")>;
852def : InstRW<[M5WriteNSHF2],  (instregex "^DUP(i8|i16|i32|i64)$")>;
853def : InstRW<[M5WriteNSHF2],  (instregex "^DUPv.+lane")>;
854def : InstRW<[M5WriteNSHF2],  (instregex "^EXTv")>;
855def : InstRW<[M5WriteNSHT4A], (instregex "^XTNv")>;
856def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]?QXTU?Nv")>;
857def : InstRW<[M5WriteNEONB],  (instregex "^INSv.+gpr")>;
858def : InstRW<[M5WriteNSHF2],  (instregex "^INSv.+lane")>;
859def : InstRW<[M5WriteMOVI],   (instregex "^(MOV|MVN)I")>;
860def : InstRW<[M5WriteNALU1],  (instregex "^FMOVv.f(16|32|64)")>;
861def : InstRW<[M5WriteFCVT3],  (instregex "^F(RECP|RSQRT)Ev[248]f(16|32|64)")>;
862def : InstRW<[M5WriteFCVT3],  (instregex "^U(RECP|RSQRT)Ev[24]i32")>;
863def : InstRW<[M5WriteFMAC4],  (instregex "^F(RECP|RSQRT)Sv.f(16|32|64)")>;
864def : InstRW<[M5WriteNSHF2],  (instregex "^REV(16|32|64)v")>;
865def : InstRW<[M5WriteNSHFA],  (instregex "^TB[LX]v(8|16)i8One")>;
866def : InstRW<[M5WriteNSHFB],  (instregex "^TB[LX]v(8|16)i8Two")>;
867def : InstRW<[M5WriteNSHFC],  (instregex "^TB[LX]v(8|16)i8Three")>;
868def : InstRW<[M5WriteNSHFD],  (instregex "^TB[LX]v(8|16)i8Four")>;
869def : InstRW<[M5WriteNEONP],  (instregex "^[SU]MOVv")>;
870def : InstRW<[M5WriteNSHF2],  (instregex "^(TRN|UZP|ZIP)[12]v")>;
871
872// ASIMD load instructions.
873def : InstRW<[WriteVLD],    (instregex "LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
874def : InstRW<[WriteVLD,
875              M5WriteA1X,
876              WriteAdr],    (instregex "LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
877def : InstRW<[M5WriteVLDA], (instregex "LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
878def : InstRW<[M5WriteVLDA,
879              M5WriteA1X,
880              WriteAdr],    (instregex "LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
881def : InstRW<[M5WriteVLDB], (instregex "LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
882def : InstRW<[M5WriteVLDB,
883              M5WriteA1X,
884              WriteAdr],    (instregex "LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
885def : InstRW<[M5WriteVLDC], (instregex "LD1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
886def : InstRW<[M5WriteVLDC,
887              M5WriteA1X,
888              WriteAdr],    (instregex "LD1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
889def : InstRW<[M5WriteVLDD], (instregex "LD1i(8|16|32|64)$")>;
890def : InstRW<[M5WriteVLDD,
891              M5WriteA1X,
892              WriteAdr],    (instregex "LD1i(8|16|32|64)_POST$")>;
893def : InstRW<[WriteVLD],    (instregex "LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
894def : InstRW<[WriteVLD,
895              M5WriteA1X,
896              WriteAdr],    (instregex "LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
897def : InstRW<[M5WriteVLDF], (instregex "LD2Twov(8b|16b|4h|8h|2s|4s|2d)$")>;
898def : InstRW<[M5WriteVLDF,
899              M5WriteA1X,
900              WriteAdr],    (instregex "LD2Twov(8b|16b|4h|8h|2s|4s|2d)_POST$")>;
901def : InstRW<[M5WriteVLDG], (instregex "LD2i(8|16|32|64)$")>;
902def : InstRW<[M5WriteVLDG,
903              M5WriteA1X,
904              WriteAdr],    (instregex "LD2i(8|16|32|64)_POST$")>;
905def : InstRW<[M5WriteVLDA], (instregex "LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
906def : InstRW<[M5WriteVLDA,
907              M5WriteA1X,
908              WriteAdr],    (instregex "LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
909def : InstRW<[M5WriteVLDI], (instregex "LD3Threev(8b|16b|4h|8h|2s|4s|2d)$")>;
910def : InstRW<[M5WriteVLDI,
911              M5WriteA1X,
912              WriteAdr],    (instregex "LD3Threev(8b|16b|4h|8h|2s|4s|2d)_POST$")>;
913def : InstRW<[M5WriteVLDJ], (instregex "LD3i(8|16|32)$")>;
914def : InstRW<[M5WriteVLDJ,
915              M5WriteA1X,
916              WriteAdr],    (instregex "LD3i(8|16|32)_POST$")>;
917def : InstRW<[M5WriteVLDL], (instregex "LD3i64$")>;
918def : InstRW<[M5WriteVLDL,
919              M5WriteA1X,
920              WriteAdr],    (instregex "LD3i64_POST$")>;
921def : InstRW<[M5WriteVLDB], (instregex "LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
922def : InstRW<[M5WriteVLDB,
923              M5WriteA1X],  (instregex "LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
924def : InstRW<[M5WriteVLDN], (instregex "LD4Fourv(8b|16b|4h|8h|2s|4s|2d)$")>;
925def : InstRW<[M5WriteVLDN,
926              M5WriteA1X,
927              WriteAdr],    (instregex "LD4Fourv(8b|16b|4h|8h|2s|4s|2d)_POST$")>;
928def : InstRW<[M5WriteVLDK], (instregex "LD4i(8|16|32)$")>;
929def : InstRW<[M5WriteVLDK,
930              M5WriteA1X,
931              WriteAdr],    (instregex "LD4i(8|16|32)_POST$")>;
932def : InstRW<[M5WriteVLDM], (instregex "LD4i64$")>;
933def : InstRW<[M5WriteVLDM,
934              M5WriteA1X,
935              WriteAdr],    (instregex "LD4i64_POST$")>;
936def : InstRW<[M5WriteVLDC], (instregex "LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
937def : InstRW<[M5WriteVLDC,
938              M5WriteA1X,
939              WriteAdr],    (instregex "LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
940
941// ASIMD store instructions.
942def : InstRW<[WriteVST],    (instregex "ST1Onev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
943def : InstRW<[WriteVST,
944              M5WriteA1X,
945              WriteAdr],    (instregex "ST1Onev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
946def : InstRW<[M5WriteVSTA], (instregex "ST1Twov(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
947def : InstRW<[M5WriteVSTA,
948              M5WriteA1X,
949              WriteAdr],    (instregex "ST1Twov(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
950
951def : InstRW<[M5WriteVSTB], (instregex "ST1Threev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
952def : InstRW<[M5WriteVSTB,
953              M5WriteA1X,
954              WriteAdr],    (instregex "ST1Threev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
955def : InstRW<[M5WriteVSTC], (instregex "ST1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
956def : InstRW<[M5WriteVSTC,
957              M5WriteA1X,
958              WriteAdr],    (instregex "ST1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
959def : InstRW<[WriteVST],    (instregex "ST1i(8|16|32|64)$")>;
960def : InstRW<[WriteVST,
961              M5WriteA1X,
962              WriteAdr],    (instregex "ST1i(8|16|32|64)_POST$")>;
963def : InstRW<[M5WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>;
964def : InstRW<[M5WriteVSTD,
965              M5WriteA1X,
966              WriteAdr],    (instregex "ST2Twov(8b|4h|2s)_POST$")>;
967def : InstRW<[M5WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
968def : InstRW<[M5WriteVSTE,
969              M5WriteA1X,
970              WriteAdr],    (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
971def : InstRW<[M5WriteVSTD], (instregex "ST2i(8|16|32|64)$")>;
972def : InstRW<[M5WriteVSTD,
973              M5WriteA1X,
974              WriteAdr],    (instregex "ST2i(8|16|32|64)_POST$")>;
975def : InstRW<[M5WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>;
976def : InstRW<[M5WriteVSTF,
977              M5WriteA1X,
978              WriteAdr],    (instregex "ST3Threev(8b|4h|2s)_POST$")>;
979def : InstRW<[M5WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>;
980def : InstRW<[M5WriteVSTG,
981              M5WriteA1X,
982              WriteAdr],    (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>;
983def : InstRW<[M5WriteVSTA], (instregex "ST3i(8|16|32|64)$")>;
984def : InstRW<[M5WriteVSTA,
985              M5WriteA1X,
986              WriteAdr],    (instregex "ST3i(8|16|32|64)_POST$")>;
987def : InstRW<[M5WriteVSTL], (instregex "ST4Fourv(8b|4h|2s)$")>;
988def : InstRW<[M5WriteVSTL,
989              M5WriteA1X,
990              WriteAdr],    (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
991def : InstRW<[M5WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>;
992def : InstRW<[M5WriteVSTI,
993              M5WriteA1X,
994              WriteAdr],    (instregex "ST4Fourv(16b|8h|4s|2d)_POST$")>;
995def : InstRW<[M5WriteVSTA], (instregex "ST4i(8|16|32|64)$")>;
996def : InstRW<[M5WriteVSTA,
997              M5WriteA1X,
998              WriteAdr],    (instregex "ST4i(8|16|32|64)_POST$")>;
999
1000// Cryptography instructions.
1001def : InstRW<[M5WriteNCRY2],  (instregex "^AES[DE]")>;
1002def : InstRW<[M5WriteNCRY2,
1003              M5ReadAESM2],   (instregex "^AESI?MC")>;
1004def : InstRW<[M5WriteNCRY2A], (instregex "^PMULv")>;
1005def : InstRW<[M5WriteNCRY1A], (instregex "^PMULLv(1|8)i")>;
1006def : InstRW<[M5WriteNCRY3A], (instregex "^PMULLv(2|16)i")>;
1007def : InstRW<[M5WriteNCRY2A], (instregex "^SHA1(H|SU[01])")>;
1008def : InstRW<[M5WriteNCRY5A], (instregex "^SHA1[CMP]")>;
1009def : InstRW<[M5WriteNCRY2A], (instrs SHA256SU0rr)>;
1010def : InstRW<[M5WriteNCRY5A], (instrs SHA256SU1rrr)>;
1011def : InstRW<[M5WriteNCRY5A], (instregex "^SHA256H2?")>;
1012
1013// CRC instructions.
1014def : InstRW<[M5WriteF2,
1015              M5ReadFM1], (instregex "^CRC32C?[BHWX]")>;
1016
1017} // SchedModel = ExynosM5Model
1018