xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td (revision 833a452e9f082a7982a31c21f0da437dbbe0a39d)
1//=- AArch64SchedExynosM5.td - Samsung Exynos M5 Sched Defs --*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the machine model for the Samsung Exynos M5 to support
10// instruction scheduling and other instruction cost heuristics.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// The Exynos-M5 is an advanced superscalar microprocessor with a 6-wide
16// in-order stage for decode and dispatch and a wider issue stage.
17// The execution units and loads and stores are out-of-order.
18
19def ExynosM5Model : SchedMachineModel {
20  let IssueWidth            =   6; // Up to 6 uops per cycle.
21  let MicroOpBufferSize     = 228; // ROB size.
22  let LoopMicroOpBufferSize =  60; // Based on the instruction queue size.
23  let LoadLatency           =   4; // Optimistic load cases.
24  let MispredictPenalty     =  15; // Minimum branch misprediction penalty.
25  let CompleteModel         =   1; // Use the default model otherwise.
26
27  list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
28                                                    PAUnsupported.F,
29                                                    SMEUnsupported.F);
30}
31
32//===----------------------------------------------------------------------===//
33// Define each kind of processor resource and number available on the Exynos-M5.
34
35let SchedModel = ExynosM5Model in {
36
37def M5UnitA  : ProcResource<2>; // Simple integer
38def M5UnitC  : ProcResource<2>; // Simple and complex integer
39let Super =  M5UnitC, BufferSize = 1 in
40def M5UnitD  : ProcResource<1>; // Integer division (inside C0, serialized)
41def M5UnitE  : ProcResource<2>; // Simple 32-bit integer
42let Super =  M5UnitC in
43def M5UnitF  : ProcResource<2>; // CRC (inside C)
44def M5UnitB  : ProcResource<1>; // Branch
45def M5UnitL0 : ProcResource<1>; // Load
46def M5UnitS0 : ProcResource<1>; // Store
47def M5PipeLS : ProcResource<1>; // Load/Store
48let Super = M5PipeLS in {
49  def M5UnitL1 : ProcResource<1>;
50  def M5UnitS1 : ProcResource<1>;
51}
52def M5PipeF0 : ProcResource<1>; // FP #0
53let Super = M5PipeF0 in {
54  def M5UnitFMAC0 : ProcResource<1>; // FP multiplication
55  def M5UnitFADD0 : ProcResource<1>; // Simple FP
56  def M5UnitNALU0 : ProcResource<1>; // Simple vector
57  def M5UnitNDOT0 : ProcResource<1>; // Dot product vector
58  def M5UnitNHAD  : ProcResource<1>; // Horizontal vector
59  def M5UnitNMSC  : ProcResource<1>; // FP and vector miscellanea
60  def M5UnitNMUL0 : ProcResource<1>; // Vector multiplication
61  def M5UnitNSHT0 : ProcResource<1>; // Vector shifting
62  def M5UnitNSHF0 : ProcResource<1>; // Vector shuffling
63  def M5UnitNCRY0 : ProcResource<1>; // Cryptographic
64}
65def M5PipeF1 : ProcResource<1>; // FP #1
66let Super = M5PipeF1 in {
67  def M5UnitFMAC1 : ProcResource<1>; // FP multiplication
68  def M5UnitFADD1 : ProcResource<1>; // Simple FP
69  def M5UnitFCVT0 : ProcResource<1>; // FP conversion
70  def M5UnitFDIV0 : ProcResource<2>; // FP division (serialized)
71  def M5UnitFSQR0 : ProcResource<2>; // FP square root (serialized)
72  def M5UnitFST0  : ProcResource<1>; // FP store
73  def M5UnitNALU1 : ProcResource<1>; // Simple vector
74  def M5UnitNDOT1 : ProcResource<1>; // Dot product vector
75  def M5UnitNSHT1 : ProcResource<1>; // Vector shifting
76  def M5UnitNSHF1 : ProcResource<1>; // Vector shuffling
77}
78def M5PipeF2 : ProcResource<1>; // FP #2
79let Super = M5PipeF2 in {
80  def M5UnitFMAC2 : ProcResource<1>; // FP multiplication
81  def M5UnitFADD2 : ProcResource<1>; // Simple FP
82  def M5UnitFCVT1 : ProcResource<1>; // FP conversion
83  def M5UnitFDIV1 : ProcResource<2>; // FP division (serialized)
84  def M5UnitFSQR1 : ProcResource<2>; // FP square root (serialized)
85  def M5UnitFST1  : ProcResource<1>; // FP store
86  def M5UnitNALU2 : ProcResource<1>; // Simple vector
87  def M5UnitNDOT2 : ProcResource<1>; // Dot product vector
88  def M5UnitNMUL1 : ProcResource<1>; // Vector multiplication
89  def M5UnitNSHT2 : ProcResource<1>; // Vector shifting
90  def M5UnitNCRY1 : ProcResource<1>; // Cryptographic
91}
92
93def M5UnitAX    : ProcResGroup<[M5UnitA,
94                                M5UnitC]>;
95def M5UnitAW    : ProcResGroup<[M5UnitA,
96                                M5UnitC,
97                                M5UnitE]>;
98def M5UnitL     : ProcResGroup<[M5UnitL0,
99                                M5UnitL1]>;
100def M5UnitS     : ProcResGroup<[M5UnitS0,
101                                M5UnitS1]>;
102def M5UnitFMAC  : ProcResGroup<[M5UnitFMAC0,
103                                M5UnitFMAC1,
104                                M5UnitFMAC2]>;
105def M5UnitFADD  : ProcResGroup<[M5UnitFADD0,
106                                M5UnitFADD1,
107                                M5UnitFADD2]>;
108def M5UnitFCVT  : ProcResGroup<[M5UnitFCVT0,
109                                M5UnitFCVT1]>;
110def M5UnitFDIV  : ProcResGroup<[M5UnitFDIV0,
111                                M5UnitFDIV1]>;
112def M5UnitFSQR  : ProcResGroup<[M5UnitFSQR0,
113                                M5UnitFSQR1]>;
114def M5UnitFST   : ProcResGroup<[M5UnitFST0,
115                                M5UnitFST1]>;
116def M5UnitNALU  : ProcResGroup<[M5UnitNALU0,
117                                M5UnitNALU1,
118                                M5UnitNALU2]>;
119def M5UnitNDOT  : ProcResGroup<[M5UnitNDOT0,
120                                M5UnitNDOT1,
121                                M5UnitNDOT2]>;
122def M5UnitNMUL  : ProcResGroup<[M5UnitNMUL0,
123                                M5UnitNMUL1]>;
124def M5UnitNSHT  : ProcResGroup<[M5UnitNSHT0,
125                                M5UnitNSHT1,
126                                M5UnitNSHT2]>;
127def M5UnitNSHF  : ProcResGroup<[M5UnitNSHF0,
128                                M5UnitNSHF1]>;
129def M5UnitNCRY  : ProcResGroup<[M5UnitNCRY0,
130                                M5UnitNCRY1]>;
131
132//===----------------------------------------------------------------------===//
133// Resources details.
134
135def M5WriteZ0 : SchedWriteRes<[]> { let Latency = 0; }
136def M5WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
137                                    let NumMicroOps = 0; }
138def M5WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
139                                    let NumMicroOps = 0; }
140
141def M5WriteA1W : SchedWriteRes<[M5UnitAW]> { let Latency = 1; }
142def M5WriteA1X : SchedWriteRes<[M5UnitAX]> { let Latency = 1; }
143def M5WriteAAW : SchedWriteRes<[M5UnitAW]> { let Latency = 2;
144                                             let ResourceCycles = [2]; }
145def M5WriteAAX : SchedWriteRes<[M5UnitAX]> { let Latency = 2;
146                                             let ResourceCycles = [2]; }
147def M5WriteAB  : SchedWriteRes<[M5UnitAX,
148                                M5UnitC,
149                                M5UnitE]>  { let Latency = 2;
150                                             let NumMicroOps = 2; }
151def M5WriteAC  : SchedWriteRes<[M5UnitAX,
152                                M5UnitAX,
153                                M5UnitC]>  { let Latency = 3;
154                                             let NumMicroOps = 3; }
155def M5WriteAD  : SchedWriteRes<[M5UnitAW,
156                                M5UnitC]>  { let Latency = 2;
157                                              let NumMicroOps = 2; }
158def M5WriteAFW : SchedWriteRes<[M5UnitAW]> { let Latency = 2;
159                                             let NumMicroOps = 2; }
160def M5WriteAFX : SchedWriteRes<[M5UnitAX]> { let Latency = 2;
161                                             let NumMicroOps = 2; }
162def M5WriteAUW : SchedWriteVariant<[SchedVar<IsCopyIdiomPred,   [M5WriteZ0]>,
163                                    SchedVar<ExynosArithPred,   [M5WriteA1W]>,
164                                    SchedVar<ExynosLogicExPred, [M5WriteA1W]>,
165                                    SchedVar<NoSchedPred,       [M5WriteAAW]>]>;
166def M5WriteAUX : SchedWriteVariant<[SchedVar<IsCopyIdiomPred,   [M5WriteZ0]>,
167                                    SchedVar<ExynosArithPred,   [M5WriteA1X]>,
168                                    SchedVar<ExynosLogicExPred, [M5WriteA1X]>,
169                                    SchedVar<NoSchedPred,       [M5WriteAAX]>]>;
170def M5WriteAVW : SchedWriteVariant<[SchedVar<ExynosResetPred,   [M5WriteZ0]>,
171                                    SchedVar<ExynosArithPred,   [M5WriteA1W]>,
172                                    SchedVar<ExynosLogicExPred, [M5WriteA1W]>,
173                                    SchedVar<NoSchedPred,       [M5WriteAAW]>]>;
174def M5WriteAVX : SchedWriteVariant<[SchedVar<ExynosResetPred,   [M5WriteZ0]>,
175                                    SchedVar<ExynosArithPred,   [M5WriteA1X]>,
176                                    SchedVar<ExynosLogicExPred, [M5WriteA1X]>,
177                                    SchedVar<NoSchedPred,       [M5WriteAAX]>]>;
178def M5WriteAXW : SchedWriteVariant<[SchedVar<ExynosArithPred,   [M5WriteA1W]>,
179                                    SchedVar<ExynosLogicExPred, [M5WriteA1W]>,
180                                    SchedVar<NoSchedPred,       [M5WriteAAW]>]>;
181def M5WriteAXX : SchedWriteVariant<[SchedVar<ExynosArithPred,   [M5WriteA1X]>,
182                                    SchedVar<ExynosLogicExPred, [M5WriteA1X]>,
183                                    SchedVar<NoSchedPred,       [M5WriteAAX]>]>;
184def M5WriteAYW : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M5WriteA1W]>,
185                                    SchedVar<NoSchedPred,              [M5WriteAFW]>]>;
186def M5WriteAYX : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M5WriteA1X]>,
187                                    SchedVar<NoSchedPred,              [M5WriteAFX]>]>;
188
189def M5WriteB1 : SchedWriteRes<[M5UnitB]> { let Latency = 1; }
190def M5WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M5WriteAC]>,
191                                   SchedVar<NoSchedPred,            [M5WriteAB]>]>;
192
193def M5WriteC1 : SchedWriteRes<[M5UnitC]> { let Latency = 1; }
194def M5WriteC2 : SchedWriteRes<[M5UnitC]> { let Latency = 2; }
195def M5WriteCA : SchedWriteRes<[M5UnitC]> { let Latency = 3;
196                                           let ResourceCycles = [2]; }
197
198def M5WriteD10 : SchedWriteRes<[M5UnitD]> { let Latency = 10;
199                                            let ResourceCycles = [10]; }
200def M5WriteD16 : SchedWriteRes<[M5UnitD]> { let Latency = 16;
201                                            let ResourceCycles = [16]; }
202
203def M5WriteF2 : SchedWriteRes<[M5UnitF]> { let Latency = 2; }
204
205def M5WriteL4 : SchedWriteRes<[M5UnitL]> { let Latency = 4; }
206def M5WriteL5 : SchedWriteRes<[M5UnitL]> { let Latency = 5; }
207def M5WriteL6 : SchedWriteRes<[M5UnitL]> { let Latency = 6; }
208def M5WriteLA : SchedWriteRes<[M5UnitL,
209                               M5UnitL]> { let Latency = 6;
210                                           let NumMicroOps = 1; }
211def M5WriteLB : SchedWriteRes<[M5UnitAX,
212                               M5UnitL]> { let Latency = 6;
213                                           let NumMicroOps = 2; }
214def M5WriteLC : SchedWriteRes<[M5UnitAX,
215                               M5UnitL,
216                               M5UnitL]> { let Latency = 6;
217                                           let NumMicroOps = 2; }
218def M5WriteLD : SchedWriteRes<[M5UnitAX,
219                               M5UnitL]> { let Latency = 4;
220                                           let NumMicroOps = 2; }
221def M5WriteLE : SchedWriteRes<[M5UnitAX,
222                               M5UnitL]> { let Latency = 7;
223                                           let NumMicroOps = 2; }
224def M5WriteLFW : SchedWriteRes<[M5UnitAW,
225                                M5UnitAW,
226                                M5UnitAW,
227                                M5UnitAW,
228                                M5UnitL]>  { let Latency = 15;
229                                             let NumMicroOps = 6;
230                                             let ResourceCycles = [1, 1, 1, 1, 15]; }
231def M5WriteLFX : SchedWriteRes<[M5UnitAX,
232                                M5UnitAX,
233                                M5UnitAX,
234                                M5UnitAX,
235                                M5UnitL]>  { let Latency = 15;
236                                             let NumMicroOps = 6;
237                                             let ResourceCycles = [1, 1, 1, 1, 15]; }
238def M5WriteLGW : SchedWriteRes<[M5UnitAW,
239                                M5UnitL]>  { let Latency = 13;
240                                             let NumMicroOps = 1;
241                                             let ResourceCycles = [1, 13]; }
242def M5WriteLGX : SchedWriteRes<[M5UnitAX,
243                                M5UnitL]>  { let Latency = 13;
244                                             let NumMicroOps = 1;
245                                             let ResourceCycles = [1, 13]; }
246def M5WriteLH : SchedWriteRes<[]>        { let Latency = 6;
247                                           let NumMicroOps = 0; }
248def M5WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteL5]>,
249                                   SchedVar<NoSchedPred,         [M5WriteL4]>]>;
250def M5WriteLY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteLE]>,
251                                   SchedVar<NoSchedPred,         [M5WriteL6]>]>;
252
253def M5WriteS1  : SchedWriteRes<[M5UnitS]>  { let Latency = 1; }
254def M5WriteSA  : SchedWriteRes<[M5UnitS0]> { let Latency = 4; }
255def M5WriteSB  : SchedWriteRes<[M5UnitAX,
256                                M5UnitS]>  { let Latency = 2;
257                                             let NumMicroOps = 1; }
258def M5WriteSX  : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteSB]>,
259                                    SchedVar<NoSchedPred,         [M5WriteS1]>]>;
260
261def M5ReadAdrBase : SchedReadVariant<[SchedVar<
262                                        MCSchedPredicate<
263                                          CheckAny<
264                                            [ScaledIdxFn,
265                                             ExynosScaledIdxFn]>>, [ReadDefault]>,
266                                      SchedVar<NoSchedPred,        [ReadDefault]>]>;
267
268def M5WriteNEONB   : SchedWriteRes<[M5UnitNALU,
269                                    M5UnitS0]>    { let Latency = 5;
270                                                    let NumMicroOps = 2; }
271def M5WriteNEONH   : SchedWriteRes<[M5UnitNALU,
272                                    M5UnitS0]>    { let Latency = 2;
273                                                    let NumMicroOps = 2; }
274def M5WriteNEONI   : SchedWriteRes<[M5UnitS0,
275                                    M5UnitNSHF]>  { let Latency = 6;
276                                                    let NumMicroOps = 2; }
277def M5WriteNEONK   : SchedWriteRes<[M5UnitNSHF,
278                                    M5UnitFCVT0,
279                                    M5UnitS0]>    { let Latency = 5;
280                                                    let NumMicroOps = 2; }
281def M5WriteNEONN   : SchedWriteRes<[M5UnitNMSC,
282                                    M5UnitNMSC]>  { let Latency = 5;
283                                                    let NumMicroOps = 2;
284                                                    let ResourceCycles = [7, 7]; }
285def M5WriteNEONO   : SchedWriteRes<[M5UnitNMSC,
286                                    M5UnitNMSC,
287                                    M5UnitNMSC]>  { let Latency = 8;
288                                                    let NumMicroOps = 3;
289                                                    let ResourceCycles = [10, 10, 10]; }
290def M5WriteNEONP   : SchedWriteRes<[M5UnitNSHF,
291                                    M5UnitS0,
292                                    M5UnitFCVT]>  { let Latency = 7;
293                                                    let NumMicroOps = 2; }
294def M5WriteNEONQ   : SchedWriteRes<[M5UnitNMSC,
295                                    M5UnitC]>     { let Latency = 3;
296                                                    let NumMicroOps = 1; }
297def M5WriteNEONU   : SchedWriteRes<[M5UnitFSQR,
298                                    M5UnitFSQR]>  { let Latency = 7;
299                                                    let ResourceCycles = [4, 4]; }
300def M5WriteNEONV   : SchedWriteRes<[M5UnitFDIV,
301                                    M5UnitFDIV]>  { let Latency = 7;
302                                                    let ResourceCycles = [6, 6]; }
303def M5WriteNEONW   : SchedWriteRes<[M5UnitFDIV,
304                                    M5UnitFDIV]>  { let Latency = 12;
305                                                    let ResourceCycles = [9, 9]; }
306def M5WriteNEONX   : SchedWriteRes<[M5UnitFSQR,
307                                    M5UnitFSQR]>  { let Latency = 8;
308                                                    let ResourceCycles = [5, 5]; }
309def M5WriteNEONY   : SchedWriteRes<[M5UnitFSQR,
310                                    M5UnitFSQR]>  { let Latency = 12;
311                                                    let ResourceCycles = [9, 9]; }
312def M5WriteNEONZ   : SchedWriteVariant<[SchedVar<ExynosQFormPred, [M5WriteNEONO]>,
313                                        SchedVar<NoSchedPred,     [M5WriteNEONN]>]>;
314
315def M5WriteFADD2   : SchedWriteRes<[M5UnitFADD]>  { let Latency = 2; }
316
317def M5WriteFCVT2   : SchedWriteRes<[M5UnitFCVT]>  { let Latency = 2; }
318def M5WriteFCVT2A  : SchedWriteRes<[M5UnitFCVT0]> { let Latency = 2; }
319def M5WriteFCVT3   : SchedWriteRes<[M5UnitFCVT]>  { let Latency = 3; }
320def M5WriteFCVT3A  : SchedWriteRes<[M5UnitFCVT0]> { let Latency = 3; }
321def M5WriteFCVTA   : SchedWriteRes<[M5UnitFCVT0,
322                                    M5UnitS0]>    { let Latency = 3;
323                                                    let NumMicroOps = 1; }
324def M5WriteFCVTB   : SchedWriteRes<[M5UnitFCVT,
325                                    M5UnitS0]>    { let Latency = 4;
326                                                    let NumMicroOps = 1; }
327def M5WriteFCVTC   : SchedWriteRes<[M5UnitFCVT,
328                                    M5UnitS0]>    { let Latency = 6;
329                                                    let NumMicroOps = 1; }
330
331def M5WriteFDIV5   : SchedWriteRes<[M5UnitFDIV]>  { let Latency = 5;
332                                                    let ResourceCycles = [2]; }
333def M5WriteFDIV7   : SchedWriteRes<[M5UnitFDIV]>  { let Latency = 7;
334                                                    let ResourceCycles = [4]; }
335def M5WriteFDIV12  : SchedWriteRes<[M5UnitFDIV]>  { let Latency = 12;
336                                                    let ResourceCycles = [9]; }
337
338def M5WriteFMAC3   : SchedWriteRes<[M5UnitFMAC]>  { let Latency = 3; }
339def M5WriteFMAC4   : SchedWriteRes<[M5UnitFMAC]>  { let Latency = 4; }
340def M5WriteFMAC5   : SchedWriteRes<[M5UnitFMAC]>  { let Latency = 5; }
341
342def M5WriteFSQR5   : SchedWriteRes<[M5UnitFSQR]>  { let Latency = 5;
343                                                    let ResourceCycles = [2]; }
344def M5WriteFSQR7   : SchedWriteRes<[M5UnitFSQR]>  { let Latency = 7;
345                                                    let ResourceCycles = [4]; }
346def M5WriteFSQR8   : SchedWriteRes<[M5UnitFSQR]>  { let Latency = 8;
347                                                    let ResourceCycles = [5]; }
348def M5WriteFSQR12  : SchedWriteRes<[M5UnitFSQR]>  { let Latency = 12;
349                                                    let ResourceCycles = [9]; }
350
351def M5WriteNALU1   : SchedWriteRes<[M5UnitNALU]>  { let Latency = 1; }
352def M5WriteNALU2   : SchedWriteRes<[M5UnitNALU]>  { let Latency = 2; }
353
354def M5WriteNDOT2   : SchedWriteRes<[M5UnitNDOT]>  { let Latency = 2; }
355
356def M5WriteNCRY2   : SchedWriteRes<[M5UnitNCRY]>  { let Latency = 2; }
357def M5WriteNCRY1A  : SchedWriteRes<[M5UnitNCRY0]> { let Latency = 1; }
358def M5WriteNCRY2A  : SchedWriteRes<[M5UnitNCRY0]> { let Latency = 2; }
359def M5WriteNCRY3A  : SchedWriteRes<[M5UnitNCRY0]> { let Latency = 3; }
360def M5WriteNCRY5A  : SchedWriteRes<[M5UnitNCRY]>  { let Latency = 5; }
361
362def M5WriteNHAD1   : SchedWriteRes<[M5UnitNHAD]>  { let Latency = 1; }
363def M5WriteNHAD3   : SchedWriteRes<[M5UnitNHAD]>  { let Latency = 3; }
364
365def M5WriteNMSC1   : SchedWriteRes<[M5UnitNMSC]>  { let Latency = 1; }
366def M5WriteNMSC2   : SchedWriteRes<[M5UnitNMSC]>  { let Latency = 2; }
367
368def M5WriteNMUL3   : SchedWriteRes<[M5UnitNMUL]>  { let Latency = 3; }
369
370def M5WriteNSHF1   : SchedWriteRes<[M5UnitNSHF]>  { let Latency = 1; }
371def M5WriteNSHF2   : SchedWriteRes<[M5UnitNSHF]>  { let Latency = 2; }
372def M5WriteNSHFA   : SchedWriteRes<[M5UnitNSHF]>  { let Latency = 2; }
373def M5WriteNSHFB   : SchedWriteRes<[M5UnitNSHF]>  { let Latency = 4;
374                                                    let NumMicroOps = 2; }
375def M5WriteNSHFC   : SchedWriteRes<[M5UnitNSHF]>  { let Latency = 6;
376                                                    let NumMicroOps = 3; }
377def M5WriteNSHFD   : SchedWriteRes<[M5UnitNSHF]>  { let Latency = 8;
378                                                    let NumMicroOps = 4; }
379
380def M5WriteNSHT2   : SchedWriteRes<[M5UnitNSHT]>  { let Latency = 2; }
381def M5WriteNSHT4A  : SchedWriteRes<[M5UnitNSHT1]> { let Latency = 4; }
382
383def M5WriteVLDA    : SchedWriteRes<[M5UnitL,
384                                    M5UnitL]>     { let Latency = 6;
385                                                    let NumMicroOps = 2; }
386def M5WriteVLDB    : SchedWriteRes<[M5UnitL,
387                                    M5UnitL,
388                                    M5UnitL]>     { let Latency = 7;
389                                                    let NumMicroOps = 3; }
390def M5WriteVLDC    : SchedWriteRes<[M5UnitL,
391                                    M5UnitL,
392                                    M5UnitL,
393                                    M5UnitL]>     { let Latency = 7;
394                                                    let NumMicroOps = 4; }
395def M5WriteVLDD    : SchedWriteRes<[M5UnitL,
396                                    M5UnitNSHF]>  { let Latency = 7;
397                                                    let NumMicroOps = 2;
398                                                    let ResourceCycles = [2, 1]; }
399def M5WriteVLDF    : SchedWriteRes<[M5UnitL,
400                                    M5UnitL]>     { let Latency = 11;
401                                                    let NumMicroOps = 2;
402                                                    let ResourceCycles = [6, 5]; }
403def M5WriteVLDG    : SchedWriteRes<[M5UnitL,
404                                    M5UnitNSHF,
405                                    M5UnitNSHF]>  { let Latency = 7;
406                                                    let NumMicroOps = 3;
407                                                    let ResourceCycles = [2, 1, 1]; }
408def M5WriteVLDI    : SchedWriteRes<[M5UnitL,
409                                    M5UnitL,
410                                    M5UnitL]>     { let Latency = 13;
411                                                    let NumMicroOps = 3; }
412def M5WriteVLDJ    : SchedWriteRes<[M5UnitL,
413                                    M5UnitNSHF,
414                                    M5UnitNSHF,
415                                    M5UnitNSHF]>  { let Latency = 8;
416                                                    let NumMicroOps = 4; }
417def M5WriteVLDK    : SchedWriteRes<[M5UnitL,
418                                    M5UnitNSHF,
419                                    M5UnitNSHF,
420                                    M5UnitNSHF,
421                                    M5UnitNSHF]>  { let Latency = 8;
422                                                    let NumMicroOps = 5; }
423def M5WriteVLDL    : SchedWriteRes<[M5UnitL,
424                                    M5UnitNSHF,
425                                    M5UnitNSHF,
426                                    M5UnitL,
427                                    M5UnitNSHF]>  { let Latency = 8;
428                                                    let NumMicroOps = 5; }
429def M5WriteVLDM    : SchedWriteRes<[M5UnitL,
430                                    M5UnitNSHF,
431                                    M5UnitNSHF,
432                                    M5UnitL,
433                                    M5UnitNSHF,
434                                    M5UnitNSHF]>  { let Latency = 8;
435                                                    let NumMicroOps = 6; }
436def M5WriteVLDN    : SchedWriteRes<[M5UnitL,
437                                    M5UnitL,
438                                    M5UnitL,
439                                    M5UnitL]>     { let Latency = 15;
440                                                    let NumMicroOps = 4;
441                                                    let ResourceCycles = [2, 2, 2, 2]; }
442
443def M5WriteVST1    : SchedWriteRes<[M5UnitS,
444                                    M5UnitFST]> { let Latency = 1;
445                                                  let NumMicroOps = 1; }
446def M5WriteVSTA    : SchedWriteRes<[M5UnitS,
447                                    M5UnitFST,
448                                    M5UnitS,
449                                    M5UnitFST]> { let Latency = 2;
450                                                  let NumMicroOps = 2; }
451def M5WriteVSTB    : SchedWriteRes<[M5UnitS,
452                                    M5UnitFST,
453                                    M5UnitS,
454                                    M5UnitFST,
455                                    M5UnitS,
456                                    M5UnitFST]> { let Latency = 3;
457                                                  let NumMicroOps = 3; }
458def M5WriteVSTC    : SchedWriteRes<[M5UnitS,
459                                    M5UnitFST,
460                                    M5UnitS,
461                                    M5UnitFST,
462                                    M5UnitS,
463                                    M5UnitFST,
464                                    M5UnitS,
465                                    M5UnitFST]> { let Latency = 4;
466                                                  let NumMicroOps = 4; }
467def M5WriteVSTD    : SchedWriteRes<[M5UnitS,
468                                    M5UnitFST]> { let Latency = 2; }
469def M5WriteVSTE    : SchedWriteRes<[M5UnitS,
470                                    M5UnitFST,
471                                    M5UnitS,
472                                    M5UnitFST]> { let Latency = 2;
473                                                  let NumMicroOps = 1; }
474def M5WriteVSTF    : SchedWriteRes<[M5UnitNSHF,
475                                    M5UnitNSHF,
476                                    M5UnitS,
477                                    M5UnitFST]> { let Latency = 4;
478                                                  let NumMicroOps = 3; }
479def M5WriteVSTG    : SchedWriteRes<[M5UnitNSHF,
480                                    M5UnitNSHF,
481                                    M5UnitNSHF,
482                                    M5UnitS,
483                                    M5UnitFST,
484                                    M5UnitS,
485                                    M5UnitFST]> { let Latency = 4;
486                                                  let NumMicroOps = 5; }
487def M5WriteVSTH    : SchedWriteRes<[M5UnitS0,
488                                    M5UnitFST]> { let Latency = 1;
489                                                  let NumMicroOps = 1; }
490def M5WriteVSTI    : SchedWriteRes<[M5UnitNSHF,
491                                    M5UnitNSHF,
492                                    M5UnitNSHF,
493                                    M5UnitNSHF,
494                                    M5UnitS,
495                                    M5UnitFST,
496                                    M5UnitS,
497                                    M5UnitFST,
498                                    M5UnitS,
499                                    M5UnitFST,
500                                    M5UnitS,
501                                    M5UnitFST]> { let Latency = 8;
502                                                  let NumMicroOps = 5;
503                                                  let ResourceCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; }
504def M5WriteVSTJ    : SchedWriteRes<[M5UnitA,
505                                    M5UnitS0,
506                                    M5UnitFST]> { let Latency = 1;
507                                                  let NumMicroOps = 1; }
508def M5WriteVSTK    : SchedWriteRes<[M5UnitAX,
509                                    M5UnitS,
510                                    M5UnitFST]> { let Latency = 3;
511                                                  let NumMicroOps = 2; }
512def M5WriteVSTL    : SchedWriteRes<[M5UnitNSHF,
513                                    M5UnitNSHF,
514                                    M5UnitS,
515                                    M5UnitFST,
516                                    M5UnitS,
517                                    M5UnitFST]> { let Latency = 4;
518                                                    let NumMicroOps = 4;
519                                                    let ResourceCycles = [1, 1, 2, 1, 2, 1]; }
520def M5WriteVSTY   : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteVSTK]>,
521                                       SchedVar<NoSchedPred,         [WriteVST]>]>;
522
523// Special cases.
524def M5WriteCOPY    : SchedWriteVariant<[SchedVar<ExynosFPPred, [M5WriteNALU2]>,
525                                        SchedVar<NoSchedPred,  [M5WriteZ0]>]>;
526def M5WriteMOVI    : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M5WriteZ0]>,
527                                        SchedVar<NoSchedPred,       [M5WriteNALU1]>]>;
528
529// Fast forwarding.
530def M5ReadFM1      : SchedReadAdvance<+1, [M5WriteF2]>;
531def M5ReadAESM2    : SchedReadAdvance<+2, [M5WriteNCRY2]>;
532def M5ReadFMACM1   : SchedReadAdvance<+1, [M5WriteFMAC4,
533                                           M5WriteFMAC5]>;
534def M5ReadNMULM1   : SchedReadAdvance<+1, [M5WriteNMUL3]>;
535
536//===----------------------------------------------------------------------===//
537// Coarse scheduling model.
538
539// Branch instructions.
540def : SchedAlias<WriteBr,    M5WriteZ0>;
541def : SchedAlias<WriteBrReg, M5WriteC1>;
542
543// Arithmetic and logical integer instructions.
544def : SchedAlias<WriteI,     M5WriteA1W>;
545def : SchedAlias<WriteIEReg, M5WriteA1W>; // FIXME: M5WriteAX crashes TableGen.
546def : SchedAlias<WriteISReg, M5WriteA1W>; // FIXME: M5WriteAX crashes TableGen.
547def : SchedAlias<WriteIS,    M5WriteA1W>;
548
549// Move instructions.
550def : SchedAlias<WriteImm, M5WriteA1W>;
551
552// Divide and multiply instructions.
553def : SchedAlias<WriteID32, M5WriteD10>;
554def : SchedAlias<WriteID64, M5WriteD16>;
555def : SchedAlias<WriteIM32, M5WriteC2>;
556def : SchedAlias<WriteIM64, M5WriteCA>;
557
558// Miscellaneous instructions.
559def : SchedAlias<WriteExtr, M5WriteAYW>;
560
561// Addressing modes.
562def : SchedAlias<WriteAdr,    M5WriteZ1>;
563def : SchedAlias<ReadAdrBase, M5ReadAdrBase>;
564
565// Load instructions.
566def : SchedAlias<WriteLD,    M5WriteL4>;
567def : SchedAlias<WriteLDHi,  M5WriteZ4>;
568def : SchedAlias<WriteLDIdx, M5WriteLX>;
569
570// Store instructions.
571def : SchedAlias<WriteST,    M5WriteS1>;
572def : SchedAlias<WriteSTP,   M5WriteS1>;
573def : SchedAlias<WriteSTX,   M5WriteS1>;
574def : SchedAlias<WriteSTIdx, M5WriteSX>;
575
576// Atomic load and store instructions.
577def : SchedAlias<WriteAtomic, M5WriteLGW>;
578
579// FP data instructions.
580def : SchedAlias<WriteF,    M5WriteFADD2>;
581def : SchedAlias<WriteFCmp, M5WriteNMSC2>;
582def : SchedAlias<WriteFDiv, M5WriteFDIV12>;
583def : SchedAlias<WriteFMul, M5WriteFMAC3>;
584
585// FP miscellaneous instructions.
586def : SchedAlias<WriteFCvt,  M5WriteFCVT2>;
587def : SchedAlias<WriteFImm,  M5WriteNALU1>;
588def : SchedAlias<WriteFCopy, M5WriteNALU2>;
589
590// FP load instructions.
591def : SchedAlias<WriteVLD, M5WriteL6>;
592
593// FP store instructions.
594def : SchedAlias<WriteVST, M5WriteVST1>;
595
596// ASIMD FP instructions.
597def : SchedAlias<WriteV, M5WriteNALU1>;
598
599// Other miscellaneous instructions.
600def : WriteRes<WriteBarrier, []> { let Latency = 1; }
601def : WriteRes<WriteHint,    []> { let Latency = 1; }
602def : WriteRes<WriteSys,     []> { let Latency = 1; }
603
604//===----------------------------------------------------------------------===//
605// Generic fast forwarding.
606
607// TODO: Add FP register forwarding rules.
608
609def : ReadAdvance<ReadI,       0>;
610def : ReadAdvance<ReadISReg,   0>;
611def : ReadAdvance<ReadIEReg,   0>;
612def : ReadAdvance<ReadIM,      0>;
613// TODO: The forwarding for 32 bits actually saves 2 cycles.
614def : ReadAdvance<ReadIMA,     3, [WriteIM32, WriteIM64]>;
615def : ReadAdvance<ReadID,      0>;
616def : ReadAdvance<ReadExtrHi,  0>;
617def : ReadAdvance<ReadAdrBase, 0>;
618def : ReadAdvance<ReadVLD,     0>;
619
620//===----------------------------------------------------------------------===//
621// Finer scheduling model.
622
623// Branch instructions
624def : InstRW<[M5WriteB1],  (instrs Bcc)>;
625def : InstRW<[M5WriteAFX], (instrs BL)>;
626def : InstRW<[M5WriteBX],  (instrs BLR)>;
627def : InstRW<[M5WriteC1],  (instregex "^CBN?Z[WX]")>;
628def : InstRW<[M5WriteAD],  (instregex "^TBN?ZW")>;
629def : InstRW<[M5WriteAB],  (instregex "^TBN?ZX")>;
630
631// Arithmetic and logical integer instructions.
632def : InstRW<[M5WriteA1W], (instregex "^(ADC|SBC)S?Wr$")>;
633def : InstRW<[M5WriteA1X], (instregex "^(ADC|SBC)S?Xr$")>;
634def : InstRW<[M5WriteAXW], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)Wrs$")>;
635def : InstRW<[M5WriteAXX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)Xrs$")>;
636def : InstRW<[M5WriteAUW], (instrs ORRWrs)>;
637def : InstRW<[M5WriteAUX], (instrs ORRXrs)>;
638def : InstRW<[M5WriteAXW], (instregex "^(ADD|AND|BIC|SUB)SWrs$")>;
639def : InstRW<[M5WriteAXX], (instregex "^(ADD|AND|BIC|SUB)SXrs$")>;
640def : InstRW<[M5WriteAXW], (instregex "^(ADD|SUB)S?Wrx(64)?$")>;
641def : InstRW<[M5WriteAXX], (instregex "^(ADD|SUB)S?Xrx(64)?$")>;
642def : InstRW<[M5WriteAVW], (instrs ADDWri, ORRWri)>;
643def : InstRW<[M5WriteAVX], (instrs ADDXri, ORRXri)>;
644def : InstRW<[M5WriteA1W], (instregex "^CCM[NP]W[ir]$")>;
645def : InstRW<[M5WriteA1X], (instregex "^CCM[NP]X[ir]$")>;
646def : InstRW<[M5WriteA1W], (instrs CSELWr, CSINCWr, CSINVWr, CSNEGWr)>;
647def : InstRW<[M5WriteA1X], (instrs CSELXr, CSINCXr, CSINVXr, CSNEGXr)>;
648
649// Move instructions.
650def : InstRW<[M5WriteCOPY], (instrs COPY)>;
651def : InstRW<[M5WriteZ0],   (instrs ADR, ADRP)>;
652def : InstRW<[M5WriteZ0],   (instregex "^MOV[NZ][WX]i$")>;
653
654// Shift instructions.
655def : InstRW<[M5WriteA1W], (instrs ASRVWr, LSLVWr, LSRVWr, RORVWr)>;
656def : InstRW<[M5WriteA1X], (instrs ASRVXr, LSLVXr, LSRVXr, RORVXr)>;
657
658// Miscellaneous instructions.
659def : InstRW<[M5WriteAYW], (instrs EXTRWrri)>;
660def : InstRW<[M5WriteAYX], (instrs EXTRXrri)>;
661def : InstRW<[M5WriteA1W], (instrs BFMWri, SBFMWri, UBFMWri)>;
662def : InstRW<[M5WriteA1X], (instrs BFMXri, SBFMXri, UBFMXri)>;
663def : InstRW<[M5WriteA1W], (instrs CLSWr, CLZWr)>;
664def : InstRW<[M5WriteA1X], (instrs CLSXr, CLZXr)>;
665def : InstRW<[M5WriteA1W], (instrs RBITWr, REVWr, REV16Wr)>;
666def : InstRW<[M5WriteA1X], (instrs RBITXr, REVXr, REV16Xr, REV32Xr)>;
667
668// Load instructions.
669def : InstRW<[M5WriteLD,
670              WriteLDHi,
671              WriteAdr],    (instregex "^LDP(SW|W|X)(post|pre)")>;
672def : InstRW<[M5WriteL5,
673              ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
674def : InstRW<[WriteLDIdx,
675              ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
676def : InstRW<[M5WriteL5,
677              ReadAdrBase], (instrs PRFMroW)>;
678def : InstRW<[WriteLDIdx,
679              ReadAdrBase], (instrs PRFMroX)>;
680
681// Store instructions.
682def : InstRW<[M5WriteSB,
683              ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>;
684def : InstRW<[WriteST,
685              ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>;
686
687// Atomic load and store instructions.
688def : InstRW<[M5WriteLGW], (instregex "^CAS(A|AL|L)?[BHW]$")>;
689def : InstRW<[M5WriteLGX], (instregex "^CAS(A|AL|L)?X$")>;
690def : InstRW<[M5WriteLFW], (instregex "^CASP(A|AL|L)?W$")>;
691def : InstRW<[M5WriteLFX], (instregex "^CASP(A|AL|L)?X$")>;
692def : InstRW<[M5WriteLGW], (instregex "^LD(ADD|CLR|EOR|SET|[SU]MAX|[SU]MIN)(A|AL|L)?[BHW]$")>;
693def : InstRW<[M5WriteLGX], (instregex "^LD(ADD|CLR|EOR|SET|[SU]MAX|[SU]MIN)(A|AL|L)?X$")>;
694def : InstRW<[M5WriteLGW], (instregex "^SWP(A|AL|L)?[BHW]$")>;
695def : InstRW<[M5WriteLGX], (instregex "^SWP(A|AL|L)?X$")>;
696
697// FP data instructions.
698def : InstRW<[M5WriteNSHF1],  (instrs FABSHr, FABSSr,FABSDr)>;
699def : InstRW<[M5WriteFADD2],  (instregex "^F(ADD|SUB)[HSD]rr")>;
700def : InstRW<[M5WriteFADD2],  (instregex "^FADDPv.i(16|32|64)")>;
701def : InstRW<[M5WriteNEONQ],  (instregex "^FCCMPE?[HSD]rr")>;
702def : InstRW<[M5WriteNMSC2],  (instregex "^FCMPE?[HSD]r[ir]")>;
703def : InstRW<[M5WriteNMSC1],  (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)(16|32|64|v1)")>;
704def : InstRW<[M5WriteFDIV5],  (instrs FDIVHrr)>;
705def : InstRW<[M5WriteFDIV7],  (instrs FDIVSrr)>;
706def : InstRW<[M5WriteFDIV12], (instrs FDIVDrr)>;
707def : InstRW<[M5WriteNMSC1],  (instregex "^F(MAX|MIN)(NM)?[HSD]rr")>;
708def : InstRW<[M5WriteFMAC3],  (instregex "^FN?MUL[HSD]rr")>;
709def : InstRW<[M5WriteFMAC3],  (instrs FMULX16, FMULX32, FMULX64)>;
710def : InstRW<[M5WriteFMAC4,
711              M5ReadFMACM1],  (instregex "^FN?M(ADD|SUB)[HSD]rrr")>;
712def : InstRW<[M5WriteNALU2],  (instrs FNEGHr, FNEGSr, FNEGDr)>;
713def : InstRW<[M5WriteFCVT3A], (instregex "^FRINT.+r")>;
714def : InstRW<[M5WriteNEONH],  (instregex "^FCSEL[HSD]rrr")>;
715def : InstRW<[M5WriteFSQR5],  (instrs FSQRTHr)>;
716def : InstRW<[M5WriteFSQR8],  (instrs FSQRTSr)>;
717def : InstRW<[M5WriteFSQR12], (instrs FSQRTDr)>;
718
719// FP miscellaneous instructions.
720def : InstRW<[M5WriteFCVT2],  (instregex "^FCVT[HSD][HSD]r")>;
721def : InstRW<[M5WriteFCVTC],  (instregex "^[SU]CVTF[SU][XW][HSD]ri")>;
722def : InstRW<[M5WriteFCVTB],  (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>;
723def : InstRW<[M5WriteNALU1],  (instregex "^FMOV[HSD]i")>;
724def : InstRW<[M5WriteNALU2],  (instregex "^FMOV[HSD]r")>;
725def : InstRW<[M5WriteSA],     (instregex "^FMOV[WX][HSD]r")>;
726def : InstRW<[M5WriteFCVTA],  (instregex "^FMOV[HSD][WX]r")>;
727def : InstRW<[M5WriteNEONI],  (instregex "^FMOVXDHighr")>;
728def : InstRW<[M5WriteNEONK],  (instregex "^FMOVDXHighr")>;
729def : InstRW<[M5WriteFCVT3],  (instregex "^F(RECP|RSQRT)Ev1(f16|i32|i64)")>;
730def : InstRW<[M5WriteNMSC1],  (instregex "^FRECPXv1")>;
731def : InstRW<[M5WriteFMAC4],  (instregex "^F(RECP|RSQRT)S(16|32|64)")>;
732
733// FP load instructions.
734def : InstRW<[WriteVLD],    (instregex "^LDR[SDQ]l")>;
735def : InstRW<[WriteVLD],    (instregex "^LDUR[BHSDQ]i")>;
736def : InstRW<[WriteVLD,
737              WriteAdr],    (instregex "^LDR[BHSDQ](post|pre)")>;
738def : InstRW<[WriteVLD],    (instregex "^LDR[BHSDQ]ui")>;
739def : InstRW<[M5WriteLE,
740              ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>;
741def : InstRW<[WriteVLD,
742              ReadAdrBase], (instregex "^LDR[BHSD]roX")>;
743def : InstRW<[M5WriteLY,
744              ReadAdrBase], (instrs LDRQroX)>;
745def : InstRW<[WriteVLD,
746              M5WriteLH],   (instregex "^LDN?P[SD]i")>;
747def : InstRW<[M5WriteLA,
748              M5WriteLH],   (instregex "^LDN?PQi")>;
749def : InstRW<[M5WriteLB,
750              M5WriteLH,
751              WriteAdr],    (instregex "^LDP[SD](post|pre)")>;
752def : InstRW<[M5WriteLC,
753              M5WriteLH,
754              WriteAdr],    (instregex "^LDPQ(post|pre)")>;
755
756// FP store instructions.
757def : InstRW<[WriteVST],    (instregex "^STUR[BHSDQ]i")>;
758def : InstRW<[WriteVST,
759              WriteAdr],    (instregex "^STR[BHSDQ](post|pre)")>;
760def : InstRW<[WriteVST],    (instregex "^STR[BHSDQ]ui")>;
761def : InstRW<[WriteVST,
762              ReadAdrBase], (instregex "^STR[BHSD]ro[WX]")>;
763def : InstRW<[M5WriteVSTK,
764              ReadAdrBase], (instregex "^STRQroW")>;
765def : InstRW<[M5WriteVSTY,
766              ReadAdrBase], (instregex "^STRQroX")>;
767def : InstRW<[WriteVST],    (instregex "^STN?P[SD]i")>;
768def : InstRW<[M5WriteVSTH], (instregex "^STN?PQi")>;
769def : InstRW<[WriteVST,
770              WriteAdr],    (instregex "^STP[SD](post|pre)")>;
771def : InstRW<[M5WriteVSTJ,
772              WriteAdr],    (instregex "^STPQ(post|pre)")>;
773
774// ASIMD instructions.
775def : InstRW<[M5WriteNHAD1],  (instregex "^[SU]ABDL?v")>;
776def : InstRW<[M5WriteNHAD3],  (instregex "^[SU]ABAL?v")>;
777def : InstRW<[M5WriteNMSC1],  (instregex "^ABSv")>;
778def : InstRW<[M5WriteNALU2],  (instregex "^(ADD|NEG|SUB)v")>;
779def : InstRW<[M5WriteNHAD3],  (instregex "^[SU]?ADDL?Pv")>;
780def : InstRW<[M5WriteNHAD3],  (instregex "^[SU]H(ADD|SUB)v")>;
781def : InstRW<[M5WriteNHAD3],  (instregex "^[SU](ADD|SUB)[LW]v")>;
782def : InstRW<[M5WriteNHAD3],  (instregex "^R?(ADD|SUB)HN2?v")>;
783def : InstRW<[M5WriteNHAD3],  (instregex "^[SU]Q(ADD|SUB)v")>;
784def : InstRW<[M5WriteNHAD3],  (instregex "^(SU|US)QADDv")>;
785def : InstRW<[M5WriteNHAD3],  (instregex "^[SU]RHADDv")>;
786def : InstRW<[M5WriteNMSC1],  (instregex "^SQ(ABS|NEG)v")>;
787def : InstRW<[M5WriteNHAD3],  (instregex "^[SU]?ADDL?Vv")>;
788def : InstRW<[M5WriteNMSC1],  (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>;
789def : InstRW<[M5WriteNALU2],  (instregex "^CMTSTv")>;
790def : InstRW<[M5WriteNALU2],  (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>;
791def : InstRW<[M5WriteNMSC1],  (instregex "^[SU](MIN|MAX)v")>;
792def : InstRW<[M5WriteNMSC2],  (instregex "^[SU](MIN|MAX)Pv")>;
793def : InstRW<[M5WriteNHAD3],  (instregex "^[SU](MIN|MAX)Vv")>;
794def : InstRW<[M5WriteNMUL3],  (instregex "^(SQR?D)?MULH?v")>;
795def : InstRW<[M5WriteNMUL3,
796              M5ReadNMULM1],  (instregex "^ML[AS]v")>;
797def : InstRW<[M5WriteNMUL3,
798              M5ReadNMULM1],  (instregex "^SQRDML[AS]H")>;
799def : InstRW<[M5WriteNMUL3],  (instregex "^(S|U|SQD)ML[AS]L(v1(i32|i64)|v2i32|v4i16|v8i8)")>;
800def : InstRW<[M5WriteNMUL3,
801              M5ReadNMULM1],  (instregex "^(S|U|SQD)ML[AS]L(v4i32|v8i16|v16i8)")>;
802def : InstRW<[M5WriteNMUL3,
803              M5ReadNMULM1],  (instregex "^(S|U|SQD)MULL(v1(i32|i64)|v2i32|v4i16|v8i8)")>;
804def : InstRW<[M5WriteNMUL3,
805              M5ReadNMULM1],  (instregex "^(S|U|SQD)MULL(v4i32|v8i16|v16i8)")>;
806def : InstRW<[M5WriteNDOT2],  (instregex "^[SU]DOT(lane)?v")>;
807def : InstRW<[M5WriteNHAD3],  (instregex "^[SU]ADALPv")>;
808def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]R?SRA[dv]")>;
809def : InstRW<[M5WriteNSHT2],  (instregex "^SHL[dv]")>;
810def : InstRW<[M5WriteNSHT2],  (instregex "^S[LR]I[dv]")>;
811def : InstRW<[M5WriteNSHT2],  (instregex "^[SU]SH[LR][dv]")>;
812def : InstRW<[M5WriteNSHT2],  (instregex "^[SU]?SHLLv")>;
813def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]?Q?R?SHRU?N[bhsv]")>;
814def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]RSH[LR][dv]")>;
815def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]QR?SHLU?[bhsdv]")>;
816
817// ASIMD FP instructions.
818def : InstRW<[M5WriteNSHF2],  (instregex "^FABSv.f(16|32|64)")>;
819def : InstRW<[M5WriteFADD2],  (instregex "^F(ABD|ADD|SUB)v.f(16|32|64)")>;
820def : InstRW<[M5WriteFADD2],  (instregex "^FADDPv.f(16|32|64)")>;
821def : InstRW<[M5WriteNMSC1],  (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>;
822def : InstRW<[M5WriteFCVT2],  (instregex "^FCVT(L|N|XN)v")>;
823def : InstRW<[M5WriteFCVT2A], (instregex "^FCVT[AMNPZ][SU]v")>;
824def : InstRW<[M5WriteFCVT2],  (instregex "^[SU]CVTFv.[fi](16|32|64)")>;
825def : InstRW<[M5WriteFDIV7],  (instrs FDIVv4f16)>;
826def : InstRW<[M5WriteNEONV],  (instrs FDIVv8f16)>;
827def : InstRW<[M5WriteFDIV7],  (instrs FDIVv2f32)>;
828def : InstRW<[M5WriteNEONV],  (instrs FDIVv4f32)>;
829def : InstRW<[M5WriteNEONW],  (instrs FDIVv2f64)>;
830def : InstRW<[M5WriteNMSC1],  (instregex "^F(MAX|MIN)(NM)?v")>;
831def : InstRW<[M5WriteNMSC2],  (instregex "^F(MAX|MIN)(NM)?Pv")>;
832def : InstRW<[M5WriteNEONZ],  (instregex "^F(MAX|MIN)(NM)?Vv")>;
833def : InstRW<[M5WriteFMAC3],  (instregex "^FMULX?v.[fi](16|32|64)")>;
834def : InstRW<[M5WriteFMAC4,
835              M5ReadFMACM1],  (instregex "^FML[AS]v.[fi](16|32|64)")>;
836def : InstRW<[M5WriteNALU2],  (instregex "^FNEGv.f(16|32|64)")>;
837def : InstRW<[M5WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
838def : InstRW<[M5WriteFSQR7],  (instrs FSQRTv4f16)>;
839def : InstRW<[M5WriteNEONU],  (instrs FSQRTv8f16)>;
840def : InstRW<[M5WriteFSQR8],  (instrs FSQRTv2f32)>;
841def : InstRW<[M5WriteNEONX],  (instrs FSQRTv4f32)>;
842def : InstRW<[M5WriteNEONY],  (instrs FSQRTv2f64)>;
843
844// ASIMD miscellaneous instructions.
845def : InstRW<[M5WriteNALU2],  (instregex "^RBITv")>;
846def : InstRW<[M5WriteNALU2],  (instregex "^(BIF|BIT|BSL|BSP)v")>;
847def : InstRW<[M5WriteNALU2],  (instregex "^CL[STZ]v")>;
848def : InstRW<[M5WriteNEONB],  (instregex "^DUPv.+gpr")>;
849def : InstRW<[M5WriteNSHF2],  (instregex "^CPY")>;
850def : InstRW<[M5WriteNSHF2],  (instregex "^DUPv.+lane")>;
851def : InstRW<[M5WriteNSHF2],  (instregex "^EXTv")>;
852def : InstRW<[M5WriteNSHT4A], (instregex "^XTNv")>;
853def : InstRW<[M5WriteNSHT4A], (instregex "^[SU]?QXTU?Nv")>;
854def : InstRW<[M5WriteNEONB],  (instregex "^INSv.+gpr")>;
855def : InstRW<[M5WriteNSHF2],  (instregex "^INSv.+lane")>;
856def : InstRW<[M5WriteMOVI],   (instregex "^(MOV|MVN)I")>;
857def : InstRW<[M5WriteNALU1],  (instregex "^FMOVv.f(16|32|64)")>;
858def : InstRW<[M5WriteFCVT3],  (instregex "^F(RECP|RSQRT)Ev[248]f(16|32|64)")>;
859def : InstRW<[M5WriteFCVT3],  (instregex "^U(RECP|RSQRT)Ev[24]i32")>;
860def : InstRW<[M5WriteFMAC4],  (instregex "^F(RECP|RSQRT)Sv.f(16|32|64)")>;
861def : InstRW<[M5WriteNSHF2],  (instregex "^REV(16|32|64)v")>;
862def : InstRW<[M5WriteNSHFA],  (instregex "^TB[LX]v(8|16)i8One")>;
863def : InstRW<[M5WriteNSHFB],  (instregex "^TB[LX]v(8|16)i8Two")>;
864def : InstRW<[M5WriteNSHFC],  (instregex "^TB[LX]v(8|16)i8Three")>;
865def : InstRW<[M5WriteNSHFD],  (instregex "^TB[LX]v(8|16)i8Four")>;
866def : InstRW<[M5WriteNEONP],  (instregex "^[SU]MOVv")>;
867def : InstRW<[M5WriteNSHF2],  (instregex "^(TRN|UZP|ZIP)[12]v")>;
868
869// ASIMD load instructions.
870def : InstRW<[WriteVLD],    (instregex "LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
871def : InstRW<[WriteVLD,
872              M5WriteA1X,
873              WriteAdr],    (instregex "LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
874def : InstRW<[M5WriteVLDA], (instregex "LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
875def : InstRW<[M5WriteVLDA,
876              M5WriteA1X,
877              WriteAdr],    (instregex "LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
878def : InstRW<[M5WriteVLDB], (instregex "LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
879def : InstRW<[M5WriteVLDB,
880              M5WriteA1X,
881              WriteAdr],    (instregex "LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
882def : InstRW<[M5WriteVLDC], (instregex "LD1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
883def : InstRW<[M5WriteVLDC,
884              M5WriteA1X,
885              WriteAdr],    (instregex "LD1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
886def : InstRW<[M5WriteVLDD], (instregex "LD1i(8|16|32|64)$")>;
887def : InstRW<[M5WriteVLDD,
888              M5WriteA1X,
889              WriteAdr],    (instregex "LD1i(8|16|32|64)_POST$")>;
890def : InstRW<[WriteVLD],    (instregex "LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
891def : InstRW<[WriteVLD,
892              M5WriteA1X,
893              WriteAdr],    (instregex "LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
894def : InstRW<[M5WriteVLDF], (instregex "LD2Twov(8b|16b|4h|8h|2s|4s|2d)$")>;
895def : InstRW<[M5WriteVLDF,
896              M5WriteA1X,
897              WriteAdr],    (instregex "LD2Twov(8b|16b|4h|8h|2s|4s|2d)_POST$")>;
898def : InstRW<[M5WriteVLDG], (instregex "LD2i(8|16|32|64)$")>;
899def : InstRW<[M5WriteVLDG,
900              M5WriteA1X,
901              WriteAdr],    (instregex "LD2i(8|16|32|64)_POST$")>;
902def : InstRW<[M5WriteVLDA], (instregex "LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
903def : InstRW<[M5WriteVLDA,
904              M5WriteA1X,
905              WriteAdr],    (instregex "LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
906def : InstRW<[M5WriteVLDI], (instregex "LD3Threev(8b|16b|4h|8h|2s|4s|2d)$")>;
907def : InstRW<[M5WriteVLDI,
908              M5WriteA1X,
909              WriteAdr],    (instregex "LD3Threev(8b|16b|4h|8h|2s|4s|2d)_POST$")>;
910def : InstRW<[M5WriteVLDJ], (instregex "LD3i(8|16|32)$")>;
911def : InstRW<[M5WriteVLDJ,
912              M5WriteA1X,
913              WriteAdr],    (instregex "LD3i(8|16|32)_POST$")>;
914def : InstRW<[M5WriteVLDL], (instregex "LD3i64$")>;
915def : InstRW<[M5WriteVLDL,
916              M5WriteA1X,
917              WriteAdr],    (instregex "LD3i64_POST$")>;
918def : InstRW<[M5WriteVLDB], (instregex "LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
919def : InstRW<[M5WriteVLDB,
920              M5WriteA1X],  (instregex "LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
921def : InstRW<[M5WriteVLDN], (instregex "LD4Fourv(8b|16b|4h|8h|2s|4s|2d)$")>;
922def : InstRW<[M5WriteVLDN,
923              M5WriteA1X,
924              WriteAdr],    (instregex "LD4Fourv(8b|16b|4h|8h|2s|4s|2d)_POST$")>;
925def : InstRW<[M5WriteVLDK], (instregex "LD4i(8|16|32)$")>;
926def : InstRW<[M5WriteVLDK,
927              M5WriteA1X,
928              WriteAdr],    (instregex "LD4i(8|16|32)_POST$")>;
929def : InstRW<[M5WriteVLDM], (instregex "LD4i64$")>;
930def : InstRW<[M5WriteVLDM,
931              M5WriteA1X,
932              WriteAdr],    (instregex "LD4i64_POST$")>;
933def : InstRW<[M5WriteVLDC], (instregex "LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
934def : InstRW<[M5WriteVLDC,
935              M5WriteA1X,
936              WriteAdr],    (instregex "LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
937
938// ASIMD store instructions.
939def : InstRW<[WriteVST],    (instregex "ST1Onev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
940def : InstRW<[WriteVST,
941              M5WriteA1X,
942              WriteAdr],    (instregex "ST1Onev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
943def : InstRW<[M5WriteVSTA], (instregex "ST1Twov(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
944def : InstRW<[M5WriteVSTA,
945              M5WriteA1X,
946              WriteAdr],    (instregex "ST1Twov(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
947
948def : InstRW<[M5WriteVSTB], (instregex "ST1Threev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
949def : InstRW<[M5WriteVSTB,
950              M5WriteA1X,
951              WriteAdr],    (instregex "ST1Threev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
952def : InstRW<[M5WriteVSTC], (instregex "ST1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
953def : InstRW<[M5WriteVSTC,
954              M5WriteA1X,
955              WriteAdr],    (instregex "ST1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
956def : InstRW<[WriteVST],    (instregex "ST1i(8|16|32|64)$")>;
957def : InstRW<[WriteVST,
958              M5WriteA1X,
959              WriteAdr],    (instregex "ST1i(8|16|32|64)_POST$")>;
960def : InstRW<[M5WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>;
961def : InstRW<[M5WriteVSTD,
962              M5WriteA1X,
963              WriteAdr],    (instregex "ST2Twov(8b|4h|2s)_POST$")>;
964def : InstRW<[M5WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
965def : InstRW<[M5WriteVSTE,
966              M5WriteA1X,
967              WriteAdr],    (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
968def : InstRW<[M5WriteVSTD], (instregex "ST2i(8|16|32|64)$")>;
969def : InstRW<[M5WriteVSTD,
970              M5WriteA1X,
971              WriteAdr],    (instregex "ST2i(8|16|32|64)_POST$")>;
972def : InstRW<[M5WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>;
973def : InstRW<[M5WriteVSTF,
974              M5WriteA1X,
975              WriteAdr],    (instregex "ST3Threev(8b|4h|2s)_POST$")>;
976def : InstRW<[M5WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>;
977def : InstRW<[M5WriteVSTG,
978              M5WriteA1X,
979              WriteAdr],    (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>;
980def : InstRW<[M5WriteVSTA], (instregex "ST3i(8|16|32|64)$")>;
981def : InstRW<[M5WriteVSTA,
982              M5WriteA1X,
983              WriteAdr],    (instregex "ST3i(8|16|32|64)_POST$")>;
984def : InstRW<[M5WriteVSTL], (instregex "ST4Fourv(8b|4h|2s)$")>;
985def : InstRW<[M5WriteVSTL,
986              M5WriteA1X,
987              WriteAdr],    (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
988def : InstRW<[M5WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>;
989def : InstRW<[M5WriteVSTI,
990              M5WriteA1X,
991              WriteAdr],    (instregex "ST4Fourv(16b|8h|4s|2d)_POST$")>;
992def : InstRW<[M5WriteVSTA], (instregex "ST4i(8|16|32|64)$")>;
993def : InstRW<[M5WriteVSTA,
994              M5WriteA1X,
995              WriteAdr],    (instregex "ST4i(8|16|32|64)_POST$")>;
996
997// Cryptography instructions.
998def : InstRW<[M5WriteNCRY2],  (instregex "^AES[DE]")>;
999def : InstRW<[M5WriteNCRY2,
1000              M5ReadAESM2],   (instregex "^AESI?MC")>;
1001def : InstRW<[M5WriteNCRY2A], (instregex "^PMULv")>;
1002def : InstRW<[M5WriteNCRY1A], (instregex "^PMULLv(1|8)i")>;
1003def : InstRW<[M5WriteNCRY3A], (instregex "^PMULLv(2|16)i")>;
1004def : InstRW<[M5WriteNCRY2A], (instregex "^SHA1(H|SU[01])")>;
1005def : InstRW<[M5WriteNCRY5A], (instregex "^SHA1[CMP]")>;
1006def : InstRW<[M5WriteNCRY2A], (instrs SHA256SU0rr)>;
1007def : InstRW<[M5WriteNCRY5A], (instrs SHA256SU1rrr)>;
1008def : InstRW<[M5WriteNCRY5A], (instregex "^SHA256H2?")>;
1009
1010// CRC instructions.
1011def : InstRW<[M5WriteF2,
1012              M5ReadFM1], (instregex "^CRC32C?[BHWX]")>;
1013
1014} // SchedModel = ExynosM5Model
1015