1//=- AArch64SchedExynosM4.td - Samsung Exynos M4 Sched Defs --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for the Samsung Exynos M4 to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// The Exynos-M4 is an advanced superscalar microprocessor with a 6-wide 16// in-order stage for decode and dispatch and a wider issue stage. 17// The execution units and loads and stores are out-of-order. 18 19def ExynosM4Model : SchedMachineModel { 20 let IssueWidth = 6; // Up to 6 uops per cycle. 21 let MicroOpBufferSize = 228; // ROB size. 22 let LoopMicroOpBufferSize = 48; // Based on the instruction queue size. 23 let LoadLatency = 4; // Optimistic load cases. 24 let MispredictPenalty = 16; // Minimum branch misprediction penalty. 25 let CompleteModel = 1; // Use the default model otherwise. 26 27 list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F, 28 PAUnsupported.F, 29 SMEUnsupported.F, 30 [HasMTE]); 31} 32 33//===----------------------------------------------------------------------===// 34// Define each kind of processor resource and number available on the Exynos-M4. 35 36let SchedModel = ExynosM4Model in { 37 38def M4UnitA : ProcResource<2>; // Simple integer 39def M4UnitC : ProcResource<2>; // Simple and complex integer 40let Super = M4UnitC, BufferSize = 1 in 41def M4UnitD : ProcResource<1>; // Integer division (inside C0, serialized) 42let Super = M4UnitC in 43def M4UnitE : ProcResource<1>; // CRC (inside C0) 44def M4UnitB : ProcResource<2>; // Branch 45def M4UnitL0 : ProcResource<1>; // Load 46def M4UnitS0 : ProcResource<1>; // Store 47def M4PipeLS : ProcResource<1>; // Load/Store 48let Super = M4PipeLS in { 49 def M4UnitL1 : ProcResource<1>; 50 def M4UnitS1 : ProcResource<1>; 51} 52def M4PipeF0 : ProcResource<1>; // FP #0 53let Super = M4PipeF0 in { 54 def M4UnitFMAC0 : ProcResource<1>; // FP multiplication 55 def M4UnitFADD0 : ProcResource<1>; // Simple FP 56 def M4UnitFCVT0 : ProcResource<1>; // FP conversion 57 def M4UnitNALU0 : ProcResource<1>; // Simple vector 58 def M4UnitNHAD : ProcResource<1>; // Horizontal vector 59 def M4UnitNMSC : ProcResource<1>; // FP and vector miscellanea 60 def M4UnitNMUL0 : ProcResource<1>; // Vector multiplication 61 def M4UnitNSHT0 : ProcResource<1>; // Vector shifting 62 def M4UnitNSHF0 : ProcResource<1>; // Vector shuffling 63 def M4UnitNCRY0 : ProcResource<1>; // Cryptographic 64} 65def M4PipeF1 : ProcResource<1>; // FP #1 66let Super = M4PipeF1 in { 67 def M4UnitFMAC1 : ProcResource<1>; // FP multiplication 68 def M4UnitFADD1 : ProcResource<1>; // Simple FP 69 def M4UnitFDIV0 : ProcResource<2>; // FP division (serialized) 70 def M4UnitFSQR0 : ProcResource<2>; // FP square root (serialized) 71 def M4UnitFST0 : ProcResource<1>; // FP store 72 def M4UnitNALU1 : ProcResource<1>; // Simple vector 73 def M4UnitNSHT1 : ProcResource<1>; // Vector shifting 74 def M4UnitNSHF1 : ProcResource<1>; // Vector shuffling 75} 76def M4PipeF2 : ProcResource<1>; // FP #2 77let Super = M4PipeF2 in { 78 def M4UnitFMAC2 : ProcResource<1>; // FP multiplication 79 def M4UnitFADD2 : ProcResource<1>; // Simple FP 80 def M4UnitFCVT1 : ProcResource<1>; // FP conversion 81 def M4UnitFDIV1 : ProcResource<2>; // FP division (serialized) 82 def M4UnitFSQR1 : ProcResource<2>; // FP square root (serialized) 83 def M4UnitFST1 : ProcResource<1>; // FP store 84 def M4UnitNALU2 : ProcResource<1>; // Simple vector 85 def M4UnitNMUL1 : ProcResource<1>; // Vector multiplication 86 def M4UnitNSHT2 : ProcResource<1>; // Vector shifting 87 def M4UnitNCRY1 : ProcResource<1>; // Cryptographic 88} 89 90def M4UnitALU : ProcResGroup<[M4UnitA, 91 M4UnitC]>; 92def M4UnitL : ProcResGroup<[M4UnitL0, 93 M4UnitL1]>; 94def M4UnitS : ProcResGroup<[M4UnitS0, 95 M4UnitS1]>; 96def M4UnitFMAC : ProcResGroup<[M4UnitFMAC0, 97 M4UnitFMAC1, 98 M4UnitFMAC2]>; 99def M4UnitFMACH : ProcResGroup<[M4UnitFMAC0, 100 M4UnitFMAC1]>; 101def M4UnitFADD : ProcResGroup<[M4UnitFADD0, 102 M4UnitFADD1, 103 M4UnitFADD2]>; 104def M4UnitFADDH : ProcResGroup<[M4UnitFADD0, 105 M4UnitFADD1]>; 106def M4UnitFCVT : ProcResGroup<[M4UnitFCVT0, 107 M4UnitFCVT1]>; 108def M4UnitFCVTH : ProcResGroup<[M4UnitFCVT0]>; 109def M4UnitFDIV : ProcResGroup<[M4UnitFDIV0, 110 M4UnitFDIV1]>; 111def M4UnitFDIVH : ProcResGroup<[M4UnitFDIV0]>; 112def M4UnitFSQR : ProcResGroup<[M4UnitFSQR0, 113 M4UnitFSQR1]>; 114def M4UnitFSQRH : ProcResGroup<[M4UnitFSQR0]>; 115def M4UnitFST : ProcResGroup<[M4UnitFST0, 116 M4UnitFST1]>; 117def M4UnitNALU : ProcResGroup<[M4UnitNALU0, 118 M4UnitNALU1, 119 M4UnitNALU2]>; 120def M4UnitNALUH : ProcResGroup<[M4UnitNALU0, 121 M4UnitNALU1]>; 122def M4UnitNMUL : ProcResGroup<[M4UnitNMUL0, 123 M4UnitNMUL1]>; 124def M4UnitNSHT : ProcResGroup<[M4UnitNSHT0, 125 M4UnitNSHT1, 126 M4UnitNSHT2]>; 127def M4UnitNSHF : ProcResGroup<[M4UnitNSHF0, 128 M4UnitNSHF1]>; 129def M4UnitNSHFH : ProcResGroup<[M4UnitNSHF0]>; 130def M4UnitNCRY : ProcResGroup<[M4UnitNCRY0, 131 M4UnitNCRY1]>; 132 133//===----------------------------------------------------------------------===// 134// Resources details. 135 136def M4WriteZ0 : SchedWriteRes<[]> { let Latency = 0; } 137def M4WriteZ1 : SchedWriteRes<[]> { let Latency = 1; 138 let NumMicroOps = 0; } 139def M4WriteZ4 : SchedWriteRes<[]> { let Latency = 4; 140 let NumMicroOps = 0; } 141 142def M4WriteA1 : SchedWriteRes<[M4UnitALU]> { let Latency = 1; } 143def M4WriteA2 : SchedWriteRes<[M4UnitALU]> { let Latency = 2; } 144def M4WriteAA : SchedWriteRes<[M4UnitALU]> { let Latency = 2; 145 let ResourceCycles = [2]; } 146def M4WriteAB : SchedWriteRes<[M4UnitALU, 147 M4UnitC]> { let Latency = 2; 148 let NumMicroOps = 2; } 149def M4WriteAC : SchedWriteRes<[M4UnitALU, 150 M4UnitALU, 151 M4UnitC]> { let Latency = 3; 152 let NumMicroOps = 3; } 153def M4WriteAD : SchedWriteRes<[M4UnitALU, 154 M4UnitC]> { let Latency = 2; 155 let NumMicroOps = 2; } 156def M4WriteAF : SchedWriteRes<[M4UnitALU]> { let Latency = 2; 157 let NumMicroOps = 2; } 158def M4WriteAU : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M4WriteZ0]>, 159 SchedVar<ExynosArithPred, [M4WriteA1]>, 160 SchedVar<ExynosLogicExPred, [M4WriteA1]>, 161 SchedVar<NoSchedPred, [M4WriteAA]>]>; 162def M4WriteAV : SchedWriteVariant<[SchedVar<ExynosResetPred, [M4WriteZ0]>, 163 SchedVar<ExynosArithPred, [M4WriteA1]>, 164 SchedVar<ExynosLogicExPred, [M4WriteA1]>, 165 SchedVar<NoSchedPred, [M4WriteAA]>]>; 166def M4WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M4WriteA1]>, 167 SchedVar<ExynosLogicExPred, [M4WriteA1]>, 168 SchedVar<NoSchedPred, [M4WriteAA]>]>; 169def M4WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M4WriteA1]>, 170 SchedVar<NoSchedPred, [M4WriteAF]>]>; 171 172def M4WriteB1 : SchedWriteRes<[M4UnitB]> { let Latency = 1; } 173def M4WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M4WriteAC]>, 174 SchedVar<NoSchedPred, [M4WriteAB]>]>; 175 176def M4WriteC1 : SchedWriteRes<[M4UnitC]> { let Latency = 1; } 177def M4WriteC3 : SchedWriteRes<[M4UnitC]> { let Latency = 3; } 178def M4WriteCA : SchedWriteRes<[M4UnitC]> { let Latency = 4; 179 let ResourceCycles = [2]; } 180 181def M4WriteD12 : SchedWriteRes<[M4UnitD]> { let Latency = 12; 182 let ResourceCycles = [12]; } 183def M4WriteD21 : SchedWriteRes<[M4UnitD]> { let Latency = 21; 184 let ResourceCycles = [21]; } 185 186def M4WriteE2 : SchedWriteRes<[M4UnitE]> { let Latency = 2; } 187 188def M4WriteL4 : SchedWriteRes<[M4UnitL]> { let Latency = 4; } 189def M4WriteL5 : SchedWriteRes<[M4UnitL]> { let Latency = 5; } 190def M4WriteLA : SchedWriteRes<[M4UnitL, 191 M4UnitL]> { let Latency = 5; 192 let NumMicroOps = 1; } 193def M4WriteLB : SchedWriteRes<[M4UnitA, 194 M4UnitL]> { let Latency = 5; 195 let NumMicroOps = 2; } 196def M4WriteLC : SchedWriteRes<[M4UnitA, 197 M4UnitL, 198 M4UnitL]> { let Latency = 5; 199 let NumMicroOps = 2; } 200def M4WriteLD : SchedWriteRes<[M4UnitA, 201 M4UnitL]> { let Latency = 4; 202 let NumMicroOps = 2; } 203def M4WriteLE : SchedWriteRes<[M4UnitA, 204 M4UnitL]> { let Latency = 6; 205 let NumMicroOps = 2; } 206def M4WriteLH : SchedWriteRes<[]> { let Latency = 5; 207 let NumMicroOps = 0; } 208def M4WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteL5]>, 209 SchedVar<NoSchedPred, [M4WriteL4]>]>; 210def M4WriteLY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteLE]>, 211 SchedVar<NoSchedPred, [M4WriteL5]>]>; 212 213def M4WriteS1 : SchedWriteRes<[M4UnitS]> { let Latency = 1; } 214def M4WriteSA : SchedWriteRes<[M4UnitS0]> { let Latency = 3; } 215def M4WriteSB : SchedWriteRes<[M4UnitA, 216 M4UnitS]> { let Latency = 2; 217 let NumMicroOps = 1; } 218def M4WriteSX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteSB]>, 219 SchedVar<NoSchedPred, [M4WriteS1]>]>; 220 221def M4ReadAdrBase : SchedReadVariant<[SchedVar< 222 MCSchedPredicate< 223 CheckAny< 224 [ScaledIdxFn, 225 ExynosScaledIdxFn]>>, [ReadDefault]>, 226 SchedVar<NoSchedPred, [ReadDefault]>]>; 227 228def M4WriteNEONA : SchedWriteRes<[M4UnitNSHF, 229 M4UnitFADD]> { let Latency = 3; 230 let NumMicroOps = 2; } 231def M4WriteNEONB : SchedWriteRes<[M4UnitNALU, 232 M4UnitS0]> { let Latency = 5; 233 let NumMicroOps = 2; } 234def M4WriteNEOND : SchedWriteRes<[M4UnitNSHF, 235 M4UnitFST]> { let Latency = 6; 236 let NumMicroOps = 2; } 237def M4WriteNEONH : SchedWriteRes<[M4UnitNALU, 238 M4UnitS0]> { let Latency = 5; 239 let NumMicroOps = 2; } 240def M4WriteNEONI : SchedWriteRes<[M4UnitNSHF, 241 M4UnitS0]> { let Latency = 2; 242 let NumMicroOps = 2; } 243def M4WriteNEONJ : SchedWriteRes<[M4UnitNMSC, 244 M4UnitS0]> { let Latency = 4; } 245def M4WriteNEONK : SchedWriteRes<[M4UnitNSHF, 246 M4UnitNMSC, 247 M4UnitS0]> { let Latency = 5; 248 let NumMicroOps = 2; } 249def M4WriteNEONL : SchedWriteRes<[M4UnitNMUL]> { let Latency = 3; } 250def M4WriteNEONN : SchedWriteRes<[M4UnitNMSC, 251 M4UnitNMSC]> { let Latency = 5; 252 let NumMicroOps = 2; } 253def M4WriteNEONO : SchedWriteRes<[M4UnitNMSC, 254 M4UnitNMSC, 255 M4UnitNMSC]> { let Latency = 8; 256 let NumMicroOps = 3; } 257def M4WriteNEONP : SchedWriteRes<[M4UnitNSHF, 258 M4UnitNMSC]> { let Latency = 4; 259 let NumMicroOps = 2; } 260def M4WriteNEONQ : SchedWriteRes<[M4UnitNMSC, 261 M4UnitC]> { let Latency = 3; 262 let NumMicroOps = 1; } 263def M4WriteNEONR : SchedWriteRes<[M4UnitFCVT0, 264 M4UnitS0]> { let Latency = 4; 265 let NumMicroOps = 1; } 266def M4WriteNEONV : SchedWriteRes<[M4UnitFDIV, 267 M4UnitFDIV]> { let Latency = 7; 268 let ResourceCycles = [6, 6]; } 269def M4WriteNEONVH : SchedWriteRes<[M4UnitFDIVH, 270 M4UnitFDIVH]> { let Latency = 7; 271 let ResourceCycles = [6, 6]; } 272def M4WriteNEONW : SchedWriteRes<[M4UnitFDIV, 273 M4UnitFDIV]> { let Latency = 12; 274 let ResourceCycles = [9, 9]; } 275def M4WriteNEONX : SchedWriteRes<[M4UnitFSQR, 276 M4UnitFSQR]> { let Latency = 8; 277 let ResourceCycles = [7, 7]; } 278def M4WriteNEONXH : SchedWriteRes<[M4UnitFSQRH, 279 M4UnitFSQRH]> { let Latency = 7; 280 let ResourceCycles = [6, 6]; } 281def M4WriteNEONY : SchedWriteRes<[M4UnitFSQR, 282 M4UnitFSQR]> { let Latency = 12; 283 let ResourceCycles = [9, 9]; } 284def M4WriteNEONZ : SchedWriteVariant<[SchedVar<ExynosQFormPred, [M4WriteNEONO]>, 285 SchedVar<NoSchedPred, [M4WriteNEONN]>]>; 286 287def M4WriteFADD2 : SchedWriteRes<[M4UnitFADD]> { let Latency = 2; } 288def M4WriteFADD2H : SchedWriteRes<[M4UnitFADDH]> { let Latency = 2; } 289 290def M4WriteFCVT2 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 2; } 291def M4WriteFCVT2A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 2; } 292def M4WriteFCVT2H : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 2; } 293def M4WriteFCVT3 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 3; } 294def M4WriteFCVT3A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 3; } 295def M4WriteFCVT3H : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 3; } 296def M4WriteFCVT4 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 4; } 297def M4WriteFCVT4A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 4; } 298def M4WriteFCVT6A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 6; } 299 300def M4WriteFDIV7 : SchedWriteRes<[M4UnitFDIV]> { let Latency = 7; 301 let ResourceCycles = [6]; } 302def M4WriteFDIV7H : SchedWriteRes<[M4UnitFDIVH]> { let Latency = 7; 303 let ResourceCycles = [6]; } 304def M4WriteFDIV12 : SchedWriteRes<[M4UnitFDIV]> { let Latency = 12; 305 let ResourceCycles = [9]; } 306 307def M4WriteFMAC2H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 2; } 308def M4WriteFMAC3H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 3; } 309def M4WriteFMAC3 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 3; } 310def M4WriteFMAC4 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 4; } 311def M4WriteFMAC4H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 4; } 312def M4WriteFMAC5 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 5; } 313 314def M4WriteFSQR7H : SchedWriteRes<[M4UnitFSQRH]> { let Latency = 7; 315 let ResourceCycles = [6]; } 316def M4WriteFSQR8 : SchedWriteRes<[M4UnitFSQR]> { let Latency = 8; 317 let ResourceCycles = [7]; } 318def M4WriteFSQR12 : SchedWriteRes<[M4UnitFSQR]> { let Latency = 12; 319 let ResourceCycles = [9]; } 320 321def M4WriteNALU1 : SchedWriteRes<[M4UnitNALU]> { let Latency = 1; } 322def M4WriteNALU1H : SchedWriteRes<[M4UnitNALUH]> { let Latency = 1; } 323 324def M4WriteNCRY1 : SchedWriteRes<[M4UnitNCRY]> { let Latency = 1; } 325def M4WriteNCRY1A : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 1; } 326def M4WriteNCRY3A : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 3; } 327def M4WriteNCRY5A : SchedWriteRes<[M4UnitNCRY]> { let Latency = 5; } 328 329def M4WriteNHAD1 : SchedWriteRes<[M4UnitNHAD]> { let Latency = 1; } 330def M4WriteNHAD3 : SchedWriteRes<[M4UnitNHAD]> { let Latency = 3; } 331 332def M4WriteNMSC1 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 1; } 333def M4WriteNMSC2 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 2; } 334def M4WriteNMSC3 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 3; } 335 336def M4WriteNMUL3 : SchedWriteRes<[M4UnitNMUL]> { let Latency = 3; } 337 338def M4WriteNSHF1 : SchedWriteRes<[M4UnitNSHF]> { let Latency = 1; } 339def M4WriteNSHF1H : SchedWriteRes<[M4UnitNSHFH]> { let Latency = 1; } 340def M4WriteNSHF3 : SchedWriteRes<[M4UnitNSHF]> { let Latency = 3; } 341def M4WriteNSHFA : SchedWriteRes<[M4UnitNSHF]> { let Latency = 1; 342 let ResourceCycles = [2]; } 343def M4WriteNSHFB : SchedWriteRes<[M4UnitNSHF]> { let Latency = 2; 344 let NumMicroOps = 2; 345 let ResourceCycles = [2]; } 346def M4WriteNSHFC : SchedWriteRes<[M4UnitNSHF]> { let Latency = 3; 347 let NumMicroOps = 3; 348 let ResourceCycles = [4]; } 349def M4WriteNSHFD : SchedWriteRes<[M4UnitNSHF]> { let Latency = 4; 350 let NumMicroOps = 4; 351 let ResourceCycles = [4]; } 352 353def M4WriteNSHT1 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 1; } 354def M4WriteNSHT2 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 2; } 355def M4WriteNSHT3 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 3; } 356def M4WriteNSHT4A : SchedWriteRes<[M4UnitNSHT1]> { let Latency = 4; } 357 358def M4WriteVLDA : SchedWriteRes<[M4UnitL, 359 M4UnitL]> { let Latency = 5; 360 let NumMicroOps = 2; } 361def M4WriteVLDB : SchedWriteRes<[M4UnitL, 362 M4UnitL, 363 M4UnitL]> { let Latency = 6; 364 let NumMicroOps = 3; } 365def M4WriteVLDC : SchedWriteRes<[M4UnitL, 366 M4UnitL, 367 M4UnitL, 368 M4UnitL]> { let Latency = 6; 369 let NumMicroOps = 4; } 370def M4WriteVLDD : SchedWriteRes<[M4UnitL, 371 M4UnitNSHF]> { let Latency = 6; 372 let NumMicroOps = 2; 373 let ResourceCycles = [2, 1]; } 374def M4WriteVLDF : SchedWriteRes<[M4UnitL, 375 M4UnitL]> { let Latency = 10; 376 let NumMicroOps = 2; 377 let ResourceCycles = [3, 3]; } 378def M4WriteVLDG : SchedWriteRes<[M4UnitL, 379 M4UnitNSHF, 380 M4UnitNSHF]> { let Latency = 6; 381 let NumMicroOps = 3; 382 let ResourceCycles = [2, 1, 1]; } 383def M4WriteVLDI : SchedWriteRes<[M4UnitL, 384 M4UnitL, 385 M4UnitL]> { let Latency = 12; 386 let NumMicroOps = 3; 387 let ResourceCycles = [3, 3, 3]; } 388def M4WriteVLDJ : SchedWriteRes<[M4UnitL, 389 M4UnitNSHF, 390 M4UnitNSHF, 391 M4UnitNSHF]> { let Latency = 7; 392 let NumMicroOps = 4; 393 let ResourceCycles = [3, 1, 1, 1]; } 394def M4WriteVLDK : SchedWriteRes<[M4UnitL, 395 M4UnitNSHF, 396 M4UnitNSHF, 397 M4UnitNSHF, 398 M4UnitNSHF]> { let Latency = 7; 399 let NumMicroOps = 5; 400 let ResourceCycles = [3, 1, 1, 1, 1]; } 401def M4WriteVLDL : SchedWriteRes<[M4UnitL, 402 M4UnitNSHF, 403 M4UnitNSHF, 404 M4UnitL, 405 M4UnitNSHF]> { let Latency = 7; 406 let NumMicroOps = 5; 407 let ResourceCycles = [3, 1, 1, 6, 1]; } 408def M4WriteVLDM : SchedWriteRes<[M4UnitL, 409 M4UnitNSHF, 410 M4UnitNSHF, 411 M4UnitL, 412 M4UnitNSHF, 413 M4UnitNSHF]> { let Latency = 7; 414 let NumMicroOps = 6; 415 let ResourceCycles = [3, 1, 1, 3, 1, 1]; } 416def M4WriteVLDN : SchedWriteRes<[M4UnitL, 417 M4UnitL, 418 M4UnitL, 419 M4UnitL]> { let Latency = 14; 420 let NumMicroOps = 4; 421 let ResourceCycles = [3, 3, 3, 3]; } 422 423def M4WriteVST1 : SchedWriteRes<[M4UnitS, 424 M4UnitFST]> { let Latency = 1; 425 let NumMicroOps = 1; } 426def M4WriteVSTA : WriteSequence<[WriteVST], 2>; 427def M4WriteVSTB : WriteSequence<[WriteVST], 3>; 428def M4WriteVSTC : WriteSequence<[WriteVST], 4>; 429def M4WriteVSTD : SchedWriteRes<[M4UnitS, 430 M4UnitFST]> { let Latency = 2; } 431def M4WriteVSTE : SchedWriteRes<[M4UnitS, 432 M4UnitFST, 433 M4UnitS, 434 M4UnitFST]> { let Latency = 2; 435 let NumMicroOps = 2; } 436def M4WriteVSTF : SchedWriteRes<[M4UnitNSHF, 437 M4UnitS, 438 M4UnitFST, 439 M4UnitS, 440 M4UnitFST]> { let Latency = 4; 441 let NumMicroOps = 4; 442 let ResourceCycles = [1, 2, 1, 2, 1]; } 443def M4WriteVSTG : SchedWriteRes<[M4UnitNSHF, 444 M4UnitNSHF, 445 M4UnitNSHF, 446 M4UnitS, 447 M4UnitFST, 448 M4UnitS, 449 M4UnitFST, 450 M4UnitS, 451 M4UnitFST]> { let Latency = 5; 452 let NumMicroOps = 6; 453 let ResourceCycles = [1, 1, 1, 2, 1, 2, 1, 2, 1]; } 454def M4WriteVSTI : SchedWriteRes<[M4UnitNSHF, 455 M4UnitNSHF, 456 M4UnitNSHF, 457 M4UnitNSHF, 458 M4UnitS, 459 M4UnitFST, 460 M4UnitS, 461 M4UnitFST, 462 M4UnitS, 463 M4UnitFST, 464 M4UnitS, 465 M4UnitFST]> { let Latency = 8; 466 let NumMicroOps = 5; 467 let ResourceCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; } 468def M4WriteVSTJ : SchedWriteRes<[M4UnitA, 469 M4UnitS, 470 M4UnitFST, 471 M4UnitS, 472 M4UnitFST]> { let Latency = 1; 473 let NumMicroOps = 2; } 474def M4WriteVSTK : SchedWriteRes<[M4UnitA, 475 M4UnitS, 476 M4UnitFST]> { let Latency = 3; 477 let NumMicroOps = 2; } 478def M4WriteVSTL : SchedWriteRes<[M4UnitNSHF, 479 M4UnitNSHF, 480 M4UnitS, 481 M4UnitFST, 482 M4UnitS, 483 M4UnitFST]> { let Latency = 4; 484 let NumMicroOps = 4; 485 let ResourceCycles = [1, 1, 2, 1, 2, 1]; } 486def M4WriteVSTY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteVSTK]>, 487 SchedVar<NoSchedPred, [WriteVST]>]>; 488 489// Special cases. 490def M4WriteCOPY : SchedWriteVariant<[SchedVar<ExynosFPPred, [M4WriteNALU1]>, 491 SchedVar<NoSchedPred, [M4WriteZ0]>]>; 492def M4WriteMOVI : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M4WriteZ0]>, 493 SchedVar<NoSchedPred, [M4WriteNALU1]>]>; 494 495// Fast forwarding. 496def M4ReadAESM1 : SchedReadAdvance<+1, [M4WriteNCRY1]>; 497def M4ReadFMACM1 : SchedReadAdvance<+1, [M4WriteFMAC4, 498 M4WriteFMAC4H, 499 M4WriteFMAC5]>; 500def M4ReadNMULM1 : SchedReadAdvance<+1, [M4WriteNMUL3]>; 501def M4ReadNMULP2 : SchedReadAdvance<-2, [M4WriteNMUL3]>; 502 503 504//===----------------------------------------------------------------------===// 505// Coarse scheduling model. 506 507// Branch instructions. 508def : SchedAlias<WriteBr, M4WriteZ0>; 509def : SchedAlias<WriteBrReg, M4WriteC1>; 510 511// Arithmetic and logical integer instructions. 512def : SchedAlias<WriteI, M4WriteA1>; 513def : SchedAlias<WriteIEReg, M4WriteAA>; // FIXME: M4WriteAX crashes TableGen. 514def : SchedAlias<WriteISReg, M4WriteAA>; // FIXME: M4WriteAX crashes TableGen. 515def : SchedAlias<WriteIS, M4WriteA1>; 516 517// Move instructions. 518def : SchedAlias<WriteImm, M4WriteA1>; 519 520// Divide and multiply instructions. 521def : SchedAlias<WriteID32, M4WriteD12>; 522def : SchedAlias<WriteID64, M4WriteD21>; 523def : SchedAlias<WriteIM32, M4WriteC3>; 524def : SchedAlias<WriteIM64, M4WriteCA>; 525 526// Miscellaneous instructions. 527def : SchedAlias<WriteExtr, M4WriteAY>; 528 529// Addressing modes. 530def : SchedAlias<WriteAdr, M4WriteZ1>; 531def : SchedAlias<ReadAdrBase, M4ReadAdrBase>; 532 533// Load instructions. 534def : SchedAlias<WriteLD, M4WriteL4>; 535def : SchedAlias<WriteLDHi, M4WriteZ4>; 536def : SchedAlias<WriteLDIdx, M4WriteLX>; 537 538// Store instructions. 539def : SchedAlias<WriteST, M4WriteS1>; 540def : SchedAlias<WriteSTP, M4WriteS1>; 541def : SchedAlias<WriteSTX, M4WriteS1>; 542def : SchedAlias<WriteSTIdx, M4WriteSX>; 543 544// FP data instructions. 545def : SchedAlias<WriteF, M4WriteFADD2>; 546def : SchedAlias<WriteFCmp, M4WriteNMSC2>; 547def : SchedAlias<WriteFDiv, M4WriteFDIV12>; 548def : SchedAlias<WriteFMul, M4WriteFMAC3>; 549 550// FP miscellaneous instructions. 551def : SchedAlias<WriteFCvt, M4WriteFCVT2>; 552def : SchedAlias<WriteFImm, M4WriteNALU1>; 553def : SchedAlias<WriteFCopy, M4WriteNALU1>; 554 555// FP load instructions. 556def : SchedAlias<WriteVLD, M4WriteL5>; 557 558// FP store instructions. 559def : SchedAlias<WriteVST, M4WriteVST1>; 560 561// ASIMD FP instructions. 562def : SchedAlias<WriteVd, M4WriteNALU1>; 563def : SchedAlias<WriteVq, M4WriteNALU1>; 564 565// Other miscellaneous instructions. 566def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 567def : WriteRes<WriteBarrier, []> { let Latency = 1; } 568def : WriteRes<WriteHint, []> { let Latency = 1; } 569def : WriteRes<WriteSys, []> { let Latency = 1; } 570 571//===----------------------------------------------------------------------===// 572// Generic fast forwarding. 573 574// TODO: Add FP register forwarding rules. 575 576def : ReadAdvance<ReadI, 0>; 577def : ReadAdvance<ReadISReg, 0>; 578def : ReadAdvance<ReadIEReg, 0>; 579def : ReadAdvance<ReadIM, 0>; 580// TODO: The forwarding for 32 bits actually saves 2 cycles. 581def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>; 582def : ReadAdvance<ReadID, 0>; 583def : ReadAdvance<ReadExtrHi, 0>; 584def : ReadAdvance<ReadAdrBase, 0>; 585def : ReadAdvance<ReadVLD, 0>; 586def : ReadAdvance<ReadST, 0>; 587 588//===----------------------------------------------------------------------===// 589// Finer scheduling model. 590 591// Branch instructions 592def : InstRW<[M4WriteB1], (instrs Bcc)>; 593def : InstRW<[M4WriteAF], (instrs BL)>; 594def : InstRW<[M4WriteBX], (instrs BLR)>; 595def : InstRW<[M4WriteC1], (instregex "^CBN?Z[WX]")>; 596def : InstRW<[M4WriteAD], (instregex "^TBN?Z[WX]")>; 597 598// Arithmetic and logical integer instructions. 599def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>; 600def : InstRW<[M4WriteAU], (instrs ORRWrs, ORRXrs)>; 601def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>; 602def : InstRW<[M4WriteAX], (instregex "^(ADD|SUB)S?[WX]rx(64)?$")>; 603def : InstRW<[M4WriteAV], (instrs ADDWri, ADDXri, ORRWri, ORRXri)>; 604 605// Move instructions. 606def : InstRW<[M4WriteCOPY], (instrs COPY)>; 607def : InstRW<[M4WriteZ0], (instrs ADR, ADRP)>; 608def : InstRW<[M4WriteZ0], (instregex "^MOV[NZ][WX]i")>; 609 610// Divide and multiply instructions. 611 612// Miscellaneous instructions. 613 614// Load instructions. 615def : InstRW<[M4WriteLD, 616 WriteLDHi, 617 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>; 618def : InstRW<[M4WriteL5, 619 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>; 620def : InstRW<[WriteLDIdx, 621 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>; 622def : InstRW<[M4WriteL5, 623 ReadAdrBase], (instrs PRFMroW)>; 624def : InstRW<[WriteLDIdx, 625 ReadAdrBase], (instrs PRFMroX)>; 626 627// Store instructions. 628def : InstRW<[M4WriteSB, 629 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>; 630def : InstRW<[WriteST, 631 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>; 632 633// FP data instructions. 634def : InstRW<[M4WriteNSHF1H], (instrs FABSHr)>; 635def : InstRW<[M4WriteNSHF1], (instregex "^FABS[SD]r")>; 636def : InstRW<[M4WriteFADD2H], (instregex "^F(ADD|SUB)Hrr")>; 637def : InstRW<[M4WriteFADD2], (instregex "^F(ADD|SUB)[SD]rr")>; 638def : InstRW<[M4WriteFADD2H], (instregex "^FADDPv.i16")>; 639def : InstRW<[M4WriteFADD2], (instregex "^FADDPv.i(32|64)")>; 640def : InstRW<[M4WriteNEONQ], (instregex "^FCCMPE?[HSD]rr")>; 641def : InstRW<[M4WriteNMSC2], (instregex "^FCMPE?[HSD]r[ir]")>; 642def : InstRW<[M4WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)(16|32|64|v1)")>; 643def : InstRW<[M4WriteFDIV7H], (instrs FDIVHrr)>; 644def : InstRW<[M4WriteFDIV7], (instrs FDIVSrr)>; 645def : InstRW<[M4WriteFDIV12], (instrs FDIVDrr)>; 646def : InstRW<[M4WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?[HSD]rr")>; 647def : InstRW<[M4WriteFMAC3H], (instregex "^FN?MULHrr")>; 648def : InstRW<[M4WriteFMAC3], (instregex "^FN?MUL[SD]rr")>; 649def : InstRW<[M4WriteFMAC3H], (instrs FMULX16)>; 650def : InstRW<[M4WriteFMAC3], (instregex "^FMULX(32|64)")>; 651def : InstRW<[M4WriteFMAC4H, 652 M4ReadFMACM1], (instregex "^FN?M(ADD|SUB)Hrrr")>; 653def : InstRW<[M4WriteFMAC4, 654 M4ReadFMACM1], (instregex "^FN?M(ADD|SUB)[SD]rrr")>; 655def : InstRW<[M4WriteNALU1H], (instrs FNEGHr)>; 656def : InstRW<[M4WriteNALU1], (instregex "^FNEG[SD]r")>; 657def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT.+r")>; 658def : InstRW<[M4WriteNEONH], (instregex "^FCSEL[HSD]rrr")>; 659def : InstRW<[M4WriteFSQR7H], (instrs FSQRTHr)>; 660def : InstRW<[M4WriteFSQR8], (instrs FSQRTSr)>; 661def : InstRW<[M4WriteFSQR12], (instrs FSQRTDr)>; 662 663// FP miscellaneous instructions. 664def : InstRW<[M4WriteFCVT2H], (instregex "^FCVTH[SD]r")>; 665def : InstRW<[M4WriteFCVT2H], (instregex "^FCVT[SD]Hr")>; 666def : InstRW<[M4WriteFCVT2], (instregex "^FCVT[SD][SD]r")>; 667def : InstRW<[M4WriteFCVT6A], (instregex "^[SU]CVTF[SU][XW][HSD]ri")>; 668def : InstRW<[M4WriteNEONR], (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>; 669def : InstRW<[M4WriteNALU1], (instregex "^FMOV[HSD][ir]")>; 670def : InstRW<[M4WriteSA], (instregex "^FMOV[WX][HSD]r")>; 671def : InstRW<[M4WriteNEONJ], (instregex "^FMOV[HSD][WX]r")>; 672def : InstRW<[M4WriteNEONI], (instregex "^FMOVXDHighr")>; 673def : InstRW<[M4WriteNEONK], (instregex "^FMOVDXHighr")>; 674def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev1f16")>; 675def : InstRW<[M4WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev1i(32|64)")>; 676def : InstRW<[M4WriteNMSC1], (instregex "^FRECPXv1")>; 677def : InstRW<[M4WriteFMAC4H], (instregex "^F(RECP|RSQRT)S16")>; 678def : InstRW<[M4WriteFMAC4], (instregex "^F(RECP|RSQRT)S(32|64)")>; 679 680// FP load instructions. 681def : InstRW<[WriteVLD], (instregex "^LDR[SDQ]l")>; 682def : InstRW<[WriteVLD], (instregex "^LDUR[BHSDQ]i")>; 683def : InstRW<[WriteVLD, 684 WriteAdr], (instregex "^LDR[BHSDQ](post|pre)")>; 685def : InstRW<[WriteVLD], (instregex "^LDR[BHSDQ]ui")>; 686def : InstRW<[M4WriteLE, 687 ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>; 688def : InstRW<[WriteVLD, 689 ReadAdrBase], (instregex "^LDR[BHSD]roX")>; 690def : InstRW<[M4WriteLY, 691 ReadAdrBase], (instrs LDRQroX)>; 692def : InstRW<[WriteVLD, 693 M4WriteLH], (instregex "^LDN?P[SD]i")>; 694def : InstRW<[M4WriteLA, 695 M4WriteLH], (instregex "^LDN?PQi")>; 696def : InstRW<[M4WriteL5, 697 M4WriteLH, 698 WriteAdr], (instregex "^LDP[SD]post")>; 699def : InstRW<[M4WriteLB, 700 M4WriteLH, 701 WriteAdr], (instrs LDPQpost)>; 702def : InstRW<[M4WriteLB, 703 M4WriteLH, 704 WriteAdr], (instregex "^LDP[SD]pre")>; 705def : InstRW<[M4WriteLC, 706 M4WriteLH, 707 WriteAdr], (instrs LDPQpre)>; 708 709// FP store instructions. 710def : InstRW<[WriteVST], (instregex "^STUR[BHSDQ]i")>; 711def : InstRW<[WriteVST, 712 WriteAdr], (instregex "^STR[BHSDQ](post|pre)")>; 713def : InstRW<[WriteVST], (instregex "^STR[BHSDQ]ui")>; 714def : InstRW<[M4WriteVSTK, 715 ReadAdrBase], (instregex "^STR[BHSD]roW")>; 716def : InstRW<[M4WriteVSTK, 717 ReadAdrBase], (instrs STRQroW)>; 718def : InstRW<[WriteVST, 719 ReadAdrBase], (instregex "^STR[BHSD]roX")>; 720def : InstRW<[M4WriteVSTY, 721 ReadAdrBase], (instrs STRQroX)>; 722def : InstRW<[WriteVST], (instregex "^STN?P[SD]i")>; 723def : InstRW<[M4WriteVSTJ], (instregex "^STN?PQi")>; 724def : InstRW<[WriteVST, 725 WriteAdr], (instregex "^STP[SD](post|pre)")>; 726def : InstRW<[M4WriteVSTJ, 727 WriteAdr], (instregex "^STPQ(post|pre)")>; 728 729// ASIMD instructions. 730def : InstRW<[M4WriteNHAD1], (instregex "^[SU]ABDL?v")>; 731def : InstRW<[M4WriteNHAD3], (instregex "^[SU]ABAL?v")>; 732def : InstRW<[M4WriteNMSC1], (instregex "^ABSv")>; 733def : InstRW<[M4WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>; 734def : InstRW<[M4WriteNHAD3], (instregex "^[SU]?ADDL?Pv")>; 735def : InstRW<[M4WriteNHAD3], (instregex "^[SU]H(ADD|SUB)v")>; 736def : InstRW<[M4WriteNHAD3], (instregex "^[SU](ADD|SUB)[LW]v")>; 737def : InstRW<[M4WriteNHAD3], (instregex "^R?(ADD|SUB)HN2?v")>; 738def : InstRW<[M4WriteNHAD3], (instregex "^[SU]Q(ADD|SUB)v")>; 739def : InstRW<[M4WriteNHAD3], (instregex "^(SU|US)QADDv")>; 740def : InstRW<[M4WriteNHAD3], (instregex "^[SU]RHADDv")>; 741def : InstRW<[M4WriteNMSC1], (instregex "^SQ(ABS|NEG)v")>; 742def : InstRW<[M4WriteNHAD3], (instregex "^[SU]?ADDL?Vv")>; 743def : InstRW<[M4WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>; 744def : InstRW<[M4WriteNALU1], (instregex "^CMTSTv")>; 745def : InstRW<[M4WriteNALU1], (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>; 746def : InstRW<[M4WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>; 747def : InstRW<[M4WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>; 748def : InstRW<[M4WriteNHAD3], (instregex "^[SU](MIN|MAX)Vv")>; 749def : InstRW<[M4WriteNMUL3, 750 M4ReadNMULM1], (instregex "^ML[AS]v")>; 751def : InstRW<[M4WriteNMUL3, 752 M4ReadNMULM1], (instregex "^(SQR?D)?MULH?v")>; 753def : InstRW<[M4WriteNMUL3, 754 M4ReadNMULM1], (instregex "^SQRDML[AS]H")>; 755def : InstRW<[M4WriteNMUL3, 756 M4ReadNMULM1], (instregex "^(S|U|SQD)ML[AS]L(v1(i32|i64)|v2i32|v4i16|v8i8)")>; 757def : InstRW<[M4WriteNMUL3, 758 M4ReadNMULP2], (instregex "^(S|U|SQD)ML[AS]L(v4i32|v8i16|v16i8)")>; 759def : InstRW<[M4WriteNMUL3, 760 M4ReadNMULM1], (instregex "^(S|U|SQD)MULL(v1(i32|i64)|v2i32|v4i16|v8i8)")>; 761def : InstRW<[M4WriteNMUL3, 762 M4ReadNMULP2], (instregex "^(S|U|SQD)MULL(v4i32|v8i16|v16i8)")>; 763def : InstRW<[M4WriteNMUL3], (instregex "^[SU]DOT(lane)?v")>; 764def : InstRW<[M4WriteNHAD3], (instregex "^[SU]ADALPv")>; 765def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]R?SRA[dv]")>; 766def : InstRW<[M4WriteNSHT1], (instregex "^SHL[dv]")>; 767def : InstRW<[M4WriteNSHT1], (instregex "^S[LR]I[dv]")>; 768def : InstRW<[M4WriteNSHT1], (instregex "^[SU]SH[LR][dv]")>; 769def : InstRW<[M4WriteNSHT2], (instregex "^[SU]?SHLLv")>; 770def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?Q?R?SHRU?N[bhsv]")>; 771def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]RSH[LR][dv]")>; 772def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]QR?SHLU?[bhsdv]")>; 773 774// ASIMD FP instructions. 775def : InstRW<[M4WriteNSHF1H], (instregex "^FABSv.f16")>; 776def : InstRW<[M4WriteNSHF1], (instregex "^FABSv.f(32|64)")>; 777def : InstRW<[M4WriteFADD2H], (instregex "^F(ABD|ADD|SUB)v.f16")>; 778def : InstRW<[M4WriteFADD2], (instregex "^F(ABD|ADD|SUB)v.f(32|64)")>; 779def : InstRW<[M4WriteFADD2H], (instregex "^FADDPv.f16")>; 780def : InstRW<[M4WriteFADD2], (instregex "^FADDPv.f(32|64)")>; 781def : InstRW<[M4WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>; 782def : InstRW<[M4WriteFCVT2], (instregex "^FCVT(L|N|XN)v")>; 783def : InstRW<[M4WriteFCVT2A], (instregex "^FCVT[AMNPZ][SU]v")>; 784def : InstRW<[M4WriteFCVT2H], (instregex "^[SU]CVTFv.[fi]16")>; 785def : InstRW<[M4WriteFCVT2], (instregex "^[SU]CVTFv.[fi](32|64)")>; 786def : InstRW<[M4WriteFDIV7H], (instrs FDIVv4f16)>; 787def : InstRW<[M4WriteNEONVH], (instrs FDIVv8f16)>; 788def : InstRW<[M4WriteFDIV7], (instrs FDIVv2f32)>; 789def : InstRW<[M4WriteNEONV], (instrs FDIVv4f32)>; 790def : InstRW<[M4WriteNEONW], (instrs FDIVv2f64)>; 791def : InstRW<[M4WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?v")>; 792def : InstRW<[M4WriteNMSC2], (instregex "^F(MAX|MIN)(NM)?Pv")>; 793def : InstRW<[M4WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>; 794def : InstRW<[M4WriteFMAC2H], (instregex "^FMULX?v.[fi]16")>; 795def : InstRW<[M4WriteFMAC3], (instregex "^FMULX?v.[fi](32|64)")>; 796def : InstRW<[M4WriteFMAC4H, 797 M4ReadFMACM1], (instregex "^FML[AS]v.[fi]16")>; 798def : InstRW<[M4WriteFMAC4, 799 M4ReadFMACM1], (instregex "^FML[AS]v.[fi](32|64)")>; 800def : InstRW<[M4WriteNALU1H], (instregex "^FNEGv.f16")>; 801def : InstRW<[M4WriteNALU1], (instregex "^FNEGv.f(32|64)")>; 802def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>; 803def : InstRW<[M4WriteFSQR7H], (instrs FSQRTv4f16)>; 804def : InstRW<[M4WriteNEONXH], (instrs FSQRTv8f16)>; 805def : InstRW<[M4WriteFSQR8], (instrs FSQRTv2f32)>; 806def : InstRW<[M4WriteNEONX], (instrs FSQRTv4f32)>; 807def : InstRW<[M4WriteNEONY], (instrs FSQRTv2f64)>; 808 809// ASIMD miscellaneous instructions. 810def : InstRW<[M4WriteNALU1], (instregex "^RBITv")>; 811def : InstRW<[M4WriteNALU1], (instregex "^(BIF|BIT|BSL|BSP)v")>; 812def : InstRW<[M4WriteNALU1], (instregex "^CL[STZ]v")>; 813def : InstRW<[M4WriteNEONB], (instregex "^DUPv.+gpr")>; 814def : InstRW<[M4WriteNSHF1], (instregex "^DUP(i8|i16|i32|i64)$")>; 815def : InstRW<[M4WriteNSHF1], (instregex "^DUPv.+lane")>; 816def : InstRW<[M4WriteNSHF1], (instregex "^EXTv")>; 817def : InstRW<[M4WriteNSHT4A], (instregex "^XTNv")>; 818def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?QXTU?Nv")>; 819def : InstRW<[M4WriteNEONB], (instregex "^INSv.+gpr")>; 820def : InstRW<[M4WriteNSHF1], (instregex "^INSv.+lane")>; 821def : InstRW<[M4WriteMOVI], (instregex "^(MOV|MVN)I")>; 822def : InstRW<[M4WriteNALU1H], (instregex "^FMOVv.f16")>; 823def : InstRW<[M4WriteNALU1], (instregex "^FMOVv.f(32|64)")>; 824def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev[248]f16")>; 825def : InstRW<[M4WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev[248]f(32|64)")>; 826def : InstRW<[M4WriteFCVT3], (instregex "^U(RECP|RSQRT)Ev[24]i32")>; 827def : InstRW<[M4WriteFMAC4H], (instregex "^F(RECP|RSQRT)Sv.f16")>; 828def : InstRW<[M4WriteFMAC4], (instregex "^F(RECP|RSQRT)Sv.f(32|64)")>; 829def : InstRW<[M4WriteNSHF1], (instregex "^REV(16|32|64)v")>; 830def : InstRW<[M4WriteNSHFA], (instregex "^TB[LX]v(8|16)i8One")>; 831def : InstRW<[M4WriteNSHFB], (instregex "^TB[LX]v(8|16)i8Two")>; 832def : InstRW<[M4WriteNSHFC], (instregex "^TB[LX]v(8|16)i8Three")>; 833def : InstRW<[M4WriteNSHFD], (instregex "^TB[LX]v(8|16)i8Four")>; 834def : InstRW<[M4WriteNEONP], (instregex "^[SU]MOVv")>; 835def : InstRW<[M4WriteNSHF1], (instregex "^(TRN|UZP|ZIP)[12]v")>; 836 837// ASIMD load instructions. 838def : InstRW<[WriteVLD], (instregex "LD1Onev(8b|4h|2s|1d)$")>; 839def : InstRW<[WriteVLD, 840 M4WriteA1], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>; 841def : InstRW<[WriteVLD], (instregex "LD1Onev(16b|8h|4s|2d)$")>; 842def : InstRW<[WriteVLD, 843 M4WriteA1], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>; 844 845def : InstRW<[M4WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>; 846def : InstRW<[M4WriteVLDA, 847 M4WriteA1], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>; 848def : InstRW<[M4WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>; 849def : InstRW<[M4WriteVLDA, 850 M4WriteA1], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>; 851 852def : InstRW<[M4WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>; 853def : InstRW<[M4WriteVLDB, 854 M4WriteA1], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>; 855def : InstRW<[M4WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>; 856def : InstRW<[M4WriteVLDB, 857 M4WriteA1], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>; 858 859def : InstRW<[M4WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>; 860def : InstRW<[M4WriteVLDC, 861 M4WriteA1], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>; 862def : InstRW<[M4WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>; 863def : InstRW<[M4WriteVLDC, 864 M4WriteA1], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>; 865 866def : InstRW<[M4WriteVLDD], (instregex "LD1i(8|16|32|64)$")>; 867def : InstRW<[M4WriteVLDD, 868 M4WriteA1], (instregex "LD1i(8|16|32|64)_POST$")>; 869 870def : InstRW<[WriteVLD], (instregex "LD1Rv(8b|4h|2s|1d)$")>; 871def : InstRW<[WriteVLD, 872 M4WriteA1], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>; 873def : InstRW<[WriteVLD], (instregex "LD1Rv(16b|8h|4s|2d)$")>; 874def : InstRW<[WriteVLD, 875 M4WriteA1], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>; 876 877def : InstRW<[M4WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>; 878def : InstRW<[M4WriteVLDF, 879 M4WriteA1], (instregex "LD2Twov(8b|4h|2s)_POST$")>; 880def : InstRW<[M4WriteVLDF], (instregex "LD2Twov(16b|8h|4s|2d)$")>; 881def : InstRW<[M4WriteVLDF, 882 M4WriteA1], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>; 883 884def : InstRW<[M4WriteVLDG], (instregex "LD2i(8|16|32|64)$")>; 885def : InstRW<[M4WriteVLDG, 886 M4WriteA1], (instregex "LD2i(8|16|32|64)_POST$")>; 887 888def : InstRW<[M4WriteVLDA], (instregex "LD2Rv(8b|4h|2s|1d)$")>; 889def : InstRW<[M4WriteVLDA, 890 M4WriteA1], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>; 891def : InstRW<[M4WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>; 892def : InstRW<[M4WriteVLDA, 893 M4WriteA1], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>; 894 895def : InstRW<[M4WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>; 896def : InstRW<[M4WriteVLDI, 897 M4WriteA1], (instregex "LD3Threev(8b|4h|2s)_POST$")>; 898def : InstRW<[M4WriteVLDI], (instregex "LD3Threev(16b|8h|4s|2d)$")>; 899def : InstRW<[M4WriteVLDI, 900 M4WriteA1], (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>; 901 902def : InstRW<[M4WriteVLDJ], (instregex "LD3i(8|16|32)$")>; 903def : InstRW<[M4WriteVLDJ, 904 M4WriteA1], (instregex "LD3i(8|16|32)_POST$")>; 905def : InstRW<[M4WriteVLDL], (instregex "LD3i64$")>; 906def : InstRW<[M4WriteVLDL, 907 M4WriteA1], (instregex "LD3i64_POST$")>; 908 909def : InstRW<[M4WriteVLDB], (instregex "LD3Rv(8b|4h|2s|1d)$")>; 910def : InstRW<[M4WriteVLDB, 911 M4WriteA1], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>; 912def : InstRW<[M4WriteVLDB], (instregex "LD3Rv(16b|8h|4s|2d)$")>; 913def : InstRW<[M4WriteVLDB, 914 M4WriteA1], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>; 915 916def : InstRW<[M4WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>; 917def : InstRW<[M4WriteVLDN, 918 M4WriteA1], (instregex "LD4Fourv(8b|4h|2s)_POST$")>; 919def : InstRW<[M4WriteVLDN], (instregex "LD4Fourv(16b|8h|4s|2d)$")>; 920def : InstRW<[M4WriteVLDN, 921 M4WriteA1], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>; 922 923def : InstRW<[M4WriteVLDK], (instregex "LD4i(8|16|32)$")>; 924def : InstRW<[M4WriteVLDK, 925 M4WriteA1], (instregex "LD4i(8|16|32)_POST$")>; 926def : InstRW<[M4WriteVLDM], (instregex "LD4i64$")>; 927def : InstRW<[M4WriteVLDM, 928 M4WriteA1], (instregex "LD4i64_POST$")>; 929 930def : InstRW<[M4WriteVLDC], (instregex "LD4Rv(8b|4h|2s|1d)$")>; 931def : InstRW<[M4WriteVLDC, 932 M4WriteA1], (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>; 933def : InstRW<[M4WriteVLDC], (instregex "LD4Rv(16b|8h|4s|2d)$")>; 934def : InstRW<[M4WriteVLDC, 935 M4WriteA1], (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>; 936 937// ASIMD store instructions. 938def : InstRW<[WriteVST], (instregex "ST1Onev(8b|4h|2s|1d)$")>; 939def : InstRW<[WriteVST, 940 M4WriteA1], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>; 941def : InstRW<[WriteVST], (instregex "ST1Onev(16b|8h|4s|2d)$")>; 942def : InstRW<[WriteVST, 943 M4WriteA1], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>; 944 945def : InstRW<[M4WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>; 946def : InstRW<[M4WriteVSTA, 947 M4WriteA1], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>; 948def : InstRW<[M4WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>; 949def : InstRW<[M4WriteVSTA, 950 M4WriteA1], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>; 951 952def : InstRW<[M4WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>; 953def : InstRW<[M4WriteVSTB, 954 M4WriteA1], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>; 955def : InstRW<[M4WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>; 956def : InstRW<[M4WriteVSTB, 957 M4WriteA1], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>; 958 959def : InstRW<[M4WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; 960def : InstRW<[M4WriteVSTC, 961 M4WriteA1], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>; 962def : InstRW<[M4WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; 963def : InstRW<[M4WriteVSTC, 964 M4WriteA1], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>; 965 966def : InstRW<[WriteVST], (instregex "ST1i(8|16|32|64)$")>; 967def : InstRW<[WriteVST, 968 M4WriteA1], (instregex "ST1i(8|16|32|64)_POST$")>; 969 970def : InstRW<[M4WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>; 971def : InstRW<[M4WriteVSTD, 972 M4WriteA1], (instregex "ST2Twov(8b|4h|2s)_POST$")>; 973def : InstRW<[M4WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>; 974def : InstRW<[M4WriteVSTE, 975 M4WriteA1], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>; 976 977def : InstRW<[M4WriteVSTD], (instregex "ST2i(8|16|32|64)$")>; 978def : InstRW<[M4WriteVSTD, 979 M4WriteA1], (instregex "ST2i(8|16|32|64)_POST$")>; 980 981def : InstRW<[M4WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>; 982def : InstRW<[M4WriteVSTF, 983 M4WriteA1], (instregex "ST3Threev(8b|4h|2s)_POST$")>; 984def : InstRW<[M4WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>; 985def : InstRW<[M4WriteVSTG, 986 M4WriteA1], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>; 987 988def : InstRW<[M4WriteVSTE], (instregex "ST3i(8|16|32|64)$")>; 989def : InstRW<[M4WriteVSTE, 990 M4WriteA1], (instregex "ST3i(8|16|32|64)_POST$")>; 991 992def : InstRW<[M4WriteVSTL], (instregex "ST4Fourv(8b|4h|2s)$")>; 993def : InstRW<[M4WriteVSTL, 994 M4WriteA1], (instregex "ST4Fourv(8b|4h|2s)_POST$")>; 995def : InstRW<[M4WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>; 996def : InstRW<[M4WriteVSTI, 997 M4WriteA1], (instregex "ST4Fourv(16b|8h|4s|2d)_POST$")>; 998 999def : InstRW<[M4WriteVSTE], (instregex "ST4i(8|16|32|64)$")>; 1000def : InstRW<[M4WriteVSTE, 1001 M4WriteA1], (instregex "ST4i(8|16|32|64)_POST$")>; 1002 1003// Cryptography instructions. 1004def : InstRW<[M4WriteNCRY1], (instregex "^AES[DE]")>; 1005def : InstRW<[M4WriteNCRY1, 1006 M4ReadAESM1], (instregex "^AESI?MC")>; 1007def : InstRW<[M4WriteNCRY1A], (instregex "^PMULv")>; 1008def : InstRW<[M4WriteNCRY1A], (instregex "^PMULLv(1|8)i")>; 1009def : InstRW<[M4WriteNCRY3A], (instregex "^PMULLv(2|16)i")>; 1010def : InstRW<[M4WriteNCRY1A], (instregex "^SHA1([CHMP]|SU[01])")>; 1011def : InstRW<[M4WriteNCRY1A], (instrs SHA256SU0rr)>; 1012def : InstRW<[M4WriteNCRY5A], (instrs SHA256SU1rrr)>; 1013def : InstRW<[M4WriteNCRY5A], (instrs SHA256H2rrr)>; 1014 1015// CRC instructions. 1016def : InstRW<[M4WriteE2], (instregex "^CRC32C?[BHWX]rr$")>; 1017 1018} // SchedModel = ExynosM4Model 1019