1//=- AArch64SchedExynosM4.td - Samsung Exynos M4 Sched Defs --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for the Samsung Exynos M4 to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// The Exynos-M4 is an advanced superscalar microprocessor with a 6-wide 16// in-order stage for decode and dispatch and a wider issue stage. 17// The execution units and loads and stores are out-of-order. 18 19def ExynosM4Model : SchedMachineModel { 20 let IssueWidth = 6; // Up to 6 uops per cycle. 21 let MicroOpBufferSize = 228; // ROB size. 22 let LoopMicroOpBufferSize = 48; // Based on the instruction queue size. 23 let LoadLatency = 4; // Optimistic load cases. 24 let MispredictPenalty = 16; // Minimum branch misprediction penalty. 25 let CompleteModel = 1; // Use the default model otherwise. 26 27 list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F, 28 PAUnsupported.F, 29 SMEUnsupported.F, 30 [HasMTE, HasCSSC]); 31} 32 33//===----------------------------------------------------------------------===// 34// Define each kind of processor resource and number available on the Exynos-M4. 35 36let SchedModel = ExynosM4Model in { 37 38def M4UnitA : ProcResource<2>; // Simple integer 39def M4UnitC : ProcResource<2>; // Simple and complex integer 40let Super = M4UnitC, BufferSize = 1 in 41def M4UnitD : ProcResource<1>; // Integer division (inside C0, serialized) 42let Super = M4UnitC in 43def M4UnitE : ProcResource<1>; // CRC (inside C0) 44def M4UnitB : ProcResource<2>; // Branch 45def M4UnitL0 : ProcResource<1>; // Load 46def M4UnitS0 : ProcResource<1>; // Store 47def M4PipeLS : ProcResource<1>; // Load/Store 48let Super = M4PipeLS in { 49 def M4UnitL1 : ProcResource<1>; 50 def M4UnitS1 : ProcResource<1>; 51} 52def M4PipeF0 : ProcResource<1>; // FP #0 53let Super = M4PipeF0 in { 54 def M4UnitFMAC0 : ProcResource<1>; // FP multiplication 55 def M4UnitFADD0 : ProcResource<1>; // Simple FP 56 def M4UnitFCVT0 : ProcResource<1>; // FP conversion 57 def M4UnitNALU0 : ProcResource<1>; // Simple vector 58 def M4UnitNHAD : ProcResource<1>; // Horizontal vector 59 def M4UnitNMSC : ProcResource<1>; // FP and vector miscellanea 60 def M4UnitNMUL0 : ProcResource<1>; // Vector multiplication 61 def M4UnitNSHT0 : ProcResource<1>; // Vector shifting 62 def M4UnitNSHF0 : ProcResource<1>; // Vector shuffling 63 def M4UnitNCRY0 : ProcResource<1>; // Cryptographic 64} 65def M4PipeF1 : ProcResource<1>; // FP #1 66let Super = M4PipeF1 in { 67 def M4UnitFMAC1 : ProcResource<1>; // FP multiplication 68 def M4UnitFADD1 : ProcResource<1>; // Simple FP 69 def M4UnitFDIV0 : ProcResource<2>; // FP division (serialized) 70 def M4UnitFSQR0 : ProcResource<2>; // FP square root (serialized) 71 def M4UnitFST0 : ProcResource<1>; // FP store 72 def M4UnitNALU1 : ProcResource<1>; // Simple vector 73 def M4UnitNSHT1 : ProcResource<1>; // Vector shifting 74 def M4UnitNSHF1 : ProcResource<1>; // Vector shuffling 75} 76def M4PipeF2 : ProcResource<1>; // FP #2 77let Super = M4PipeF2 in { 78 def M4UnitFMAC2 : ProcResource<1>; // FP multiplication 79 def M4UnitFADD2 : ProcResource<1>; // Simple FP 80 def M4UnitFCVT1 : ProcResource<1>; // FP conversion 81 def M4UnitFDIV1 : ProcResource<2>; // FP division (serialized) 82 def M4UnitFSQR1 : ProcResource<2>; // FP square root (serialized) 83 def M4UnitFST1 : ProcResource<1>; // FP store 84 def M4UnitNALU2 : ProcResource<1>; // Simple vector 85 def M4UnitNMUL1 : ProcResource<1>; // Vector multiplication 86 def M4UnitNSHT2 : ProcResource<1>; // Vector shifting 87 def M4UnitNCRY1 : ProcResource<1>; // Cryptographic 88} 89 90def M4UnitALU : ProcResGroup<[M4UnitA, 91 M4UnitC]>; 92def M4UnitL : ProcResGroup<[M4UnitL0, 93 M4UnitL1]>; 94def M4UnitS : ProcResGroup<[M4UnitS0, 95 M4UnitS1]>; 96def M4UnitFMAC : ProcResGroup<[M4UnitFMAC0, 97 M4UnitFMAC1, 98 M4UnitFMAC2]>; 99def M4UnitFMACH : ProcResGroup<[M4UnitFMAC0, 100 M4UnitFMAC1]>; 101def M4UnitFADD : ProcResGroup<[M4UnitFADD0, 102 M4UnitFADD1, 103 M4UnitFADD2]>; 104def M4UnitFADDH : ProcResGroup<[M4UnitFADD0, 105 M4UnitFADD1]>; 106def M4UnitFCVT : ProcResGroup<[M4UnitFCVT0, 107 M4UnitFCVT1]>; 108def M4UnitFCVTH : ProcResGroup<[M4UnitFCVT0]>; 109def M4UnitFDIV : ProcResGroup<[M4UnitFDIV0, 110 M4UnitFDIV1]>; 111def M4UnitFDIVH : ProcResGroup<[M4UnitFDIV0]>; 112def M4UnitFSQR : ProcResGroup<[M4UnitFSQR0, 113 M4UnitFSQR1]>; 114def M4UnitFSQRH : ProcResGroup<[M4UnitFSQR0]>; 115def M4UnitFST : ProcResGroup<[M4UnitFST0, 116 M4UnitFST1]>; 117def M4UnitNALU : ProcResGroup<[M4UnitNALU0, 118 M4UnitNALU1, 119 M4UnitNALU2]>; 120def M4UnitNALUH : ProcResGroup<[M4UnitNALU0, 121 M4UnitNALU1]>; 122def M4UnitNMUL : ProcResGroup<[M4UnitNMUL0, 123 M4UnitNMUL1]>; 124def M4UnitNSHT : ProcResGroup<[M4UnitNSHT0, 125 M4UnitNSHT1, 126 M4UnitNSHT2]>; 127def M4UnitNSHF : ProcResGroup<[M4UnitNSHF0, 128 M4UnitNSHF1]>; 129def M4UnitNSHFH : ProcResGroup<[M4UnitNSHF0]>; 130def M4UnitNCRY : ProcResGroup<[M4UnitNCRY0, 131 M4UnitNCRY1]>; 132 133//===----------------------------------------------------------------------===// 134// Resources details. 135 136def M4WriteZ0 : SchedWriteRes<[]> { let Latency = 0; } 137def M4WriteZ1 : SchedWriteRes<[]> { let Latency = 1; 138 let NumMicroOps = 0; } 139def M4WriteZ4 : SchedWriteRes<[]> { let Latency = 4; 140 let NumMicroOps = 0; } 141 142def M4WriteA1 : SchedWriteRes<[M4UnitALU]> { let Latency = 1; } 143def M4WriteA2 : SchedWriteRes<[M4UnitALU]> { let Latency = 2; } 144def M4WriteAA : SchedWriteRes<[M4UnitALU]> { let Latency = 2; 145 let ReleaseAtCycles = [2]; } 146def M4WriteAB : SchedWriteRes<[M4UnitALU, 147 M4UnitC]> { let Latency = 2; 148 let NumMicroOps = 2; } 149def M4WriteAC : SchedWriteRes<[M4UnitALU, 150 M4UnitALU, 151 M4UnitC]> { let Latency = 3; 152 let NumMicroOps = 3; } 153def M4WriteAD : SchedWriteRes<[M4UnitALU, 154 M4UnitC]> { let Latency = 2; 155 let NumMicroOps = 2; } 156def M4WriteAF : SchedWriteRes<[M4UnitALU]> { let Latency = 2; 157 let NumMicroOps = 2; } 158def M4WriteAU : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M4WriteZ0]>, 159 SchedVar<ExynosArithPred, [M4WriteA1]>, 160 SchedVar<ExynosLogicExPred, [M4WriteA1]>, 161 SchedVar<NoSchedPred, [M4WriteAA]>]>; 162def M4WriteAV : SchedWriteVariant<[SchedVar<ExynosResetPred, [M4WriteZ0]>, 163 SchedVar<ExynosArithPred, [M4WriteA1]>, 164 SchedVar<ExynosLogicExPred, [M4WriteA1]>, 165 SchedVar<NoSchedPred, [M4WriteAA]>]>; 166def M4WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M4WriteA1]>, 167 SchedVar<ExynosLogicExPred, [M4WriteA1]>, 168 SchedVar<NoSchedPred, [M4WriteAA]>]>; 169def M4WriteAY : SchedWriteVariant<[SchedVar<IsRORImmIdiomPred, [M4WriteA1]>, 170 SchedVar<NoSchedPred, [M4WriteAF]>]>; 171 172def M4WriteB1 : SchedWriteRes<[M4UnitB]> { let Latency = 1; } 173def M4WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M4WriteAC]>, 174 SchedVar<NoSchedPred, [M4WriteAB]>]>; 175 176def M4WriteC1 : SchedWriteRes<[M4UnitC]> { let Latency = 1; } 177def M4WriteC3 : SchedWriteRes<[M4UnitC]> { let Latency = 3; } 178def M4WriteCA : SchedWriteRes<[M4UnitC]> { let Latency = 4; 179 let ReleaseAtCycles = [2]; } 180 181def M4WriteD12 : SchedWriteRes<[M4UnitD]> { let Latency = 12; 182 let ReleaseAtCycles = [12]; } 183def M4WriteD21 : SchedWriteRes<[M4UnitD]> { let Latency = 21; 184 let ReleaseAtCycles = [21]; } 185 186def M4WriteE2 : SchedWriteRes<[M4UnitE]> { let Latency = 2; } 187 188def M4WriteL4 : SchedWriteRes<[M4UnitL]> { let Latency = 4; } 189def M4WriteL5 : SchedWriteRes<[M4UnitL]> { let Latency = 5; } 190def M4WriteLA : SchedWriteRes<[M4UnitL, 191 M4UnitL]> { let Latency = 5; 192 let NumMicroOps = 1; } 193def M4WriteLB : SchedWriteRes<[M4UnitA, 194 M4UnitL]> { let Latency = 5; 195 let NumMicroOps = 2; } 196def M4WriteLC : SchedWriteRes<[M4UnitA, 197 M4UnitL, 198 M4UnitL]> { let Latency = 5; 199 let NumMicroOps = 2; } 200def M4WriteLD : SchedWriteRes<[M4UnitA, 201 M4UnitL]> { let Latency = 4; 202 let NumMicroOps = 2; } 203def M4WriteLE : SchedWriteRes<[M4UnitA, 204 M4UnitL]> { let Latency = 6; 205 let NumMicroOps = 2; } 206def M4WriteLH : SchedWriteRes<[]> { let Latency = 5; 207 let NumMicroOps = 0; } 208def M4WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteL5]>, 209 SchedVar<NoSchedPred, [M4WriteL4]>]>; 210def M4WriteLY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteLE]>, 211 SchedVar<NoSchedPred, [M4WriteL5]>]>; 212 213def M4WriteS1 : SchedWriteRes<[M4UnitS]> { let Latency = 1; } 214def M4WriteSA : SchedWriteRes<[M4UnitS0]> { let Latency = 3; } 215def M4WriteSB : SchedWriteRes<[M4UnitA, 216 M4UnitS]> { let Latency = 2; 217 let NumMicroOps = 1; } 218def M4WriteSX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteSB]>, 219 SchedVar<NoSchedPred, [M4WriteS1]>]>; 220 221def M4ReadAdrBase : SchedReadVariant<[SchedVar< 222 MCSchedPredicate< 223 CheckAny< 224 [ScaledIdxFn, 225 ExynosScaledIdxFn]>>, [ReadDefault]>, 226 SchedVar<NoSchedPred, [ReadDefault]>]>; 227 228def M4WriteNEONA : SchedWriteRes<[M4UnitNSHF, 229 M4UnitFADD]> { let Latency = 3; 230 let NumMicroOps = 2; } 231def M4WriteNEONB : SchedWriteRes<[M4UnitNALU, 232 M4UnitS0]> { let Latency = 5; 233 let NumMicroOps = 2; } 234def M4WriteNEOND : SchedWriteRes<[M4UnitNSHF, 235 M4UnitFST]> { let Latency = 6; 236 let NumMicroOps = 2; } 237def M4WriteNEONH : SchedWriteRes<[M4UnitNALU, 238 M4UnitS0]> { let Latency = 5; 239 let NumMicroOps = 2; } 240def M4WriteNEONI : SchedWriteRes<[M4UnitNSHF, 241 M4UnitS0]> { let Latency = 2; 242 let NumMicroOps = 2; } 243def M4WriteNEONJ : SchedWriteRes<[M4UnitNMSC, 244 M4UnitS0]> { let Latency = 4; } 245def M4WriteNEONK : SchedWriteRes<[M4UnitNSHF, 246 M4UnitNMSC, 247 M4UnitS0]> { let Latency = 5; 248 let NumMicroOps = 2; } 249def M4WriteNEONL : SchedWriteRes<[M4UnitNMUL]> { let Latency = 3; } 250def M4WriteNEONN : SchedWriteRes<[M4UnitNMSC, 251 M4UnitNMSC]> { let Latency = 5; 252 let NumMicroOps = 2; } 253def M4WriteNEONO : SchedWriteRes<[M4UnitNMSC, 254 M4UnitNMSC, 255 M4UnitNMSC]> { let Latency = 8; 256 let NumMicroOps = 3; } 257def M4WriteNEONP : SchedWriteRes<[M4UnitNSHF, 258 M4UnitNMSC]> { let Latency = 4; 259 let NumMicroOps = 2; } 260def M4WriteNEONQ : SchedWriteRes<[M4UnitNMSC, 261 M4UnitC]> { let Latency = 3; 262 let NumMicroOps = 1; } 263def M4WriteNEONR : SchedWriteRes<[M4UnitFCVT0, 264 M4UnitS0]> { let Latency = 4; 265 let NumMicroOps = 1; } 266def M4WriteNEONV : SchedWriteRes<[M4UnitFDIV, 267 M4UnitFDIV]> { let Latency = 7; 268 let ReleaseAtCycles = [6, 6]; } 269def M4WriteNEONVH : SchedWriteRes<[M4UnitFDIVH, 270 M4UnitFDIVH]> { let Latency = 7; 271 let ReleaseAtCycles = [6, 6]; } 272def M4WriteNEONW : SchedWriteRes<[M4UnitFDIV, 273 M4UnitFDIV]> { let Latency = 12; 274 let ReleaseAtCycles = [9, 9]; } 275def M4WriteNEONX : SchedWriteRes<[M4UnitFSQR, 276 M4UnitFSQR]> { let Latency = 8; 277 let ReleaseAtCycles = [7, 7]; } 278def M4WriteNEONXH : SchedWriteRes<[M4UnitFSQRH, 279 M4UnitFSQRH]> { let Latency = 7; 280 let ReleaseAtCycles = [6, 6]; } 281def M4WriteNEONY : SchedWriteRes<[M4UnitFSQR, 282 M4UnitFSQR]> { let Latency = 12; 283 let ReleaseAtCycles = [9, 9]; } 284def M4WriteNEONZ : SchedWriteVariant<[SchedVar<ExynosQFormPred, [M4WriteNEONO]>, 285 SchedVar<NoSchedPred, [M4WriteNEONN]>]>; 286 287def M4WriteFADD2 : SchedWriteRes<[M4UnitFADD]> { let Latency = 2; } 288def M4WriteFADD2H : SchedWriteRes<[M4UnitFADDH]> { let Latency = 2; } 289 290def M4WriteFCVT2 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 2; } 291def M4WriteFCVT2A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 2; } 292def M4WriteFCVT2H : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 2; } 293def M4WriteFCVT3 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 3; } 294def M4WriteFCVT3A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 3; } 295def M4WriteFCVT3H : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 3; } 296def M4WriteFCVT4 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 4; } 297def M4WriteFCVT4A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 4; } 298def M4WriteFCVT6A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 6; } 299 300def M4WriteFDIV7 : SchedWriteRes<[M4UnitFDIV]> { let Latency = 7; 301 let ReleaseAtCycles = [6]; } 302def M4WriteFDIV7H : SchedWriteRes<[M4UnitFDIVH]> { let Latency = 7; 303 let ReleaseAtCycles = [6]; } 304def M4WriteFDIV12 : SchedWriteRes<[M4UnitFDIV]> { let Latency = 12; 305 let ReleaseAtCycles = [9]; } 306 307def M4WriteFMAC2H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 2; } 308def M4WriteFMAC3H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 3; } 309def M4WriteFMAC3 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 3; } 310def M4WriteFMAC4 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 4; } 311def M4WriteFMAC4H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 4; } 312 313def M4WriteFSQR7H : SchedWriteRes<[M4UnitFSQRH]> { let Latency = 7; 314 let ReleaseAtCycles = [6]; } 315def M4WriteFSQR8 : SchedWriteRes<[M4UnitFSQR]> { let Latency = 8; 316 let ReleaseAtCycles = [7]; } 317def M4WriteFSQR12 : SchedWriteRes<[M4UnitFSQR]> { let Latency = 12; 318 let ReleaseAtCycles = [9]; } 319 320def M4WriteNALU1 : SchedWriteRes<[M4UnitNALU]> { let Latency = 1; } 321def M4WriteNALU1H : SchedWriteRes<[M4UnitNALUH]> { let Latency = 1; } 322 323def M4WriteNCRY1 : SchedWriteRes<[M4UnitNCRY]> { let Latency = 1; } 324def M4WriteNCRY1A : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 1; } 325def M4WriteNCRY3A : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 3; } 326def M4WriteNCRY5A : SchedWriteRes<[M4UnitNCRY]> { let Latency = 5; } 327 328def M4WriteNHAD1 : SchedWriteRes<[M4UnitNHAD]> { let Latency = 1; } 329def M4WriteNHAD3 : SchedWriteRes<[M4UnitNHAD]> { let Latency = 3; } 330 331def M4WriteNMSC1 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 1; } 332def M4WriteNMSC2 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 2; } 333def M4WriteNMSC3 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 3; } 334 335def M4WriteNMUL3 : SchedWriteRes<[M4UnitNMUL]> { let Latency = 3; } 336 337def M4WriteNSHF1 : SchedWriteRes<[M4UnitNSHF]> { let Latency = 1; } 338def M4WriteNSHF1H : SchedWriteRes<[M4UnitNSHFH]> { let Latency = 1; } 339def M4WriteNSHF3 : SchedWriteRes<[M4UnitNSHF]> { let Latency = 3; } 340def M4WriteNSHFA : SchedWriteRes<[M4UnitNSHF]> { let Latency = 1; 341 let ReleaseAtCycles = [2]; } 342def M4WriteNSHFB : SchedWriteRes<[M4UnitNSHF]> { let Latency = 2; 343 let NumMicroOps = 2; 344 let ReleaseAtCycles = [2]; } 345def M4WriteNSHFC : SchedWriteRes<[M4UnitNSHF]> { let Latency = 3; 346 let NumMicroOps = 3; 347 let ReleaseAtCycles = [4]; } 348def M4WriteNSHFD : SchedWriteRes<[M4UnitNSHF]> { let Latency = 4; 349 let NumMicroOps = 4; 350 let ReleaseAtCycles = [4]; } 351 352def M4WriteNSHT1 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 1; } 353def M4WriteNSHT2 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 2; } 354def M4WriteNSHT3 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 3; } 355def M4WriteNSHT4A : SchedWriteRes<[M4UnitNSHT1]> { let Latency = 4; } 356 357def M4WriteVLDA : SchedWriteRes<[M4UnitL, 358 M4UnitL]> { let Latency = 5; 359 let NumMicroOps = 2; } 360def M4WriteVLDB : SchedWriteRes<[M4UnitL, 361 M4UnitL, 362 M4UnitL]> { let Latency = 6; 363 let NumMicroOps = 3; } 364def M4WriteVLDC : SchedWriteRes<[M4UnitL, 365 M4UnitL, 366 M4UnitL, 367 M4UnitL]> { let Latency = 6; 368 let NumMicroOps = 4; } 369def M4WriteVLDD : SchedWriteRes<[M4UnitL, 370 M4UnitNSHF]> { let Latency = 6; 371 let NumMicroOps = 2; 372 let ReleaseAtCycles = [2, 1]; } 373def M4WriteVLDF : SchedWriteRes<[M4UnitL, 374 M4UnitL]> { let Latency = 10; 375 let NumMicroOps = 2; 376 let ReleaseAtCycles = [3, 3]; } 377def M4WriteVLDG : SchedWriteRes<[M4UnitL, 378 M4UnitNSHF, 379 M4UnitNSHF]> { let Latency = 6; 380 let NumMicroOps = 3; 381 let ReleaseAtCycles = [2, 1, 1]; } 382def M4WriteVLDI : SchedWriteRes<[M4UnitL, 383 M4UnitL, 384 M4UnitL]> { let Latency = 12; 385 let NumMicroOps = 3; 386 let ReleaseAtCycles = [3, 3, 3]; } 387def M4WriteVLDJ : SchedWriteRes<[M4UnitL, 388 M4UnitNSHF, 389 M4UnitNSHF, 390 M4UnitNSHF]> { let Latency = 7; 391 let NumMicroOps = 4; 392 let ReleaseAtCycles = [3, 1, 1, 1]; } 393def M4WriteVLDK : SchedWriteRes<[M4UnitL, 394 M4UnitNSHF, 395 M4UnitNSHF, 396 M4UnitNSHF, 397 M4UnitNSHF]> { let Latency = 7; 398 let NumMicroOps = 5; 399 let ReleaseAtCycles = [3, 1, 1, 1, 1]; } 400def M4WriteVLDL : SchedWriteRes<[M4UnitL, 401 M4UnitNSHF, 402 M4UnitNSHF, 403 M4UnitL, 404 M4UnitNSHF]> { let Latency = 7; 405 let NumMicroOps = 5; 406 let ReleaseAtCycles = [3, 1, 1, 6, 1]; } 407def M4WriteVLDM : SchedWriteRes<[M4UnitL, 408 M4UnitNSHF, 409 M4UnitNSHF, 410 M4UnitL, 411 M4UnitNSHF, 412 M4UnitNSHF]> { let Latency = 7; 413 let NumMicroOps = 6; 414 let ReleaseAtCycles = [3, 1, 1, 3, 1, 1]; } 415def M4WriteVLDN : SchedWriteRes<[M4UnitL, 416 M4UnitL, 417 M4UnitL, 418 M4UnitL]> { let Latency = 14; 419 let NumMicroOps = 4; 420 let ReleaseAtCycles = [3, 3, 3, 3]; } 421 422def M4WriteVST1 : SchedWriteRes<[M4UnitS, 423 M4UnitFST]> { let Latency = 1; 424 let NumMicroOps = 1; } 425def M4WriteVSTA : WriteSequence<[WriteVST], 2>; 426def M4WriteVSTB : WriteSequence<[WriteVST], 3>; 427def M4WriteVSTC : WriteSequence<[WriteVST], 4>; 428def M4WriteVSTD : SchedWriteRes<[M4UnitS, 429 M4UnitFST]> { let Latency = 2; } 430def M4WriteVSTE : SchedWriteRes<[M4UnitS, 431 M4UnitFST, 432 M4UnitS, 433 M4UnitFST]> { let Latency = 2; 434 let NumMicroOps = 2; } 435def M4WriteVSTF : SchedWriteRes<[M4UnitNSHF, 436 M4UnitS, 437 M4UnitFST, 438 M4UnitS, 439 M4UnitFST]> { let Latency = 4; 440 let NumMicroOps = 4; 441 let ReleaseAtCycles = [1, 2, 1, 2, 1]; } 442def M4WriteVSTG : SchedWriteRes<[M4UnitNSHF, 443 M4UnitNSHF, 444 M4UnitNSHF, 445 M4UnitS, 446 M4UnitFST, 447 M4UnitS, 448 M4UnitFST, 449 M4UnitS, 450 M4UnitFST]> { let Latency = 5; 451 let NumMicroOps = 6; 452 let ReleaseAtCycles = [1, 1, 1, 2, 1, 2, 1, 2, 1]; } 453def M4WriteVSTI : SchedWriteRes<[M4UnitNSHF, 454 M4UnitNSHF, 455 M4UnitNSHF, 456 M4UnitNSHF, 457 M4UnitS, 458 M4UnitFST, 459 M4UnitS, 460 M4UnitFST, 461 M4UnitS, 462 M4UnitFST, 463 M4UnitS, 464 M4UnitFST]> { let Latency = 8; 465 let NumMicroOps = 5; 466 let ReleaseAtCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; } 467def M4WriteVSTJ : SchedWriteRes<[M4UnitA, 468 M4UnitS, 469 M4UnitFST, 470 M4UnitS, 471 M4UnitFST]> { let Latency = 1; 472 let NumMicroOps = 2; } 473def M4WriteVSTK : SchedWriteRes<[M4UnitA, 474 M4UnitS, 475 M4UnitFST]> { let Latency = 3; 476 let NumMicroOps = 2; } 477def M4WriteVSTL : SchedWriteRes<[M4UnitNSHF, 478 M4UnitNSHF, 479 M4UnitS, 480 M4UnitFST, 481 M4UnitS, 482 M4UnitFST]> { let Latency = 4; 483 let NumMicroOps = 4; 484 let ReleaseAtCycles = [1, 1, 2, 1, 2, 1]; } 485def M4WriteVSTY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteVSTK]>, 486 SchedVar<NoSchedPred, [WriteVST]>]>; 487 488// Special cases. 489def M4WriteCOPY : SchedWriteVariant<[SchedVar<ExynosFPPred, [M4WriteNALU1]>, 490 SchedVar<NoSchedPred, [M4WriteZ0]>]>; 491def M4WriteMOVI : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M4WriteZ0]>, 492 SchedVar<NoSchedPred, [M4WriteNALU1]>]>; 493 494// Fast forwarding. 495def M4ReadAESM1 : SchedReadAdvance<+1, [M4WriteNCRY1]>; 496def M4ReadFMACM1 : SchedReadAdvance<+1, [M4WriteFMAC4, 497 M4WriteFMAC4H]>; 498def M4ReadNMULM1 : SchedReadAdvance<+1, [M4WriteNMUL3]>; 499def M4ReadNMULP2 : SchedReadAdvance<-2, [M4WriteNMUL3]>; 500 501 502//===----------------------------------------------------------------------===// 503// Coarse scheduling model. 504 505// Branch instructions. 506def : SchedAlias<WriteBr, M4WriteZ0>; 507def : SchedAlias<WriteBrReg, M4WriteC1>; 508 509// Arithmetic and logical integer instructions. 510def : SchedAlias<WriteI, M4WriteA1>; 511def : SchedAlias<WriteIEReg, M4WriteAA>; // FIXME: M4WriteAX crashes TableGen. 512def : SchedAlias<WriteISReg, M4WriteAA>; // FIXME: M4WriteAX crashes TableGen. 513def : SchedAlias<WriteIS, M4WriteA1>; 514 515// Move instructions. 516def : SchedAlias<WriteImm, M4WriteA1>; 517 518// Divide and multiply instructions. 519def : SchedAlias<WriteID32, M4WriteD12>; 520def : SchedAlias<WriteID64, M4WriteD21>; 521def : SchedAlias<WriteIM32, M4WriteC3>; 522def : SchedAlias<WriteIM64, M4WriteCA>; 523 524// Miscellaneous instructions. 525def : SchedAlias<WriteExtr, M4WriteAY>; 526 527// Addressing modes. 528def : SchedAlias<WriteAdr, M4WriteZ1>; 529def : SchedAlias<ReadAdrBase, M4ReadAdrBase>; 530 531// Load instructions. 532def : SchedAlias<WriteLD, M4WriteL4>; 533def : SchedAlias<WriteLDHi, M4WriteZ4>; 534def : SchedAlias<WriteLDIdx, M4WriteLX>; 535 536// Store instructions. 537def : SchedAlias<WriteST, M4WriteS1>; 538def : SchedAlias<WriteSTP, M4WriteS1>; 539def : SchedAlias<WriteSTX, M4WriteS1>; 540def : SchedAlias<WriteSTIdx, M4WriteSX>; 541 542// FP data instructions. 543def : SchedAlias<WriteF, M4WriteFADD2>; 544def : SchedAlias<WriteFCmp, M4WriteNMSC2>; 545def : SchedAlias<WriteFDiv, M4WriteFDIV12>; 546def : SchedAlias<WriteFMul, M4WriteFMAC3>; 547 548// FP miscellaneous instructions. 549def : SchedAlias<WriteFCvt, M4WriteFCVT2>; 550def : SchedAlias<WriteFImm, M4WriteNALU1>; 551def : SchedAlias<WriteFCopy, M4WriteNALU1>; 552 553// FP load instructions. 554def : SchedAlias<WriteVLD, M4WriteL5>; 555 556// FP store instructions. 557def : SchedAlias<WriteVST, M4WriteVST1>; 558 559// ASIMD FP instructions. 560def : SchedAlias<WriteVd, M4WriteNALU1>; 561def : SchedAlias<WriteVq, M4WriteNALU1>; 562 563// Other miscellaneous instructions. 564def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 565def : WriteRes<WriteBarrier, []> { let Latency = 1; } 566def : WriteRes<WriteHint, []> { let Latency = 1; } 567def : WriteRes<WriteSys, []> { let Latency = 1; } 568 569//===----------------------------------------------------------------------===// 570// Generic fast forwarding. 571 572// TODO: Add FP register forwarding rules. 573 574def : ReadAdvance<ReadI, 0>; 575def : ReadAdvance<ReadISReg, 0>; 576def : ReadAdvance<ReadIEReg, 0>; 577def : ReadAdvance<ReadIM, 0>; 578// TODO: The forwarding for 32 bits actually saves 2 cycles. 579def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>; 580def : ReadAdvance<ReadID, 0>; 581def : ReadAdvance<ReadExtrHi, 0>; 582def : ReadAdvance<ReadAdrBase, 0>; 583def : ReadAdvance<ReadVLD, 0>; 584def : ReadAdvance<ReadST, 0>; 585 586//===----------------------------------------------------------------------===// 587// Finer scheduling model. 588 589// Branch instructions 590def : InstRW<[M4WriteB1], (instrs Bcc)>; 591def : InstRW<[M4WriteAF], (instrs BL)>; 592def : InstRW<[M4WriteBX], (instrs BLR)>; 593def : InstRW<[M4WriteC1], (instregex "^CBN?Z[WX]")>; 594def : InstRW<[M4WriteAD], (instregex "^TBN?Z[WX]")>; 595 596// Arithmetic and logical integer instructions. 597def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>; 598def : InstRW<[M4WriteAU], (instrs ORRWrs, ORRXrs)>; 599def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>; 600def : InstRW<[M4WriteAX], (instregex "^(ADD|SUB)S?[WX]rx(64)?$")>; 601def : InstRW<[M4WriteAV], (instrs ADDWri, ADDXri, ORRWri, ORRXri)>; 602 603// Move instructions. 604def : InstRW<[M4WriteCOPY], (instrs COPY)>; 605def : InstRW<[M4WriteZ0], (instrs ADR, ADRP)>; 606def : InstRW<[M4WriteZ0], (instregex "^MOV[NZ][WX]i")>; 607 608// Divide and multiply instructions. 609 610// Miscellaneous instructions. 611 612// Load instructions. 613def : InstRW<[M4WriteLD, 614 WriteLDHi, 615 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>; 616def : InstRW<[M4WriteL5, 617 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>; 618def : InstRW<[WriteLDIdx, 619 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>; 620def : InstRW<[M4WriteL5, 621 ReadAdrBase], (instrs PRFMroW)>; 622def : InstRW<[WriteLDIdx, 623 ReadAdrBase], (instrs PRFMroX)>; 624 625// Store instructions. 626def : InstRW<[M4WriteSB, 627 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>; 628def : InstRW<[WriteST, 629 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>; 630 631// FP data instructions. 632def : InstRW<[M4WriteNSHF1H], (instrs FABSHr)>; 633def : InstRW<[M4WriteNSHF1], (instregex "^FABS[SD]r")>; 634def : InstRW<[M4WriteFADD2H], (instregex "^F(ADD|SUB)Hrr")>; 635def : InstRW<[M4WriteFADD2], (instregex "^F(ADD|SUB)[SD]rr")>; 636def : InstRW<[M4WriteFADD2H], (instregex "^FADDPv.i16")>; 637def : InstRW<[M4WriteFADD2], (instregex "^FADDPv.i(32|64)")>; 638def : InstRW<[M4WriteNEONQ], (instregex "^FCCMPE?[HSD]rr")>; 639def : InstRW<[M4WriteNMSC2], (instregex "^FCMPE?[HSD]r[ir]")>; 640def : InstRW<[M4WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)(16|32|64|v1)")>; 641def : InstRW<[M4WriteFDIV7H], (instrs FDIVHrr)>; 642def : InstRW<[M4WriteFDIV7], (instrs FDIVSrr)>; 643def : InstRW<[M4WriteFDIV12], (instrs FDIVDrr)>; 644def : InstRW<[M4WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?[HSD]rr")>; 645def : InstRW<[M4WriteFMAC3H], (instregex "^FN?MULHrr")>; 646def : InstRW<[M4WriteFMAC3], (instregex "^FN?MUL[SD]rr")>; 647def : InstRW<[M4WriteFMAC3H], (instrs FMULX16)>; 648def : InstRW<[M4WriteFMAC3], (instregex "^FMULX(32|64)")>; 649def : InstRW<[M4WriteFMAC4H, 650 M4ReadFMACM1], (instregex "^FN?M(ADD|SUB)Hrrr")>; 651def : InstRW<[M4WriteFMAC4, 652 M4ReadFMACM1], (instregex "^FN?M(ADD|SUB)[SD]rrr")>; 653def : InstRW<[M4WriteNALU1H], (instrs FNEGHr)>; 654def : InstRW<[M4WriteNALU1], (instregex "^FNEG[SD]r")>; 655def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT.+r")>; 656def : InstRW<[M4WriteNEONH], (instregex "^FCSEL[HSD]rrr")>; 657def : InstRW<[M4WriteFSQR7H], (instrs FSQRTHr)>; 658def : InstRW<[M4WriteFSQR8], (instrs FSQRTSr)>; 659def : InstRW<[M4WriteFSQR12], (instrs FSQRTDr)>; 660 661// FP miscellaneous instructions. 662def : InstRW<[M4WriteFCVT2H], (instregex "^FCVTH[SD]r")>; 663def : InstRW<[M4WriteFCVT2H], (instregex "^FCVT[SD]Hr")>; 664def : InstRW<[M4WriteFCVT2], (instregex "^FCVT[SD][SD]r")>; 665def : InstRW<[M4WriteFCVT6A], (instregex "^[SU]CVTF[SU][XW][HSD]ri")>; 666def : InstRW<[M4WriteNEONR], (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>; 667def : InstRW<[M4WriteNALU1], (instregex "^FMOV[HSD][ir]")>; 668def : InstRW<[M4WriteSA], (instregex "^FMOV[WX][HSD]r")>; 669def : InstRW<[M4WriteNEONJ], (instregex "^FMOV[HSD][WX]r")>; 670def : InstRW<[M4WriteNEONI], (instregex "^FMOVXDHighr")>; 671def : InstRW<[M4WriteNEONK], (instregex "^FMOVDXHighr")>; 672def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev1f16")>; 673def : InstRW<[M4WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev1i(32|64)")>; 674def : InstRW<[M4WriteNMSC1], (instregex "^FRECPXv1")>; 675def : InstRW<[M4WriteFMAC4H], (instregex "^F(RECP|RSQRT)S16")>; 676def : InstRW<[M4WriteFMAC4], (instregex "^F(RECP|RSQRT)S(32|64)")>; 677 678// FP load instructions. 679def : InstRW<[WriteVLD], (instregex "^LDR[SDQ]l")>; 680def : InstRW<[WriteVLD], (instregex "^LDUR[BHSDQ]i")>; 681def : InstRW<[WriteVLD, 682 WriteAdr], (instregex "^LDR[BHSDQ](post|pre)")>; 683def : InstRW<[WriteVLD], (instregex "^LDR[BHSDQ]ui")>; 684def : InstRW<[M4WriteLE, 685 ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>; 686def : InstRW<[WriteVLD, 687 ReadAdrBase], (instregex "^LDR[BHSD]roX")>; 688def : InstRW<[M4WriteLY, 689 ReadAdrBase], (instrs LDRQroX)>; 690def : InstRW<[WriteVLD, 691 M4WriteLH], (instregex "^LDN?P[SD]i")>; 692def : InstRW<[M4WriteLA, 693 M4WriteLH], (instregex "^LDN?PQi")>; 694def : InstRW<[M4WriteL5, 695 M4WriteLH, 696 WriteAdr], (instregex "^LDP[SD]post")>; 697def : InstRW<[M4WriteLB, 698 M4WriteLH, 699 WriteAdr], (instrs LDPQpost)>; 700def : InstRW<[M4WriteLB, 701 M4WriteLH, 702 WriteAdr], (instregex "^LDP[SD]pre")>; 703def : InstRW<[M4WriteLC, 704 M4WriteLH, 705 WriteAdr], (instrs LDPQpre)>; 706 707// FP store instructions. 708def : InstRW<[WriteVST], (instregex "^STUR[BHSDQ]i")>; 709def : InstRW<[WriteVST, 710 WriteAdr], (instregex "^STR[BHSDQ](post|pre)")>; 711def : InstRW<[WriteVST], (instregex "^STR[BHSDQ]ui")>; 712def : InstRW<[M4WriteVSTK, 713 ReadAdrBase], (instregex "^STR[BHSD]roW")>; 714def : InstRW<[M4WriteVSTK, 715 ReadAdrBase], (instrs STRQroW)>; 716def : InstRW<[WriteVST, 717 ReadAdrBase], (instregex "^STR[BHSD]roX")>; 718def : InstRW<[M4WriteVSTY, 719 ReadAdrBase], (instrs STRQroX)>; 720def : InstRW<[WriteVST], (instregex "^STN?P[SD]i")>; 721def : InstRW<[M4WriteVSTJ], (instregex "^STN?PQi")>; 722def : InstRW<[WriteVST, 723 WriteAdr], (instregex "^STP[SD](post|pre)")>; 724def : InstRW<[M4WriteVSTJ, 725 WriteAdr], (instregex "^STPQ(post|pre)")>; 726 727// ASIMD instructions. 728def : InstRW<[M4WriteNHAD1], (instregex "^[SU]ABDL?v")>; 729def : InstRW<[M4WriteNHAD3], (instregex "^[SU]ABAL?v")>; 730def : InstRW<[M4WriteNMSC1], (instregex "^ABSv")>; 731def : InstRW<[M4WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>; 732def : InstRW<[M4WriteNHAD3], (instregex "^[SU]?ADDL?Pv")>; 733def : InstRW<[M4WriteNHAD3], (instregex "^[SU]H(ADD|SUB)v")>; 734def : InstRW<[M4WriteNHAD3], (instregex "^[SU](ADD|SUB)[LW]v")>; 735def : InstRW<[M4WriteNHAD3], (instregex "^R?(ADD|SUB)HN2?v")>; 736def : InstRW<[M4WriteNHAD3], (instregex "^[SU]Q(ADD|SUB)v")>; 737def : InstRW<[M4WriteNHAD3], (instregex "^(SU|US)QADDv")>; 738def : InstRW<[M4WriteNHAD3], (instregex "^[SU]RHADDv")>; 739def : InstRW<[M4WriteNMSC1], (instregex "^SQ(ABS|NEG)v")>; 740def : InstRW<[M4WriteNHAD3], (instregex "^[SU]?ADDL?Vv")>; 741def : InstRW<[M4WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>; 742def : InstRW<[M4WriteNALU1], (instregex "^CMTSTv")>; 743def : InstRW<[M4WriteNALU1], (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>; 744def : InstRW<[M4WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>; 745def : InstRW<[M4WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>; 746def : InstRW<[M4WriteNHAD3], (instregex "^[SU](MIN|MAX)Vv")>; 747def : InstRW<[M4WriteNMUL3, 748 M4ReadNMULM1], (instregex "^ML[AS]v")>; 749def : InstRW<[M4WriteNMUL3, 750 M4ReadNMULM1], (instregex "^(SQR?D)?MULH?v")>; 751def : InstRW<[M4WriteNMUL3, 752 M4ReadNMULM1], (instregex "^SQRDML[AS]H")>; 753def : InstRW<[M4WriteNMUL3, 754 M4ReadNMULM1], (instregex "^(S|U|SQD)ML[AS]L(v1(i32|i64)|v2i32|v4i16|v8i8)")>; 755def : InstRW<[M4WriteNMUL3, 756 M4ReadNMULP2], (instregex "^(S|U|SQD)ML[AS]L(v4i32|v8i16|v16i8)")>; 757def : InstRW<[M4WriteNMUL3, 758 M4ReadNMULM1], (instregex "^(S|U|SQD)MULL(v1(i32|i64)|v2i32|v4i16|v8i8)")>; 759def : InstRW<[M4WriteNMUL3, 760 M4ReadNMULP2], (instregex "^(S|U|SQD)MULL(v4i32|v8i16|v16i8)")>; 761def : InstRW<[M4WriteNMUL3], (instregex "^[SU]DOT(lane)?v")>; 762def : InstRW<[M4WriteNHAD3], (instregex "^[SU]ADALPv")>; 763def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]R?SRA[dv]")>; 764def : InstRW<[M4WriteNSHT1], (instregex "^SHL[dv]")>; 765def : InstRW<[M4WriteNSHT1], (instregex "^S[LR]I[dv]")>; 766def : InstRW<[M4WriteNSHT1], (instregex "^[SU]SH[LR][dv]")>; 767def : InstRW<[M4WriteNSHT2], (instregex "^[SU]?SHLLv")>; 768def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?Q?R?SHRU?N[bhsv]")>; 769def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]RSH[LR][dv]")>; 770def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]QR?SHLU?[bhsdv]")>; 771 772// ASIMD FP instructions. 773def : InstRW<[M4WriteNSHF1H], (instregex "^FABSv.f16")>; 774def : InstRW<[M4WriteNSHF1], (instregex "^FABSv.f(32|64)")>; 775def : InstRW<[M4WriteFADD2H], (instregex "^F(ABD|ADD|SUB)v.f16")>; 776def : InstRW<[M4WriteFADD2], (instregex "^F(ABD|ADD|SUB)v.f(32|64)")>; 777def : InstRW<[M4WriteFADD2H], (instregex "^FADDPv.f16")>; 778def : InstRW<[M4WriteFADD2], (instregex "^FADDPv.f(32|64)")>; 779def : InstRW<[M4WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>; 780def : InstRW<[M4WriteFCVT2], (instregex "^FCVT(L|N|XN)v")>; 781def : InstRW<[M4WriteFCVT2A], (instregex "^FCVT[AMNPZ][SU]v")>; 782def : InstRW<[M4WriteFCVT2H], (instregex "^[SU]CVTFv.[fi]16")>; 783def : InstRW<[M4WriteFCVT2], (instregex "^[SU]CVTFv.[fi](32|64)")>; 784def : InstRW<[M4WriteFDIV7H], (instrs FDIVv4f16)>; 785def : InstRW<[M4WriteNEONVH], (instrs FDIVv8f16)>; 786def : InstRW<[M4WriteFDIV7], (instrs FDIVv2f32)>; 787def : InstRW<[M4WriteNEONV], (instrs FDIVv4f32)>; 788def : InstRW<[M4WriteNEONW], (instrs FDIVv2f64)>; 789def : InstRW<[M4WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?v")>; 790def : InstRW<[M4WriteNMSC2], (instregex "^F(MAX|MIN)(NM)?Pv")>; 791def : InstRW<[M4WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>; 792def : InstRW<[M4WriteFMAC2H], (instregex "^FMULX?v.[fi]16")>; 793def : InstRW<[M4WriteFMAC3], (instregex "^FMULX?v.[fi](32|64)")>; 794def : InstRW<[M4WriteFMAC4H, 795 M4ReadFMACM1], (instregex "^FML[AS]v.[fi]16")>; 796def : InstRW<[M4WriteFMAC4, 797 M4ReadFMACM1], (instregex "^FML[AS]v.[fi](32|64)")>; 798def : InstRW<[M4WriteNALU1H], (instregex "^FNEGv.f16")>; 799def : InstRW<[M4WriteNALU1], (instregex "^FNEGv.f(32|64)")>; 800def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>; 801def : InstRW<[M4WriteFSQR7H], (instrs FSQRTv4f16)>; 802def : InstRW<[M4WriteNEONXH], (instrs FSQRTv8f16)>; 803def : InstRW<[M4WriteFSQR8], (instrs FSQRTv2f32)>; 804def : InstRW<[M4WriteNEONX], (instrs FSQRTv4f32)>; 805def : InstRW<[M4WriteNEONY], (instrs FSQRTv2f64)>; 806 807// ASIMD miscellaneous instructions. 808def : InstRW<[M4WriteNALU1], (instregex "^RBITv")>; 809def : InstRW<[M4WriteNALU1], (instregex "^(BIF|BIT|BSL|BSP)v")>; 810def : InstRW<[M4WriteNALU1], (instregex "^CL[STZ]v")>; 811def : InstRW<[M4WriteNEONB], (instregex "^DUPv.+gpr")>; 812def : InstRW<[M4WriteNSHF1], (instregex "^DUP(i8|i16|i32|i64)$")>; 813def : InstRW<[M4WriteNSHF1], (instregex "^DUPv.+lane")>; 814def : InstRW<[M4WriteNSHF1], (instregex "^EXTv")>; 815def : InstRW<[M4WriteNSHT4A], (instregex "^XTNv")>; 816def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?QXTU?Nv")>; 817def : InstRW<[M4WriteNEONB], (instregex "^INSv.+gpr")>; 818def : InstRW<[M4WriteNSHF1], (instregex "^INSv.+lane")>; 819def : InstRW<[M4WriteMOVI], (instregex "^(MOV|MVN)I")>; 820def : InstRW<[M4WriteNALU1H], (instregex "^FMOVv.f16")>; 821def : InstRW<[M4WriteNALU1], (instregex "^FMOVv.f(32|64)")>; 822def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev[248]f16")>; 823def : InstRW<[M4WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev[248]f(32|64)")>; 824def : InstRW<[M4WriteFCVT3], (instregex "^U(RECP|RSQRT)Ev[24]i32")>; 825def : InstRW<[M4WriteFMAC4H], (instregex "^F(RECP|RSQRT)Sv.f16")>; 826def : InstRW<[M4WriteFMAC4], (instregex "^F(RECP|RSQRT)Sv.f(32|64)")>; 827def : InstRW<[M4WriteNSHF1], (instregex "^REV(16|32|64)v")>; 828def : InstRW<[M4WriteNSHFA], (instregex "^TB[LX]v(8|16)i8One")>; 829def : InstRW<[M4WriteNSHFB], (instregex "^TB[LX]v(8|16)i8Two")>; 830def : InstRW<[M4WriteNSHFC], (instregex "^TB[LX]v(8|16)i8Three")>; 831def : InstRW<[M4WriteNSHFD], (instregex "^TB[LX]v(8|16)i8Four")>; 832def : InstRW<[M4WriteNEONP], (instregex "^[SU]MOVv")>; 833def : InstRW<[M4WriteNSHF1], (instregex "^(TRN|UZP|ZIP)[12]v")>; 834 835// ASIMD load instructions. 836def : InstRW<[WriteVLD], (instregex "LD1Onev(8b|4h|2s|1d)$")>; 837def : InstRW<[WriteVLD, 838 M4WriteA1], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>; 839def : InstRW<[WriteVLD], (instregex "LD1Onev(16b|8h|4s|2d)$")>; 840def : InstRW<[WriteVLD, 841 M4WriteA1], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>; 842 843def : InstRW<[M4WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>; 844def : InstRW<[M4WriteVLDA, 845 M4WriteA1], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>; 846def : InstRW<[M4WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>; 847def : InstRW<[M4WriteVLDA, 848 M4WriteA1], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>; 849 850def : InstRW<[M4WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>; 851def : InstRW<[M4WriteVLDB, 852 M4WriteA1], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>; 853def : InstRW<[M4WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>; 854def : InstRW<[M4WriteVLDB, 855 M4WriteA1], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>; 856 857def : InstRW<[M4WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>; 858def : InstRW<[M4WriteVLDC, 859 M4WriteA1], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>; 860def : InstRW<[M4WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>; 861def : InstRW<[M4WriteVLDC, 862 M4WriteA1], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>; 863 864def : InstRW<[M4WriteVLDD], (instregex "LD1i(8|16|32|64)$")>; 865def : InstRW<[M4WriteVLDD, 866 M4WriteA1], (instregex "LD1i(8|16|32|64)_POST$")>; 867 868def : InstRW<[WriteVLD], (instregex "LD1Rv(8b|4h|2s|1d)$")>; 869def : InstRW<[WriteVLD, 870 M4WriteA1], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>; 871def : InstRW<[WriteVLD], (instregex "LD1Rv(16b|8h|4s|2d)$")>; 872def : InstRW<[WriteVLD, 873 M4WriteA1], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>; 874 875def : InstRW<[M4WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>; 876def : InstRW<[M4WriteVLDF, 877 M4WriteA1], (instregex "LD2Twov(8b|4h|2s)_POST$")>; 878def : InstRW<[M4WriteVLDF], (instregex "LD2Twov(16b|8h|4s|2d)$")>; 879def : InstRW<[M4WriteVLDF, 880 M4WriteA1], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>; 881 882def : InstRW<[M4WriteVLDG], (instregex "LD2i(8|16|32|64)$")>; 883def : InstRW<[M4WriteVLDG, 884 M4WriteA1], (instregex "LD2i(8|16|32|64)_POST$")>; 885 886def : InstRW<[M4WriteVLDA], (instregex "LD2Rv(8b|4h|2s|1d)$")>; 887def : InstRW<[M4WriteVLDA, 888 M4WriteA1], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>; 889def : InstRW<[M4WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>; 890def : InstRW<[M4WriteVLDA, 891 M4WriteA1], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>; 892 893def : InstRW<[M4WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>; 894def : InstRW<[M4WriteVLDI, 895 M4WriteA1], (instregex "LD3Threev(8b|4h|2s)_POST$")>; 896def : InstRW<[M4WriteVLDI], (instregex "LD3Threev(16b|8h|4s|2d)$")>; 897def : InstRW<[M4WriteVLDI, 898 M4WriteA1], (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>; 899 900def : InstRW<[M4WriteVLDJ], (instregex "LD3i(8|16|32)$")>; 901def : InstRW<[M4WriteVLDJ, 902 M4WriteA1], (instregex "LD3i(8|16|32)_POST$")>; 903def : InstRW<[M4WriteVLDL], (instregex "LD3i64$")>; 904def : InstRW<[M4WriteVLDL, 905 M4WriteA1], (instregex "LD3i64_POST$")>; 906 907def : InstRW<[M4WriteVLDB], (instregex "LD3Rv(8b|4h|2s|1d)$")>; 908def : InstRW<[M4WriteVLDB, 909 M4WriteA1], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>; 910def : InstRW<[M4WriteVLDB], (instregex "LD3Rv(16b|8h|4s|2d)$")>; 911def : InstRW<[M4WriteVLDB, 912 M4WriteA1], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>; 913 914def : InstRW<[M4WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>; 915def : InstRW<[M4WriteVLDN, 916 M4WriteA1], (instregex "LD4Fourv(8b|4h|2s)_POST$")>; 917def : InstRW<[M4WriteVLDN], (instregex "LD4Fourv(16b|8h|4s|2d)$")>; 918def : InstRW<[M4WriteVLDN, 919 M4WriteA1], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>; 920 921def : InstRW<[M4WriteVLDK], (instregex "LD4i(8|16|32)$")>; 922def : InstRW<[M4WriteVLDK, 923 M4WriteA1], (instregex "LD4i(8|16|32)_POST$")>; 924def : InstRW<[M4WriteVLDM], (instregex "LD4i64$")>; 925def : InstRW<[M4WriteVLDM, 926 M4WriteA1], (instregex "LD4i64_POST$")>; 927 928def : InstRW<[M4WriteVLDC], (instregex "LD4Rv(8b|4h|2s|1d)$")>; 929def : InstRW<[M4WriteVLDC, 930 M4WriteA1], (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>; 931def : InstRW<[M4WriteVLDC], (instregex "LD4Rv(16b|8h|4s|2d)$")>; 932def : InstRW<[M4WriteVLDC, 933 M4WriteA1], (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>; 934 935// ASIMD store instructions. 936def : InstRW<[WriteVST], (instregex "ST1Onev(8b|4h|2s|1d)$")>; 937def : InstRW<[WriteVST, 938 M4WriteA1], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>; 939def : InstRW<[WriteVST], (instregex "ST1Onev(16b|8h|4s|2d)$")>; 940def : InstRW<[WriteVST, 941 M4WriteA1], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>; 942 943def : InstRW<[M4WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>; 944def : InstRW<[M4WriteVSTA, 945 M4WriteA1], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>; 946def : InstRW<[M4WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>; 947def : InstRW<[M4WriteVSTA, 948 M4WriteA1], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>; 949 950def : InstRW<[M4WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>; 951def : InstRW<[M4WriteVSTB, 952 M4WriteA1], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>; 953def : InstRW<[M4WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>; 954def : InstRW<[M4WriteVSTB, 955 M4WriteA1], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>; 956 957def : InstRW<[M4WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; 958def : InstRW<[M4WriteVSTC, 959 M4WriteA1], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>; 960def : InstRW<[M4WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; 961def : InstRW<[M4WriteVSTC, 962 M4WriteA1], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>; 963 964def : InstRW<[WriteVST], (instregex "ST1i(8|16|32|64)$")>; 965def : InstRW<[WriteVST, 966 M4WriteA1], (instregex "ST1i(8|16|32|64)_POST$")>; 967 968def : InstRW<[M4WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>; 969def : InstRW<[M4WriteVSTD, 970 M4WriteA1], (instregex "ST2Twov(8b|4h|2s)_POST$")>; 971def : InstRW<[M4WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>; 972def : InstRW<[M4WriteVSTE, 973 M4WriteA1], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>; 974 975def : InstRW<[M4WriteVSTD], (instregex "ST2i(8|16|32|64)$")>; 976def : InstRW<[M4WriteVSTD, 977 M4WriteA1], (instregex "ST2i(8|16|32|64)_POST$")>; 978 979def : InstRW<[M4WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>; 980def : InstRW<[M4WriteVSTF, 981 M4WriteA1], (instregex "ST3Threev(8b|4h|2s)_POST$")>; 982def : InstRW<[M4WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>; 983def : InstRW<[M4WriteVSTG, 984 M4WriteA1], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>; 985 986def : InstRW<[M4WriteVSTE], (instregex "ST3i(8|16|32|64)$")>; 987def : InstRW<[M4WriteVSTE, 988 M4WriteA1], (instregex "ST3i(8|16|32|64)_POST$")>; 989 990def : InstRW<[M4WriteVSTL], (instregex "ST4Fourv(8b|4h|2s)$")>; 991def : InstRW<[M4WriteVSTL, 992 M4WriteA1], (instregex "ST4Fourv(8b|4h|2s)_POST$")>; 993def : InstRW<[M4WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>; 994def : InstRW<[M4WriteVSTI, 995 M4WriteA1], (instregex "ST4Fourv(16b|8h|4s|2d)_POST$")>; 996 997def : InstRW<[M4WriteVSTE], (instregex "ST4i(8|16|32|64)$")>; 998def : InstRW<[M4WriteVSTE, 999 M4WriteA1], (instregex "ST4i(8|16|32|64)_POST$")>; 1000 1001// Cryptography instructions. 1002def : InstRW<[M4WriteNCRY1], (instregex "^AES[DE]")>; 1003def : InstRW<[M4WriteNCRY1, 1004 M4ReadAESM1], (instregex "^AESI?MC")>; 1005def : InstRW<[M4WriteNCRY1A], (instregex "^PMULv")>; 1006def : InstRW<[M4WriteNCRY1A], (instregex "^PMULLv(1|8)i")>; 1007def : InstRW<[M4WriteNCRY3A], (instregex "^PMULLv(2|16)i")>; 1008def : InstRW<[M4WriteNCRY1A], (instregex "^SHA1([CHMP]|SU[01])")>; 1009def : InstRW<[M4WriteNCRY1A], (instrs SHA256SU0rr)>; 1010def : InstRW<[M4WriteNCRY5A], (instrs SHA256SU1rrr)>; 1011def : InstRW<[M4WriteNCRY5A], (instrs SHA256H2rrr)>; 1012 1013// CRC instructions. 1014def : InstRW<[M4WriteE2], (instregex "^CRC32C?[BHWX]rr$")>; 1015 1016} // SchedModel = ExynosM4Model 1017