1//=- AArch64SchedExynosM4.td - Samsung Exynos M4 Sched Defs --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for the Samsung Exynos M4 to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// The Exynos-M4 is an advanced superscalar microprocessor with a 6-wide 16// in-order stage for decode and dispatch and a wider issue stage. 17// The execution units and loads and stores are out-of-order. 18 19def ExynosM4Model : SchedMachineModel { 20 let IssueWidth = 6; // Up to 6 uops per cycle. 21 let MicroOpBufferSize = 228; // ROB size. 22 let LoopMicroOpBufferSize = 48; // Based on the instruction queue size. 23 let LoadLatency = 4; // Optimistic load cases. 24 let MispredictPenalty = 16; // Minimum branch misprediction penalty. 25 let CompleteModel = 1; // Use the default model otherwise. 26 27 list<Predicate> UnsupportedFeatures = SVEUnsupported.F; 28} 29 30//===----------------------------------------------------------------------===// 31// Define each kind of processor resource and number available on the Exynos-M4. 32 33let SchedModel = ExynosM4Model in { 34 35def M4UnitA : ProcResource<2>; // Simple integer 36def M4UnitC : ProcResource<2>; // Simple and complex integer 37let Super = M4UnitC, BufferSize = 1 in 38def M4UnitD : ProcResource<1>; // Integer division (inside C0, serialized) 39let Super = M4UnitC in 40def M4UnitE : ProcResource<1>; // CRC (inside C0) 41def M4UnitB : ProcResource<2>; // Branch 42def M4UnitL0 : ProcResource<1>; // Load 43def M4UnitS0 : ProcResource<1>; // Store 44def M4PipeLS : ProcResource<1>; // Load/Store 45let Super = M4PipeLS in { 46 def M4UnitL1 : ProcResource<1>; 47 def M4UnitS1 : ProcResource<1>; 48} 49def M4PipeF0 : ProcResource<1>; // FP #0 50let Super = M4PipeF0 in { 51 def M4UnitFMAC0 : ProcResource<1>; // FP multiplication 52 def M4UnitFADD0 : ProcResource<1>; // Simple FP 53 def M4UnitFCVT0 : ProcResource<1>; // FP conversion 54 def M4UnitNALU0 : ProcResource<1>; // Simple vector 55 def M4UnitNHAD : ProcResource<1>; // Horizontal vector 56 def M4UnitNMSC : ProcResource<1>; // FP and vector miscellanea 57 def M4UnitNMUL0 : ProcResource<1>; // Vector multiplication 58 def M4UnitNSHT0 : ProcResource<1>; // Vector shifting 59 def M4UnitNSHF0 : ProcResource<1>; // Vector shuffling 60 def M4UnitNCRY0 : ProcResource<1>; // Cryptographic 61} 62def M4PipeF1 : ProcResource<1>; // FP #1 63let Super = M4PipeF1 in { 64 def M4UnitFMAC1 : ProcResource<1>; // FP multiplication 65 def M4UnitFADD1 : ProcResource<1>; // Simple FP 66 def M4UnitFDIV0 : ProcResource<2>; // FP division (serialized) 67 def M4UnitFSQR0 : ProcResource<2>; // FP square root (serialized) 68 def M4UnitFST0 : ProcResource<1>; // FP store 69 def M4UnitNALU1 : ProcResource<1>; // Simple vector 70 def M4UnitNSHT1 : ProcResource<1>; // Vector shifting 71 def M4UnitNSHF1 : ProcResource<1>; // Vector shuffling 72} 73def M4PipeF2 : ProcResource<1>; // FP #2 74let Super = M4PipeF2 in { 75 def M4UnitFMAC2 : ProcResource<1>; // FP multiplication 76 def M4UnitFADD2 : ProcResource<1>; // Simple FP 77 def M4UnitFCVT1 : ProcResource<1>; // FP conversion 78 def M4UnitFDIV1 : ProcResource<2>; // FP division (serialized) 79 def M4UnitFSQR1 : ProcResource<2>; // FP square root (serialized) 80 def M4UnitFST1 : ProcResource<1>; // FP store 81 def M4UnitNALU2 : ProcResource<1>; // Simple vector 82 def M4UnitNMUL1 : ProcResource<1>; // Vector multiplication 83 def M4UnitNSHT2 : ProcResource<1>; // Vector shifting 84 def M4UnitNCRY1 : ProcResource<1>; // Cryptographic 85} 86 87def M4UnitALU : ProcResGroup<[M4UnitA, 88 M4UnitC]>; 89def M4UnitL : ProcResGroup<[M4UnitL0, 90 M4UnitL1]>; 91def M4UnitS : ProcResGroup<[M4UnitS0, 92 M4UnitS1]>; 93def M4UnitFMAC : ProcResGroup<[M4UnitFMAC0, 94 M4UnitFMAC1, 95 M4UnitFMAC2]>; 96def M4UnitFMACH : ProcResGroup<[M4UnitFMAC0, 97 M4UnitFMAC1]>; 98def M4UnitFADD : ProcResGroup<[M4UnitFADD0, 99 M4UnitFADD1, 100 M4UnitFADD2]>; 101def M4UnitFADDH : ProcResGroup<[M4UnitFADD0, 102 M4UnitFADD1]>; 103def M4UnitFCVT : ProcResGroup<[M4UnitFCVT0, 104 M4UnitFCVT1]>; 105def M4UnitFCVTH : ProcResGroup<[M4UnitFCVT0]>; 106def M4UnitFDIV : ProcResGroup<[M4UnitFDIV0, 107 M4UnitFDIV1]>; 108def M4UnitFDIVH : ProcResGroup<[M4UnitFDIV0]>; 109def M4UnitFSQR : ProcResGroup<[M4UnitFSQR0, 110 M4UnitFSQR1]>; 111def M4UnitFSQRH : ProcResGroup<[M4UnitFSQR0]>; 112def M4UnitFST : ProcResGroup<[M4UnitFST0, 113 M4UnitFST1]>; 114def M4UnitNALU : ProcResGroup<[M4UnitNALU0, 115 M4UnitNALU1, 116 M4UnitNALU2]>; 117def M4UnitNALUH : ProcResGroup<[M4UnitNALU0, 118 M4UnitNALU1]>; 119def M4UnitNMUL : ProcResGroup<[M4UnitNMUL0, 120 M4UnitNMUL1]>; 121def M4UnitNSHT : ProcResGroup<[M4UnitNSHT0, 122 M4UnitNSHT1, 123 M4UnitNSHT2]>; 124def M4UnitNSHF : ProcResGroup<[M4UnitNSHF0, 125 M4UnitNSHF1]>; 126def M4UnitNSHFH : ProcResGroup<[M4UnitNSHF0]>; 127def M4UnitNCRY : ProcResGroup<[M4UnitNCRY0, 128 M4UnitNCRY1]>; 129 130//===----------------------------------------------------------------------===// 131// Resources details. 132 133def M4WriteZ0 : SchedWriteRes<[]> { let Latency = 0; } 134def M4WriteZ1 : SchedWriteRes<[]> { let Latency = 1; 135 let NumMicroOps = 0; } 136def M4WriteZ4 : SchedWriteRes<[]> { let Latency = 4; 137 let NumMicroOps = 0; } 138 139def M4WriteA1 : SchedWriteRes<[M4UnitALU]> { let Latency = 1; } 140def M4WriteA2 : SchedWriteRes<[M4UnitALU]> { let Latency = 2; } 141def M4WriteAA : SchedWriteRes<[M4UnitALU]> { let Latency = 2; 142 let ResourceCycles = [2]; } 143def M4WriteAB : SchedWriteRes<[M4UnitALU, 144 M4UnitC]> { let Latency = 2; 145 let NumMicroOps = 2; } 146def M4WriteAC : SchedWriteRes<[M4UnitALU, 147 M4UnitALU, 148 M4UnitC]> { let Latency = 3; 149 let NumMicroOps = 3; } 150def M4WriteAD : SchedWriteRes<[M4UnitALU, 151 M4UnitC]> { let Latency = 2; 152 let NumMicroOps = 2; } 153def M4WriteAF : SchedWriteRes<[M4UnitALU]> { let Latency = 2; 154 let NumMicroOps = 2; } 155def M4WriteAU : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M4WriteZ0]>, 156 SchedVar<ExynosArithPred, [M4WriteA1]>, 157 SchedVar<ExynosLogicExPred, [M4WriteA1]>, 158 SchedVar<NoSchedPred, [M4WriteAA]>]>; 159def M4WriteAV : SchedWriteVariant<[SchedVar<ExynosResetPred, [M4WriteZ0]>, 160 SchedVar<ExynosArithPred, [M4WriteA1]>, 161 SchedVar<ExynosLogicExPred, [M4WriteA1]>, 162 SchedVar<NoSchedPred, [M4WriteAA]>]>; 163def M4WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M4WriteA1]>, 164 SchedVar<ExynosLogicExPred, [M4WriteA1]>, 165 SchedVar<NoSchedPred, [M4WriteAA]>]>; 166def M4WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M4WriteA1]>, 167 SchedVar<NoSchedPred, [M4WriteAF]>]>; 168 169def M4WriteB1 : SchedWriteRes<[M4UnitB]> { let Latency = 1; } 170def M4WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M4WriteAC]>, 171 SchedVar<NoSchedPred, [M4WriteAB]>]>; 172 173def M4WriteC1 : SchedWriteRes<[M4UnitC]> { let Latency = 1; } 174def M4WriteC3 : SchedWriteRes<[M4UnitC]> { let Latency = 3; } 175def M4WriteCA : SchedWriteRes<[M4UnitC]> { let Latency = 4; 176 let ResourceCycles = [2]; } 177 178def M4WriteD12 : SchedWriteRes<[M4UnitD]> { let Latency = 12; 179 let ResourceCycles = [12]; } 180def M4WriteD21 : SchedWriteRes<[M4UnitD]> { let Latency = 21; 181 let ResourceCycles = [21]; } 182 183def M4WriteE2 : SchedWriteRes<[M4UnitE]> { let Latency = 2; } 184 185def M4WriteL4 : SchedWriteRes<[M4UnitL]> { let Latency = 4; } 186def M4WriteL5 : SchedWriteRes<[M4UnitL]> { let Latency = 5; } 187def M4WriteLA : SchedWriteRes<[M4UnitL, 188 M4UnitL]> { let Latency = 5; 189 let NumMicroOps = 1; } 190def M4WriteLB : SchedWriteRes<[M4UnitA, 191 M4UnitL]> { let Latency = 5; 192 let NumMicroOps = 2; } 193def M4WriteLC : SchedWriteRes<[M4UnitA, 194 M4UnitL, 195 M4UnitL]> { let Latency = 5; 196 let NumMicroOps = 2; } 197def M4WriteLD : SchedWriteRes<[M4UnitA, 198 M4UnitL]> { let Latency = 4; 199 let NumMicroOps = 2; } 200def M4WriteLE : SchedWriteRes<[M4UnitA, 201 M4UnitL]> { let Latency = 6; 202 let NumMicroOps = 2; } 203def M4WriteLH : SchedWriteRes<[]> { let Latency = 5; 204 let NumMicroOps = 0; } 205def M4WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteL5]>, 206 SchedVar<NoSchedPred, [M4WriteL4]>]>; 207def M4WriteLY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteLE]>, 208 SchedVar<NoSchedPred, [M4WriteL5]>]>; 209 210def M4WriteS1 : SchedWriteRes<[M4UnitS]> { let Latency = 1; } 211def M4WriteSA : SchedWriteRes<[M4UnitS0]> { let Latency = 3; } 212def M4WriteSB : SchedWriteRes<[M4UnitA, 213 M4UnitS]> { let Latency = 2; 214 let NumMicroOps = 1; } 215def M4WriteSX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteSB]>, 216 SchedVar<NoSchedPred, [M4WriteS1]>]>; 217 218def M4ReadAdrBase : SchedReadVariant<[SchedVar< 219 MCSchedPredicate< 220 CheckAny< 221 [ScaledIdxFn, 222 ExynosScaledIdxFn]>>, [ReadDefault]>, 223 SchedVar<NoSchedPred, [ReadDefault]>]>; 224 225def M4WriteNEONA : SchedWriteRes<[M4UnitNSHF, 226 M4UnitFADD]> { let Latency = 3; 227 let NumMicroOps = 2; } 228def M4WriteNEONB : SchedWriteRes<[M4UnitNALU, 229 M4UnitS0]> { let Latency = 5; 230 let NumMicroOps = 2; } 231def M4WriteNEOND : SchedWriteRes<[M4UnitNSHF, 232 M4UnitFST]> { let Latency = 6; 233 let NumMicroOps = 2; } 234def M4WriteNEONH : SchedWriteRes<[M4UnitNALU, 235 M4UnitS0]> { let Latency = 5; 236 let NumMicroOps = 2; } 237def M4WriteNEONI : SchedWriteRes<[M4UnitNSHF, 238 M4UnitS0]> { let Latency = 2; 239 let NumMicroOps = 2; } 240def M4WriteNEONJ : SchedWriteRes<[M4UnitNMSC, 241 M4UnitS0]> { let Latency = 4; } 242def M4WriteNEONK : SchedWriteRes<[M4UnitNSHF, 243 M4UnitNMSC, 244 M4UnitS0]> { let Latency = 5; 245 let NumMicroOps = 2; } 246def M4WriteNEONL : SchedWriteRes<[M4UnitNMUL]> { let Latency = 3; } 247def M4WriteNEONN : SchedWriteRes<[M4UnitNMSC, 248 M4UnitNMSC]> { let Latency = 5; 249 let NumMicroOps = 2; } 250def M4WriteNEONO : SchedWriteRes<[M4UnitNMSC, 251 M4UnitNMSC, 252 M4UnitNMSC]> { let Latency = 8; 253 let NumMicroOps = 3; } 254def M4WriteNEONP : SchedWriteRes<[M4UnitNSHF, 255 M4UnitNMSC]> { let Latency = 4; 256 let NumMicroOps = 2; } 257def M4WriteNEONQ : SchedWriteRes<[M4UnitNMSC, 258 M4UnitC]> { let Latency = 3; 259 let NumMicroOps = 1; } 260def M4WriteNEONR : SchedWriteRes<[M4UnitFCVT0, 261 M4UnitS0]> { let Latency = 4; 262 let NumMicroOps = 1; } 263def M4WriteNEONV : SchedWriteRes<[M4UnitFDIV, 264 M4UnitFDIV]> { let Latency = 7; 265 let ResourceCycles = [6, 6]; } 266def M4WriteNEONVH : SchedWriteRes<[M4UnitFDIVH, 267 M4UnitFDIVH]> { let Latency = 7; 268 let ResourceCycles = [6, 6]; } 269def M4WriteNEONW : SchedWriteRes<[M4UnitFDIV, 270 M4UnitFDIV]> { let Latency = 12; 271 let ResourceCycles = [9, 9]; } 272def M4WriteNEONX : SchedWriteRes<[M4UnitFSQR, 273 M4UnitFSQR]> { let Latency = 8; 274 let ResourceCycles = [7, 7]; } 275def M4WriteNEONXH : SchedWriteRes<[M4UnitFSQRH, 276 M4UnitFSQRH]> { let Latency = 7; 277 let ResourceCycles = [6, 6]; } 278def M4WriteNEONY : SchedWriteRes<[M4UnitFSQR, 279 M4UnitFSQR]> { let Latency = 12; 280 let ResourceCycles = [9, 9]; } 281def M4WriteNEONZ : SchedWriteVariant<[SchedVar<ExynosQFormPred, [M4WriteNEONO]>, 282 SchedVar<NoSchedPred, [M4WriteNEONN]>]>; 283 284def M4WriteFADD2 : SchedWriteRes<[M4UnitFADD]> { let Latency = 2; } 285def M4WriteFADD2H : SchedWriteRes<[M4UnitFADDH]> { let Latency = 2; } 286 287def M4WriteFCVT2 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 2; } 288def M4WriteFCVT2A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 2; } 289def M4WriteFCVT2H : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 2; } 290def M4WriteFCVT3 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 3; } 291def M4WriteFCVT3A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 3; } 292def M4WriteFCVT3H : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 3; } 293def M4WriteFCVT4 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 4; } 294def M4WriteFCVT4A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 4; } 295def M4WriteFCVT6A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 6; } 296 297def M4WriteFDIV7 : SchedWriteRes<[M4UnitFDIV]> { let Latency = 7; 298 let ResourceCycles = [6]; } 299def M4WriteFDIV7H : SchedWriteRes<[M4UnitFDIVH]> { let Latency = 7; 300 let ResourceCycles = [6]; } 301def M4WriteFDIV12 : SchedWriteRes<[M4UnitFDIV]> { let Latency = 12; 302 let ResourceCycles = [9]; } 303 304def M4WriteFMAC2H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 2; } 305def M4WriteFMAC3H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 3; } 306def M4WriteFMAC3 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 3; } 307def M4WriteFMAC4 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 4; } 308def M4WriteFMAC4H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 4; } 309def M4WriteFMAC5 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 5; } 310 311def M4WriteFSQR7H : SchedWriteRes<[M4UnitFSQRH]> { let Latency = 7; 312 let ResourceCycles = [6]; } 313def M4WriteFSQR8 : SchedWriteRes<[M4UnitFSQR]> { let Latency = 8; 314 let ResourceCycles = [7]; } 315def M4WriteFSQR12 : SchedWriteRes<[M4UnitFSQR]> { let Latency = 12; 316 let ResourceCycles = [9]; } 317 318def M4WriteNALU1 : SchedWriteRes<[M4UnitNALU]> { let Latency = 1; } 319def M4WriteNALU1H : SchedWriteRes<[M4UnitNALUH]> { let Latency = 1; } 320 321def M4WriteNCRY1 : SchedWriteRes<[M4UnitNCRY]> { let Latency = 1; } 322def M4WriteNCRY1A : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 1; } 323def M4WriteNCRY3A : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 3; } 324def M4WriteNCRY5A : SchedWriteRes<[M4UnitNCRY]> { let Latency = 5; } 325 326def M4WriteNHAD1 : SchedWriteRes<[M4UnitNHAD]> { let Latency = 1; } 327def M4WriteNHAD3 : SchedWriteRes<[M4UnitNHAD]> { let Latency = 3; } 328 329def M4WriteNMSC1 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 1; } 330def M4WriteNMSC2 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 2; } 331def M4WriteNMSC3 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 3; } 332 333def M4WriteNMUL3 : SchedWriteRes<[M4UnitNMUL]> { let Latency = 3; } 334 335def M4WriteNSHF1 : SchedWriteRes<[M4UnitNSHF]> { let Latency = 1; } 336def M4WriteNSHF1H : SchedWriteRes<[M4UnitNSHFH]> { let Latency = 1; } 337def M4WriteNSHF3 : SchedWriteRes<[M4UnitNSHF]> { let Latency = 3; } 338def M4WriteNSHFA : SchedWriteRes<[M4UnitNSHF]> { let Latency = 1; 339 let ResourceCycles = [2]; } 340def M4WriteNSHFB : SchedWriteRes<[M4UnitNSHF]> { let Latency = 2; 341 let NumMicroOps = 2; 342 let ResourceCycles = [2]; } 343def M4WriteNSHFC : SchedWriteRes<[M4UnitNSHF]> { let Latency = 3; 344 let NumMicroOps = 3; 345 let ResourceCycles = [4]; } 346def M4WriteNSHFD : SchedWriteRes<[M4UnitNSHF]> { let Latency = 4; 347 let NumMicroOps = 4; 348 let ResourceCycles = [4]; } 349 350def M4WriteNSHT1 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 1; } 351def M4WriteNSHT2 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 2; } 352def M4WriteNSHT3 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 3; } 353def M4WriteNSHT4A : SchedWriteRes<[M4UnitNSHT1]> { let Latency = 4; } 354 355def M4WriteVLDA : SchedWriteRes<[M4UnitL, 356 M4UnitL]> { let Latency = 5; 357 let NumMicroOps = 2; } 358def M4WriteVLDB : SchedWriteRes<[M4UnitL, 359 M4UnitL, 360 M4UnitL]> { let Latency = 6; 361 let NumMicroOps = 3; } 362def M4WriteVLDC : SchedWriteRes<[M4UnitL, 363 M4UnitL, 364 M4UnitL, 365 M4UnitL]> { let Latency = 6; 366 let NumMicroOps = 4; } 367def M4WriteVLDD : SchedWriteRes<[M4UnitL, 368 M4UnitNSHF]> { let Latency = 6; 369 let NumMicroOps = 2; 370 let ResourceCycles = [2, 1]; } 371def M4WriteVLDF : SchedWriteRes<[M4UnitL, 372 M4UnitL]> { let Latency = 10; 373 let NumMicroOps = 2; 374 let ResourceCycles = [3, 3]; } 375def M4WriteVLDG : SchedWriteRes<[M4UnitL, 376 M4UnitNSHF, 377 M4UnitNSHF]> { let Latency = 6; 378 let NumMicroOps = 3; 379 let ResourceCycles = [2, 1, 1]; } 380def M4WriteVLDI : SchedWriteRes<[M4UnitL, 381 M4UnitL, 382 M4UnitL]> { let Latency = 12; 383 let NumMicroOps = 3; 384 let ResourceCycles = [3, 3, 3]; } 385def M4WriteVLDJ : SchedWriteRes<[M4UnitL, 386 M4UnitNSHF, 387 M4UnitNSHF, 388 M4UnitNSHF]> { let Latency = 7; 389 let NumMicroOps = 4; 390 let ResourceCycles = [3, 1, 1, 1]; } 391def M4WriteVLDK : SchedWriteRes<[M4UnitL, 392 M4UnitNSHF, 393 M4UnitNSHF, 394 M4UnitNSHF, 395 M4UnitNSHF]> { let Latency = 7; 396 let NumMicroOps = 5; 397 let ResourceCycles = [3, 1, 1, 1, 1]; } 398def M4WriteVLDL : SchedWriteRes<[M4UnitL, 399 M4UnitNSHF, 400 M4UnitNSHF, 401 M4UnitL, 402 M4UnitNSHF]> { let Latency = 7; 403 let NumMicroOps = 5; 404 let ResourceCycles = [3, 1, 1, 6, 1]; } 405def M4WriteVLDM : SchedWriteRes<[M4UnitL, 406 M4UnitNSHF, 407 M4UnitNSHF, 408 M4UnitL, 409 M4UnitNSHF, 410 M4UnitNSHF]> { let Latency = 7; 411 let NumMicroOps = 6; 412 let ResourceCycles = [3, 1, 1, 3, 1, 1]; } 413def M4WriteVLDN : SchedWriteRes<[M4UnitL, 414 M4UnitL, 415 M4UnitL, 416 M4UnitL]> { let Latency = 14; 417 let NumMicroOps = 4; 418 let ResourceCycles = [3, 3, 3, 3]; } 419 420def M4WriteVST1 : SchedWriteRes<[M4UnitS, 421 M4UnitFST]> { let Latency = 1; 422 let NumMicroOps = 1; } 423def M4WriteVSTA : WriteSequence<[WriteVST], 2>; 424def M4WriteVSTB : WriteSequence<[WriteVST], 3>; 425def M4WriteVSTC : WriteSequence<[WriteVST], 4>; 426def M4WriteVSTD : SchedWriteRes<[M4UnitS, 427 M4UnitFST]> { let Latency = 2; } 428def M4WriteVSTE : SchedWriteRes<[M4UnitS, 429 M4UnitFST, 430 M4UnitS, 431 M4UnitFST]> { let Latency = 2; 432 let NumMicroOps = 2; } 433def M4WriteVSTF : SchedWriteRes<[M4UnitNSHF, 434 M4UnitS, 435 M4UnitFST, 436 M4UnitS, 437 M4UnitFST]> { let Latency = 4; 438 let NumMicroOps = 4; 439 let ResourceCycles = [1, 2, 1, 2, 1]; } 440def M4WriteVSTG : SchedWriteRes<[M4UnitNSHF, 441 M4UnitNSHF, 442 M4UnitNSHF, 443 M4UnitS, 444 M4UnitFST, 445 M4UnitS, 446 M4UnitFST, 447 M4UnitS, 448 M4UnitFST]> { let Latency = 5; 449 let NumMicroOps = 6; 450 let ResourceCycles = [1, 1, 1, 2, 1, 2, 1, 2, 1]; } 451def M4WriteVSTI : SchedWriteRes<[M4UnitNSHF, 452 M4UnitNSHF, 453 M4UnitNSHF, 454 M4UnitNSHF, 455 M4UnitS, 456 M4UnitFST, 457 M4UnitS, 458 M4UnitFST, 459 M4UnitS, 460 M4UnitFST, 461 M4UnitS, 462 M4UnitFST]> { let Latency = 8; 463 let NumMicroOps = 5; 464 let ResourceCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; } 465def M4WriteVSTJ : SchedWriteRes<[M4UnitA, 466 M4UnitS, 467 M4UnitFST, 468 M4UnitS, 469 M4UnitFST]> { let Latency = 1; 470 let NumMicroOps = 2; } 471def M4WriteVSTK : SchedWriteRes<[M4UnitA, 472 M4UnitS, 473 M4UnitFST]> { let Latency = 3; 474 let NumMicroOps = 2; } 475def M4WriteVSTL : SchedWriteRes<[M4UnitNSHF, 476 M4UnitNSHF, 477 M4UnitS, 478 M4UnitFST, 479 M4UnitS, 480 M4UnitFST]> { let Latency = 4; 481 let NumMicroOps = 4; 482 let ResourceCycles = [1, 1, 2, 1, 2, 1]; } 483def M4WriteVSTY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteVSTK]>, 484 SchedVar<NoSchedPred, [WriteVST]>]>; 485 486// Special cases. 487def M4WriteCOPY : SchedWriteVariant<[SchedVar<ExynosFPPred, [M4WriteNALU1]>, 488 SchedVar<NoSchedPred, [M4WriteZ0]>]>; 489def M4WriteMOVI : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M4WriteZ0]>, 490 SchedVar<NoSchedPred, [M4WriteNALU1]>]>; 491 492// Fast forwarding. 493def M4ReadAESM1 : SchedReadAdvance<+1, [M4WriteNCRY1]>; 494def M4ReadFMACM1 : SchedReadAdvance<+1, [M4WriteFMAC4, 495 M4WriteFMAC4H, 496 M4WriteFMAC5]>; 497def M4ReadNMULM1 : SchedReadAdvance<+1, [M4WriteNMUL3]>; 498def M4ReadNMULP2 : SchedReadAdvance<-2, [M4WriteNMUL3]>; 499 500 501//===----------------------------------------------------------------------===// 502// Coarse scheduling model. 503 504// Branch instructions. 505def : SchedAlias<WriteBr, M4WriteZ0>; 506def : SchedAlias<WriteBrReg, M4WriteC1>; 507 508// Arithmetic and logical integer instructions. 509def : SchedAlias<WriteI, M4WriteA1>; 510def : SchedAlias<WriteIEReg, M4WriteAA>; // FIXME: M4WriteAX crashes TableGen. 511def : SchedAlias<WriteISReg, M4WriteAA>; // FIXME: M4WriteAX crashes TableGen. 512def : SchedAlias<WriteIS, M4WriteA1>; 513 514// Move instructions. 515def : SchedAlias<WriteImm, M4WriteA1>; 516 517// Divide and multiply instructions. 518def : SchedAlias<WriteID32, M4WriteD12>; 519def : SchedAlias<WriteID64, M4WriteD21>; 520def : SchedAlias<WriteIM32, M4WriteC3>; 521def : SchedAlias<WriteIM64, M4WriteCA>; 522 523// Miscellaneous instructions. 524def : SchedAlias<WriteExtr, M4WriteAY>; 525 526// Addressing modes. 527def : SchedAlias<WriteAdr, M4WriteZ1>; 528def : SchedAlias<ReadAdrBase, M4ReadAdrBase>; 529 530// Load instructions. 531def : SchedAlias<WriteLD, M4WriteL4>; 532def : SchedAlias<WriteLDHi, M4WriteZ4>; 533def : SchedAlias<WriteLDIdx, M4WriteLX>; 534 535// Store instructions. 536def : SchedAlias<WriteST, M4WriteS1>; 537def : SchedAlias<WriteSTP, M4WriteS1>; 538def : SchedAlias<WriteSTX, M4WriteS1>; 539def : SchedAlias<WriteSTIdx, M4WriteSX>; 540 541// FP data instructions. 542def : SchedAlias<WriteF, M4WriteFADD2>; 543def : SchedAlias<WriteFCmp, M4WriteNMSC2>; 544def : SchedAlias<WriteFDiv, M4WriteFDIV12>; 545def : SchedAlias<WriteFMul, M4WriteFMAC3>; 546 547// FP miscellaneous instructions. 548def : SchedAlias<WriteFCvt, M4WriteFCVT2>; 549def : SchedAlias<WriteFImm, M4WriteNALU1>; 550def : SchedAlias<WriteFCopy, M4WriteNALU1>; 551 552// FP load instructions. 553def : SchedAlias<WriteVLD, M4WriteL5>; 554 555// FP store instructions. 556def : SchedAlias<WriteVST, M4WriteVST1>; 557 558// ASIMD FP instructions. 559def : SchedAlias<WriteV, M4WriteNALU1>; 560 561// Other miscellaneous instructions. 562def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 563def : WriteRes<WriteBarrier, []> { let Latency = 1; } 564def : WriteRes<WriteHint, []> { let Latency = 1; } 565def : WriteRes<WriteSys, []> { let Latency = 1; } 566 567//===----------------------------------------------------------------------===// 568// Generic fast forwarding. 569 570// TODO: Add FP register forwarding rules. 571 572def : ReadAdvance<ReadI, 0>; 573def : ReadAdvance<ReadISReg, 0>; 574def : ReadAdvance<ReadIEReg, 0>; 575def : ReadAdvance<ReadIM, 0>; 576// TODO: The forwarding for 32 bits actually saves 2 cycles. 577def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>; 578def : ReadAdvance<ReadID, 0>; 579def : ReadAdvance<ReadExtrHi, 0>; 580def : ReadAdvance<ReadAdrBase, 0>; 581def : ReadAdvance<ReadVLD, 0>; 582 583//===----------------------------------------------------------------------===// 584// Finer scheduling model. 585 586// Branch instructions 587def : InstRW<[M4WriteB1], (instrs Bcc)>; 588def : InstRW<[M4WriteAF], (instrs BL)>; 589def : InstRW<[M4WriteBX], (instrs BLR)>; 590def : InstRW<[M4WriteC1], (instregex "^CBN?Z[WX]")>; 591def : InstRW<[M4WriteAD], (instregex "^TBN?Z[WX]")>; 592 593// Arithmetic and logical integer instructions. 594def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>; 595def : InstRW<[M4WriteAU], (instrs ORRWrs, ORRXrs)>; 596def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>; 597def : InstRW<[M4WriteAX], (instregex "^(ADD|SUB)S?[WX]rx(64)?$")>; 598def : InstRW<[M4WriteAV], (instrs ADDWri, ADDXri, ORRWri, ORRXri)>; 599 600// Move instructions. 601def : InstRW<[M4WriteCOPY], (instrs COPY)>; 602def : InstRW<[M4WriteZ0], (instrs ADR, ADRP)>; 603def : InstRW<[M4WriteZ0], (instregex "^MOV[NZ][WX]i")>; 604 605// Divide and multiply instructions. 606 607// Miscellaneous instructions. 608 609// Load instructions. 610def : InstRW<[M4WriteLD, 611 WriteLDHi, 612 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>; 613def : InstRW<[M4WriteL5, 614 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>; 615def : InstRW<[WriteLDIdx, 616 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>; 617def : InstRW<[M4WriteL5, 618 ReadAdrBase], (instrs PRFMroW)>; 619def : InstRW<[WriteLDIdx, 620 ReadAdrBase], (instrs PRFMroX)>; 621 622// Store instructions. 623def : InstRW<[M4WriteSB, 624 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>; 625def : InstRW<[WriteST, 626 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>; 627 628// FP data instructions. 629def : InstRW<[M4WriteNSHF1H], (instrs FABSHr)>; 630def : InstRW<[M4WriteNSHF1], (instregex "^FABS[SD]r")>; 631def : InstRW<[M4WriteFADD2H], (instregex "^F(ADD|SUB)Hrr")>; 632def : InstRW<[M4WriteFADD2], (instregex "^F(ADD|SUB)[SD]rr")>; 633def : InstRW<[M4WriteFADD2H], (instregex "^FADDPv.i16")>; 634def : InstRW<[M4WriteFADD2], (instregex "^FADDPv.i(32|64)")>; 635def : InstRW<[M4WriteNEONQ], (instregex "^FCCMPE?[HSD]rr")>; 636def : InstRW<[M4WriteNMSC2], (instregex "^FCMPE?[HSD]r[ir]")>; 637def : InstRW<[M4WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)(16|32|64|v1)")>; 638def : InstRW<[M4WriteFDIV7H], (instrs FDIVHrr)>; 639def : InstRW<[M4WriteFDIV7], (instrs FDIVSrr)>; 640def : InstRW<[M4WriteFDIV12], (instrs FDIVDrr)>; 641def : InstRW<[M4WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?[HSD]rr")>; 642def : InstRW<[M4WriteFMAC3H], (instregex "^FN?MULHrr")>; 643def : InstRW<[M4WriteFMAC3], (instregex "^FN?MUL[SD]rr")>; 644def : InstRW<[M4WriteFMAC3H], (instrs FMULX16)>; 645def : InstRW<[M4WriteFMAC3], (instregex "^FMULX(32|64)")>; 646def : InstRW<[M4WriteFMAC4H, 647 M4ReadFMACM1], (instregex "^FN?M(ADD|SUB)Hrrr")>; 648def : InstRW<[M4WriteFMAC4, 649 M4ReadFMACM1], (instregex "^FN?M(ADD|SUB)[SD]rrr")>; 650def : InstRW<[M4WriteNALU1H], (instrs FNEGHr)>; 651def : InstRW<[M4WriteNALU1], (instregex "^FNEG[SD]r")>; 652def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT.+r")>; 653def : InstRW<[M4WriteNEONH], (instregex "^FCSEL[HSD]rrr")>; 654def : InstRW<[M4WriteFSQR7H], (instrs FSQRTHr)>; 655def : InstRW<[M4WriteFSQR8], (instrs FSQRTSr)>; 656def : InstRW<[M4WriteFSQR12], (instrs FSQRTDr)>; 657 658// FP miscellaneous instructions. 659def : InstRW<[M4WriteFCVT2H], (instregex "^FCVTH[SD]r")>; 660def : InstRW<[M4WriteFCVT2H], (instregex "^FCVT[SD]Hr")>; 661def : InstRW<[M4WriteFCVT2], (instregex "^FCVT[SD][SD]r")>; 662def : InstRW<[M4WriteFCVT6A], (instregex "^[SU]CVTF[SU][XW][HSD]ri")>; 663def : InstRW<[M4WriteNEONR], (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>; 664def : InstRW<[M4WriteNALU1], (instregex "^FMOV[HSD][ir]")>; 665def : InstRW<[M4WriteSA], (instregex "^FMOV[WX][HSD]r")>; 666def : InstRW<[M4WriteNEONJ], (instregex "^FMOV[HSD][WX]r")>; 667def : InstRW<[M4WriteNEONI], (instregex "^FMOVXDHighr")>; 668def : InstRW<[M4WriteNEONK], (instregex "^FMOVDXHighr")>; 669def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev1f16")>; 670def : InstRW<[M4WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev1i(32|64)")>; 671def : InstRW<[M4WriteNMSC1], (instregex "^FRECPXv1")>; 672def : InstRW<[M4WriteFMAC4H], (instregex "^F(RECP|RSQRT)S16")>; 673def : InstRW<[M4WriteFMAC4], (instregex "^F(RECP|RSQRT)S(32|64)")>; 674 675// FP load instructions. 676def : InstRW<[WriteVLD], (instregex "^LDR[SDQ]l")>; 677def : InstRW<[WriteVLD], (instregex "^LDUR[BHSDQ]i")>; 678def : InstRW<[WriteVLD, 679 WriteAdr], (instregex "^LDR[BHSDQ](post|pre)")>; 680def : InstRW<[WriteVLD], (instregex "^LDR[BHSDQ]ui")>; 681def : InstRW<[M4WriteLE, 682 ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>; 683def : InstRW<[WriteVLD, 684 ReadAdrBase], (instregex "^LDR[BHSD]roX")>; 685def : InstRW<[M4WriteLY, 686 ReadAdrBase], (instrs LDRQroX)>; 687def : InstRW<[WriteVLD, 688 M4WriteLH], (instregex "^LDN?P[SD]i")>; 689def : InstRW<[M4WriteLA, 690 M4WriteLH], (instregex "^LDN?PQi")>; 691def : InstRW<[M4WriteL5, 692 M4WriteLH, 693 WriteAdr], (instregex "^LDP[SD]post")>; 694def : InstRW<[M4WriteLB, 695 M4WriteLH, 696 WriteAdr], (instrs LDPQpost)>; 697def : InstRW<[M4WriteLB, 698 M4WriteLH, 699 WriteAdr], (instregex "^LDP[SD]pre")>; 700def : InstRW<[M4WriteLC, 701 M4WriteLH, 702 WriteAdr], (instrs LDPQpre)>; 703 704// FP store instructions. 705def : InstRW<[WriteVST], (instregex "^STUR[BHSDQ]i")>; 706def : InstRW<[WriteVST, 707 WriteAdr], (instregex "^STR[BHSDQ](post|pre)")>; 708def : InstRW<[WriteVST], (instregex "^STR[BHSDQ]ui")>; 709def : InstRW<[M4WriteVSTK, 710 ReadAdrBase], (instregex "^STR[BHSD]roW")>; 711def : InstRW<[M4WriteVSTK, 712 ReadAdrBase], (instrs STRQroW)>; 713def : InstRW<[WriteVST, 714 ReadAdrBase], (instregex "^STR[BHSD]roX")>; 715def : InstRW<[M4WriteVSTY, 716 ReadAdrBase], (instrs STRQroX)>; 717def : InstRW<[WriteVST], (instregex "^STN?P[SD]i")>; 718def : InstRW<[M4WriteVSTJ], (instregex "^STN?PQi")>; 719def : InstRW<[WriteVST, 720 WriteAdr], (instregex "^STP[SD](post|pre)")>; 721def : InstRW<[M4WriteVSTJ, 722 WriteAdr], (instregex "^STPQ(post|pre)")>; 723 724// ASIMD instructions. 725def : InstRW<[M4WriteNHAD1], (instregex "^[SU]ABDL?v")>; 726def : InstRW<[M4WriteNHAD3], (instregex "^[SU]ABAL?v")>; 727def : InstRW<[M4WriteNMSC1], (instregex "^ABSv")>; 728def : InstRW<[M4WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>; 729def : InstRW<[M4WriteNHAD3], (instregex "^[SU]?ADDL?Pv")>; 730def : InstRW<[M4WriteNHAD3], (instregex "^[SU]H(ADD|SUB)v")>; 731def : InstRW<[M4WriteNHAD3], (instregex "^[SU](ADD|SUB)[LW]v")>; 732def : InstRW<[M4WriteNHAD3], (instregex "^R?(ADD|SUB)HN2?v")>; 733def : InstRW<[M4WriteNHAD3], (instregex "^[SU]Q(ADD|SUB)v")>; 734def : InstRW<[M4WriteNHAD3], (instregex "^(SU|US)QADDv")>; 735def : InstRW<[M4WriteNHAD3], (instregex "^[SU]RHADDv")>; 736def : InstRW<[M4WriteNMSC1], (instregex "^SQ(ABS|NEG)v")>; 737def : InstRW<[M4WriteNHAD3], (instregex "^[SU]?ADDL?Vv")>; 738def : InstRW<[M4WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>; 739def : InstRW<[M4WriteNALU1], (instregex "^CMTSTv")>; 740def : InstRW<[M4WriteNALU1], (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>; 741def : InstRW<[M4WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>; 742def : InstRW<[M4WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>; 743def : InstRW<[M4WriteNHAD3], (instregex "^[SU](MIN|MAX)Vv")>; 744def : InstRW<[M4WriteNMUL3, 745 M4ReadNMULM1], (instregex "^ML[AS]v")>; 746def : InstRW<[M4WriteNMUL3, 747 M4ReadNMULM1], (instregex "^(SQR?D)?MULH?v")>; 748def : InstRW<[M4WriteNMUL3, 749 M4ReadNMULM1], (instregex "^SQRDML[AS]H")>; 750def : InstRW<[M4WriteNMUL3, 751 M4ReadNMULM1], (instregex "^(S|U|SQD)ML[AS]L(v1(i32|i64)|v2i32|v4i16|v8i8)")>; 752def : InstRW<[M4WriteNMUL3, 753 M4ReadNMULP2], (instregex "^(S|U|SQD)ML[AS]L(v4i32|v8i16|v16i8)")>; 754def : InstRW<[M4WriteNMUL3, 755 M4ReadNMULM1], (instregex "^(S|U|SQD)MULL(v1(i32|i64)|v2i32|v4i16|v8i8)")>; 756def : InstRW<[M4WriteNMUL3, 757 M4ReadNMULP2], (instregex "^(S|U|SQD)MULL(v4i32|v8i16|v16i8)")>; 758def : InstRW<[M4WriteNMUL3], (instregex "^[SU]DOT(lane)?v")>; 759def : InstRW<[M4WriteNHAD3], (instregex "^[SU]ADALPv")>; 760def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]R?SRA[dv]")>; 761def : InstRW<[M4WriteNSHT1], (instregex "^SHL[dv]")>; 762def : InstRW<[M4WriteNSHT1], (instregex "^S[LR]I[dv]")>; 763def : InstRW<[M4WriteNSHT1], (instregex "^[SU]SH[LR][dv]")>; 764def : InstRW<[M4WriteNSHT2], (instregex "^[SU]?SHLLv")>; 765def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?Q?R?SHRU?N[bhsv]")>; 766def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]RSH[LR][dv]")>; 767def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]QR?SHLU?[bhsdv]")>; 768 769// ASIMD FP instructions. 770def : InstRW<[M4WriteNSHF1H], (instregex "^FABSv.f16")>; 771def : InstRW<[M4WriteNSHF1], (instregex "^FABSv.f(32|64)")>; 772def : InstRW<[M4WriteFADD2H], (instregex "^F(ABD|ADD|SUB)v.f16")>; 773def : InstRW<[M4WriteFADD2], (instregex "^F(ABD|ADD|SUB)v.f(32|64)")>; 774def : InstRW<[M4WriteFADD2H], (instregex "^FADDPv.f16")>; 775def : InstRW<[M4WriteFADD2], (instregex "^FADDPv.f(32|64)")>; 776def : InstRW<[M4WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>; 777def : InstRW<[M4WriteFCVT2], (instregex "^FCVT(L|N|XN)v")>; 778def : InstRW<[M4WriteFCVT2A], (instregex "^FCVT[AMNPZ][SU]v")>; 779def : InstRW<[M4WriteFCVT2H], (instregex "^[SU]CVTFv.[fi]16")>; 780def : InstRW<[M4WriteFCVT2], (instregex "^[SU]CVTFv.[fi](32|64)")>; 781def : InstRW<[M4WriteFDIV7H], (instrs FDIVv4f16)>; 782def : InstRW<[M4WriteNEONVH], (instrs FDIVv8f16)>; 783def : InstRW<[M4WriteFDIV7], (instrs FDIVv2f32)>; 784def : InstRW<[M4WriteNEONV], (instrs FDIVv4f32)>; 785def : InstRW<[M4WriteNEONW], (instrs FDIVv2f64)>; 786def : InstRW<[M4WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?v")>; 787def : InstRW<[M4WriteNMSC2], (instregex "^F(MAX|MIN)(NM)?Pv")>; 788def : InstRW<[M4WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>; 789def : InstRW<[M4WriteFMAC2H], (instregex "^FMULX?v.[fi]16")>; 790def : InstRW<[M4WriteFMAC3], (instregex "^FMULX?v.[fi](32|64)")>; 791def : InstRW<[M4WriteFMAC4H, 792 M4ReadFMACM1], (instregex "^FML[AS]v.[fi]16")>; 793def : InstRW<[M4WriteFMAC4, 794 M4ReadFMACM1], (instregex "^FML[AS]v.[fi](32|64)")>; 795def : InstRW<[M4WriteNALU1H], (instregex "^FNEGv.f16")>; 796def : InstRW<[M4WriteNALU1], (instregex "^FNEGv.f(32|64)")>; 797def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>; 798def : InstRW<[M4WriteFSQR7H], (instrs FSQRTv4f16)>; 799def : InstRW<[M4WriteNEONXH], (instrs FSQRTv8f16)>; 800def : InstRW<[M4WriteFSQR8], (instrs FSQRTv2f32)>; 801def : InstRW<[M4WriteNEONX], (instrs FSQRTv4f32)>; 802def : InstRW<[M4WriteNEONY], (instrs FSQRTv2f64)>; 803 804// ASIMD miscellaneous instructions. 805def : InstRW<[M4WriteNALU1], (instregex "^RBITv")>; 806def : InstRW<[M4WriteNALU1], (instregex "^(BIF|BIT|BSL)v")>; 807def : InstRW<[M4WriteNALU1], (instregex "^CL[STZ]v")>; 808def : InstRW<[M4WriteNEONB], (instregex "^DUPv.+gpr")>; 809def : InstRW<[M4WriteNSHF1], (instregex "^CPY")>; 810def : InstRW<[M4WriteNSHF1], (instregex "^DUPv.+lane")>; 811def : InstRW<[M4WriteNSHF1], (instregex "^EXTv")>; 812def : InstRW<[M4WriteNSHT4A], (instregex "^XTNv")>; 813def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?QXTU?Nv")>; 814def : InstRW<[M4WriteNEONB], (instregex "^INSv.+gpr")>; 815def : InstRW<[M4WriteNSHF1], (instregex "^INSv.+lane")>; 816def : InstRW<[M4WriteMOVI], (instregex "^(MOV|MVN)I")>; 817def : InstRW<[M4WriteNALU1H], (instregex "^FMOVv.f16")>; 818def : InstRW<[M4WriteNALU1], (instregex "^FMOVv.f(32|64)")>; 819def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev[248]f16")>; 820def : InstRW<[M4WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev[248]f(32|64)")>; 821def : InstRW<[M4WriteFCVT3], (instregex "^U(RECP|RSQRT)Ev[24]i32")>; 822def : InstRW<[M4WriteFMAC4H], (instregex "^F(RECP|RSQRT)Sv.f16")>; 823def : InstRW<[M4WriteFMAC4], (instregex "^F(RECP|RSQRT)Sv.f(32|64)")>; 824def : InstRW<[M4WriteNSHF1], (instregex "^REV(16|32|64)v")>; 825def : InstRW<[M4WriteNSHFA], (instregex "^TB[LX]v(8|16)i8One")>; 826def : InstRW<[M4WriteNSHFB], (instregex "^TB[LX]v(8|16)i8Two")>; 827def : InstRW<[M4WriteNSHFC], (instregex "^TB[LX]v(8|16)i8Three")>; 828def : InstRW<[M4WriteNSHFD], (instregex "^TB[LX]v(8|16)i8Four")>; 829def : InstRW<[M4WriteNEONP], (instregex "^[SU]MOVv")>; 830def : InstRW<[M4WriteNSHF1], (instregex "^(TRN|UZP|ZIP)[12]v")>; 831 832// ASIMD load instructions. 833def : InstRW<[WriteVLD], (instregex "LD1Onev(8b|4h|2s|1d)$")>; 834def : InstRW<[WriteVLD, 835 M4WriteA1], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>; 836def : InstRW<[WriteVLD], (instregex "LD1Onev(16b|8h|4s|2d)$")>; 837def : InstRW<[WriteVLD, 838 M4WriteA1], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>; 839 840def : InstRW<[M4WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>; 841def : InstRW<[M4WriteVLDA, 842 M4WriteA1], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>; 843def : InstRW<[M4WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>; 844def : InstRW<[M4WriteVLDA, 845 M4WriteA1], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>; 846 847def : InstRW<[M4WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>; 848def : InstRW<[M4WriteVLDB, 849 M4WriteA1], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>; 850def : InstRW<[M4WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>; 851def : InstRW<[M4WriteVLDB, 852 M4WriteA1], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>; 853 854def : InstRW<[M4WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>; 855def : InstRW<[M4WriteVLDC, 856 M4WriteA1], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>; 857def : InstRW<[M4WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>; 858def : InstRW<[M4WriteVLDC, 859 M4WriteA1], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>; 860 861def : InstRW<[M4WriteVLDD], (instregex "LD1i(8|16|32|64)$")>; 862def : InstRW<[M4WriteVLDD, 863 M4WriteA1], (instregex "LD1i(8|16|32|64)_POST$")>; 864 865def : InstRW<[WriteVLD], (instregex "LD1Rv(8b|4h|2s|1d)$")>; 866def : InstRW<[WriteVLD, 867 M4WriteA1], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>; 868def : InstRW<[WriteVLD], (instregex "LD1Rv(16b|8h|4s|2d)$")>; 869def : InstRW<[WriteVLD, 870 M4WriteA1], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>; 871 872def : InstRW<[M4WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>; 873def : InstRW<[M4WriteVLDF, 874 M4WriteA1], (instregex "LD2Twov(8b|4h|2s)_POST$")>; 875def : InstRW<[M4WriteVLDF], (instregex "LD2Twov(16b|8h|4s|2d)$")>; 876def : InstRW<[M4WriteVLDF, 877 M4WriteA1], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>; 878 879def : InstRW<[M4WriteVLDG], (instregex "LD2i(8|16|32|64)$")>; 880def : InstRW<[M4WriteVLDG, 881 M4WriteA1], (instregex "LD2i(8|16|32|64)_POST$")>; 882 883def : InstRW<[M4WriteVLDA], (instregex "LD2Rv(8b|4h|2s|1d)$")>; 884def : InstRW<[M4WriteVLDA, 885 M4WriteA1], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>; 886def : InstRW<[M4WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>; 887def : InstRW<[M4WriteVLDA, 888 M4WriteA1], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>; 889 890def : InstRW<[M4WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>; 891def : InstRW<[M4WriteVLDI, 892 M4WriteA1], (instregex "LD3Threev(8b|4h|2s)_POST$")>; 893def : InstRW<[M4WriteVLDI], (instregex "LD3Threev(16b|8h|4s|2d)$")>; 894def : InstRW<[M4WriteVLDI, 895 M4WriteA1], (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>; 896 897def : InstRW<[M4WriteVLDJ], (instregex "LD3i(8|16|32)$")>; 898def : InstRW<[M4WriteVLDJ, 899 M4WriteA1], (instregex "LD3i(8|16|32)_POST$")>; 900def : InstRW<[M4WriteVLDL], (instregex "LD3i64$")>; 901def : InstRW<[M4WriteVLDL, 902 M4WriteA1], (instregex "LD3i64_POST$")>; 903 904def : InstRW<[M4WriteVLDB], (instregex "LD3Rv(8b|4h|2s|1d)$")>; 905def : InstRW<[M4WriteVLDB, 906 M4WriteA1], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>; 907def : InstRW<[M4WriteVLDB], (instregex "LD3Rv(16b|8h|4s|2d)$")>; 908def : InstRW<[M4WriteVLDB, 909 M4WriteA1], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>; 910 911def : InstRW<[M4WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>; 912def : InstRW<[M4WriteVLDN, 913 M4WriteA1], (instregex "LD4Fourv(8b|4h|2s)_POST$")>; 914def : InstRW<[M4WriteVLDN], (instregex "LD4Fourv(16b|8h|4s|2d)$")>; 915def : InstRW<[M4WriteVLDN, 916 M4WriteA1], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>; 917 918def : InstRW<[M4WriteVLDK], (instregex "LD4i(8|16|32)$")>; 919def : InstRW<[M4WriteVLDK, 920 M4WriteA1], (instregex "LD4i(8|16|32)_POST$")>; 921def : InstRW<[M4WriteVLDM], (instregex "LD4i64$")>; 922def : InstRW<[M4WriteVLDM, 923 M4WriteA1], (instregex "LD4i64_POST$")>; 924 925def : InstRW<[M4WriteVLDC], (instregex "LD4Rv(8b|4h|2s|1d)$")>; 926def : InstRW<[M4WriteVLDC, 927 M4WriteA1], (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>; 928def : InstRW<[M4WriteVLDC], (instregex "LD4Rv(16b|8h|4s|2d)$")>; 929def : InstRW<[M4WriteVLDC, 930 M4WriteA1], (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>; 931 932// ASIMD store instructions. 933def : InstRW<[WriteVST], (instregex "ST1Onev(8b|4h|2s|1d)$")>; 934def : InstRW<[WriteVST, 935 M4WriteA1], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>; 936def : InstRW<[WriteVST], (instregex "ST1Onev(16b|8h|4s|2d)$")>; 937def : InstRW<[WriteVST, 938 M4WriteA1], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>; 939 940def : InstRW<[M4WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>; 941def : InstRW<[M4WriteVSTA, 942 M4WriteA1], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>; 943def : InstRW<[M4WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>; 944def : InstRW<[M4WriteVSTA, 945 M4WriteA1], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>; 946 947def : InstRW<[M4WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>; 948def : InstRW<[M4WriteVSTB, 949 M4WriteA1], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>; 950def : InstRW<[M4WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>; 951def : InstRW<[M4WriteVSTB, 952 M4WriteA1], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>; 953 954def : InstRW<[M4WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; 955def : InstRW<[M4WriteVSTC, 956 M4WriteA1], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>; 957def : InstRW<[M4WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; 958def : InstRW<[M4WriteVSTC, 959 M4WriteA1], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>; 960 961def : InstRW<[WriteVST], (instregex "ST1i(8|16|32|64)$")>; 962def : InstRW<[WriteVST, 963 M4WriteA1], (instregex "ST1i(8|16|32|64)_POST$")>; 964 965def : InstRW<[M4WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>; 966def : InstRW<[M4WriteVSTD, 967 M4WriteA1], (instregex "ST2Twov(8b|4h|2s)_POST$")>; 968def : InstRW<[M4WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>; 969def : InstRW<[M4WriteVSTE, 970 M4WriteA1], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>; 971 972def : InstRW<[M4WriteVSTD], (instregex "ST2i(8|16|32|64)$")>; 973def : InstRW<[M4WriteVSTD, 974 M4WriteA1], (instregex "ST2i(8|16|32|64)_POST$")>; 975 976def : InstRW<[M4WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>; 977def : InstRW<[M4WriteVSTF, 978 M4WriteA1], (instregex "ST3Threev(8b|4h|2s)_POST$")>; 979def : InstRW<[M4WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>; 980def : InstRW<[M4WriteVSTG, 981 M4WriteA1], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>; 982 983def : InstRW<[M4WriteVSTE], (instregex "ST3i(8|16|32|64)$")>; 984def : InstRW<[M4WriteVSTE, 985 M4WriteA1], (instregex "ST3i(8|16|32|64)_POST$")>; 986 987def : InstRW<[M4WriteVSTL], (instregex "ST4Fourv(8b|4h|2s)$")>; 988def : InstRW<[M4WriteVSTL, 989 M4WriteA1], (instregex "ST4Fourv(8b|4h|2s)_POST$")>; 990def : InstRW<[M4WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>; 991def : InstRW<[M4WriteVSTI, 992 M4WriteA1], (instregex "ST4Fourv(16b|8h|4s|2d)_POST$")>; 993 994def : InstRW<[M4WriteVSTE], (instregex "ST4i(8|16|32|64)$")>; 995def : InstRW<[M4WriteVSTE, 996 M4WriteA1], (instregex "ST4i(8|16|32|64)_POST$")>; 997 998// Cryptography instructions. 999def : InstRW<[M4WriteNCRY1], (instregex "^AES[DE]")>; 1000def : InstRW<[M4WriteNCRY1, 1001 M4ReadAESM1], (instregex "^AESI?MC")>; 1002def : InstRW<[M4WriteNCRY1A], (instregex "^PMULv")>; 1003def : InstRW<[M4WriteNCRY1A], (instregex "^PMULLv(1|8)i")>; 1004def : InstRW<[M4WriteNCRY3A], (instregex "^PMULLv(2|16)i")>; 1005def : InstRW<[M4WriteNCRY1A], (instregex "^SHA1([CHMP]|SU[01])")>; 1006def : InstRW<[M4WriteNCRY1A], (instrs SHA256SU0rr)>; 1007def : InstRW<[M4WriteNCRY5A], (instrs SHA256SU1rrr)>; 1008def : InstRW<[M4WriteNCRY5A], (instrs SHA256H2rrr)>; 1009 1010// CRC instructions. 1011def : InstRW<[M4WriteE2], (instregex "^CRC32C?[BHWX]rr$")>; 1012 1013} // SchedModel = ExynosM4Model 1014