xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td (revision e6bfd18d21b225af6a0ed67ceeaf1293b7b9eba5)
1//=- AArch64SchedExynosM3.td - Samsung Exynos M3 Sched Defs --*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the machine model for the Samsung Exynos M3 to support
10// instruction scheduling and other instruction cost heuristics.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// The Exynos-M3 is an advanced superscalar microprocessor with a 6-wide
16// in-order stage for decode and dispatch and a wider issue stage.
17// The execution units and loads and stores are out-of-order.
18
19def ExynosM3Model : SchedMachineModel {
20  let IssueWidth            =   6; // Up to 6 uops per cycle.
21  let MicroOpBufferSize     = 228; // ROB size.
22  let LoopMicroOpBufferSize =  40; // Based on the instruction queue size.
23  let LoadLatency           =   4; // Optimistic load cases.
24  let MispredictPenalty     =  16; // Minimum branch misprediction penalty.
25  let CompleteModel         =   1; // Use the default model otherwise.
26
27  list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
28                                                    PAUnsupported.F,
29                                                    SMEUnsupported.F,
30                                                    [HasMTE]);
31}
32
33//===----------------------------------------------------------------------===//
34// Define each kind of processor resource and number available on the Exynos-M3,
35// which has 12 pipelines, each with its own queue with out-of-order dispatch.
36
37let SchedModel = ExynosM3Model in {
38
39def M3UnitA  : ProcResource<2>; // Simple integer
40def M3UnitC  : ProcResource<2>; // Simple and complex integer
41def M3UnitD  : ProcResource<1>; // Integer division (inside C0, serialized)
42def M3UnitB  : ProcResource<2>; // Branch
43def M3UnitL  : ProcResource<2>; // Load
44def M3UnitS  : ProcResource<1>; // Store
45def M3PipeF0 : ProcResource<1>; // FP #0
46let Super = M3PipeF0 in {
47  def M3UnitFMAC0 : ProcResource<1>; // FP multiplication
48  def M3UnitFADD0 : ProcResource<1>; // Simple FP
49  def M3UnitFCVT0 : ProcResource<1>; // FP conversion
50  def M3UnitFSQR  : ProcResource<2>; // FP square root (serialized)
51  def M3UnitNALU0 : ProcResource<1>; // Simple vector
52  def M3UnitNMSC  : ProcResource<1>; // FP and vector miscellanea
53  def M3UnitNSHT0 : ProcResource<1>; // Vector shifting
54  def M3UnitNSHF0 : ProcResource<1>; // Vector shuffling
55}
56def M3PipeF1 : ProcResource<1>; // FP #1
57let Super = M3PipeF1 in {
58  def M3UnitFMAC1 : ProcResource<1>; // FP multiplication
59  def M3UnitFADD1 : ProcResource<1>; // Simple FP
60  def M3UnitFDIV0 : ProcResource<2>; // FP division (serialized)
61  def M3UnitFCVT1 : ProcResource<1>; // FP conversion
62  def M3UnitFST0  : ProcResource<1>; // FP store
63  def M3UnitNALU1 : ProcResource<1>; // Simple vector
64  def M3UnitNCRY0 : ProcResource<1>; // Cryptographic
65  def M3UnitNMUL  : ProcResource<1>; // Vector multiplication
66  def M3UnitNSHT1 : ProcResource<1>; // Vector shifting
67  def M3UnitNSHF1 : ProcResource<1>; // Vector shuffling
68}
69def M3PipeF2 : ProcResource<1>; // FP #2
70let Super = M3PipeF2 in {
71  def M3UnitFMAC2 : ProcResource<1>; // FP multiplication
72  def M3UnitFADD2 : ProcResource<1>; // Simple FP
73  def M3UnitFDIV1 : ProcResource<2>; // FP division (serialized)
74  def M3UnitFST1  : ProcResource<1>; // FP store
75  def M3UnitNALU2 : ProcResource<1>; // Simple vector
76  def M3UnitNCRY1 : ProcResource<1>; // Cryptographic
77  def M3UnitNSHT2 : ProcResource<1>; // Vector shifting
78  def M3UnitNSHF2 : ProcResource<1>; // Vector shuffling
79}
80
81
82def M3UnitALU  : ProcResGroup<[M3UnitA,
83                               M3UnitC]>;
84def M3UnitFMAC : ProcResGroup<[M3UnitFMAC0,
85                               M3UnitFMAC1,
86                               M3UnitFMAC2]>;
87def M3UnitFADD : ProcResGroup<[M3UnitFADD0,
88                               M3UnitFADD1,
89                               M3UnitFADD2]>;
90def M3UnitFDIV : ProcResGroup<[M3UnitFDIV0,
91                               M3UnitFDIV1]>;
92def M3UnitFCVT : ProcResGroup<[M3UnitFCVT0,
93                               M3UnitFCVT1]>;
94def M3UnitFST  : ProcResGroup<[M3UnitFST0,
95                               M3UnitFST1]>;
96def M3UnitNALU : ProcResGroup<[M3UnitNALU0,
97                               M3UnitNALU1,
98                               M3UnitNALU2]>;
99def M3UnitNCRY : ProcResGroup<[M3UnitNCRY0,
100                               M3UnitNCRY1]>;
101def M3UnitNSHT : ProcResGroup<[M3UnitNSHT0,
102                               M3UnitNSHT1,
103                               M3UnitNSHT2]>;
104def M3UnitNSHF : ProcResGroup<[M3UnitNSHF0,
105                               M3UnitNSHF1,
106                               M3UnitNSHF2]>;
107
108//===----------------------------------------------------------------------===//
109// Coarse scheduling model.
110
111def M3WriteZ0 : SchedWriteRes<[]> { let Latency = 0;
112                                    let NumMicroOps = 1; }
113def M3WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
114                                    let NumMicroOps = 0; }
115
116def M3WriteA1 : SchedWriteRes<[M3UnitALU]> { let Latency = 1; }
117def M3WriteAA : SchedWriteRes<[M3UnitALU]> { let Latency = 2;
118                                             let ResourceCycles = [2]; }
119def M3WriteAB : SchedWriteRes<[M3UnitALU,
120                               M3UnitC]>   { let Latency = 1;
121                                             let NumMicroOps = 2; }
122def M3WriteAC : SchedWriteRes<[M3UnitALU,
123                               M3UnitALU,
124                               M3UnitC]>   { let Latency = 2;
125                                             let NumMicroOps = 3; }
126def M3WriteAD : SchedWriteRes<[M3UnitALU,
127                               M3UnitC]>   { let Latency = 2;
128                                             let NumMicroOps = 2; }
129def M3WriteC1 : SchedWriteRes<[M3UnitC]>   { let Latency = 1; }
130def M3WriteC2 : SchedWriteRes<[M3UnitC]>   { let Latency = 2; }
131def M3WriteAU : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M3WriteZ0]>,
132                                   SchedVar<ExynosArithPred, [M3WriteA1]>,
133                                   SchedVar<ExynosLogicPred, [M3WriteA1]>,
134                                   SchedVar<NoSchedPred,     [M3WriteAA]>]>;
135def M3WriteAV : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M3WriteZ0]>,
136                                   SchedVar<ExynosArithPred, [M3WriteA1]>,
137                                   SchedVar<NoSchedPred,     [M3WriteAA]>]>;
138def M3WriteAW : SchedWriteVariant<[SchedVar<IsZeroIdiomPred, [M3WriteZ0]>,
139                                   SchedVar<ExynosLogicPred, [M3WriteA1]>,
140                                   SchedVar<NoSchedPred,     [M3WriteAA]>]>;
141def M3WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M3WriteA1]>,
142                                   SchedVar<ExynosLogicPred, [M3WriteA1]>,
143                                   SchedVar<NoSchedPred,     [M3WriteAA]>]>;
144def M3WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M3WriteA1]>,
145                                   SchedVar<NoSchedPred,              [M3WriteAA]>]>;
146
147def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; }
148def M3WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M3WriteAC]>,
149                                   SchedVar<NoSchedPred,            [M3WriteAB]>]>;
150
151def M3WriteL4 : SchedWriteRes<[M3UnitL]> { let Latency = 4; }
152def M3WriteL5 : SchedWriteRes<[M3UnitL]> { let Latency = 5; }
153def M3WriteLA : SchedWriteRes<[M3UnitL,
154                               M3UnitL]> { let Latency = 5;
155                                           let NumMicroOps = 1; }
156def M3WriteLB : SchedWriteRes<[M3UnitA,
157                               M3UnitL]> { let Latency = 5;
158                                           let NumMicroOps = 2; }
159def M3WriteLC : SchedWriteRes<[M3UnitA,
160                               M3UnitL,
161                               M3UnitL]> { let Latency = 5;
162                                           let NumMicroOps = 2; }
163def M3WriteLD : SchedWriteRes<[M3UnitA,
164                               M3UnitL]> { let Latency = 4;
165                                           let NumMicroOps = 2; }
166def M3WriteLE : SchedWriteRes<[M3UnitA,
167                               M3UnitL]> { let Latency = 6;
168                                           let NumMicroOps = 2; }
169def M3WriteLH : SchedWriteRes<[]>        { let Latency = 5;
170                                           let NumMicroOps = 0; }
171def M3WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteL5]>,
172                                   SchedVar<NoSchedPred,         [M3WriteL4]>]>;
173def M3WriteLY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteLE]>,
174                                   SchedVar<NoSchedPred,         [M3WriteL5]>]>;
175
176def M3WriteS1 : SchedWriteRes<[M3UnitS]>   { let Latency = 1; }
177def M3WriteSA : SchedWriteRes<[M3UnitA,
178                               M3UnitS,
179                               M3UnitFST]> { let Latency = 3;
180                                             let NumMicroOps = 2; }
181def M3WriteSB : SchedWriteRes<[M3UnitA,
182                               M3UnitS]>   { let Latency = 2;
183                                             let NumMicroOps = 2; }
184def M3WriteSC : SchedWriteRes<[M3UnitA,
185                               M3UnitS,
186                               M3UnitFST]> { let Latency = 1;
187                                             let NumMicroOps = 2; }
188def M3WriteSY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteSA]>,
189                                   SchedVar<NoSchedPred,         [WriteVST]>]>;
190
191def M3ReadAdrBase : SchedReadVariant<[SchedVar<ExynosScaledIdxPred, [ReadDefault]>,
192                                      SchedVar<NoSchedPred,         [ReadDefault]>]>;
193
194// Branch instructions.
195def : SchedAlias<WriteBr, M3WriteZ0>;
196def : SchedAlias<WriteBrReg, M3WriteC1>;
197
198// Arithmetic and logical integer instructions.
199def : SchedAlias<WriteI,     M3WriteA1>;
200def : SchedAlias<WriteISReg, M3WriteA1>;
201def : SchedAlias<WriteIEReg, M3WriteA1>;
202def : SchedAlias<WriteIS,    M3WriteA1>;
203
204// Move instructions.
205def : SchedAlias<WriteImm, M3WriteA1>;
206
207// Divide and multiply instructions.
208def : WriteRes<WriteID32, [M3UnitC,
209                           M3UnitD]>  { let Latency = 12;
210                                        let ResourceCycles = [1, 12]; }
211def : WriteRes<WriteID64, [M3UnitC,
212                           M3UnitD]>  { let Latency = 21;
213                                        let ResourceCycles = [1, 21]; }
214def : WriteRes<WriteIM32, [M3UnitC]>  { let Latency = 3; }
215def : WriteRes<WriteIM64, [M3UnitC]>  { let Latency = 4;
216                                        let ResourceCycles = [2]; }
217
218// Miscellaneous instructions.
219def : SchedAlias<WriteExtr, M3WriteAY>;
220
221// Addressing modes.
222def : SchedAlias<WriteAdr,    M3WriteZ1>;
223def : SchedAlias<ReadAdrBase, M3ReadAdrBase>;
224
225// Load instructions.
226def : SchedAlias<WriteLD, M3WriteL4>;
227def : WriteRes<WriteLDHi, []> { let Latency = 4;
228                                let NumMicroOps = 0; }
229def : SchedAlias<WriteLDIdx, M3WriteLB>;
230
231// Store instructions.
232def : SchedAlias<WriteST,    M3WriteS1>;
233def : SchedAlias<WriteSTP,   M3WriteS1>;
234def : SchedAlias<WriteSTX,   M3WriteS1>;
235def : SchedAlias<WriteSTIdx, M3WriteSB>;
236
237// FP data instructions.
238def : WriteRes<WriteF,    [M3UnitFADD]>  { let Latency = 2; }
239def : WriteRes<WriteFCmp, [M3UnitNMSC]>  { let Latency = 2; }
240def : WriteRes<WriteFDiv, [M3UnitFDIV]>  { let Latency = 12;
241                                           let ResourceCycles = [12]; }
242def : WriteRes<WriteFMul, [M3UnitFMAC]>  { let Latency = 4; }
243
244// FP miscellaneous instructions.
245def : WriteRes<WriteFCvt,  [M3UnitFCVT]> { let Latency = 3; }
246def : WriteRes<WriteFImm,  [M3UnitNALU]> { let Latency = 1; }
247def : WriteRes<WriteFCopy, [M3UnitNALU]> { let Latency = 1; }
248
249// FP load instructions.
250def : SchedAlias<WriteVLD, M3WriteL5>;
251
252// FP store instructions.
253def : WriteRes<WriteVST, [M3UnitS,
254                          M3UnitFST]> { let Latency = 1;
255                                        let NumMicroOps = 1; }
256
257// ASIMD FP instructions.
258def : WriteRes<WriteVd, [M3UnitNALU]> { let Latency = 3; }
259def : WriteRes<WriteVq, [M3UnitNALU]> { let Latency = 3; }
260
261// Other miscellaneous instructions.
262def : WriteRes<WriteAtomic,  []> { let Unsupported = 1; }
263def : WriteRes<WriteBarrier, []> { let Latency = 1; }
264def : WriteRes<WriteHint,    []> { let Latency = 1; }
265def : WriteRes<WriteSys,     []> { let Latency = 1; }
266
267//===----------------------------------------------------------------------===//
268// Generic fast forwarding.
269
270// TODO: Add FP register forwarding rules.
271
272def : ReadAdvance<ReadI,       0>;
273def : ReadAdvance<ReadISReg,   0>;
274def : ReadAdvance<ReadIEReg,   0>;
275def : ReadAdvance<ReadIM,      0>;
276// TODO: The forwarding for 32 bits actually saves 2 cycles.
277def : ReadAdvance<ReadIMA,     3, [WriteIM32, WriteIM64]>;
278def : ReadAdvance<ReadID,      0>;
279def : ReadAdvance<ReadExtrHi,  0>;
280def : ReadAdvance<ReadAdrBase, 0>;
281def : ReadAdvance<ReadVLD,     0>;
282def : ReadAdvance<ReadST,      0>;
283
284//===----------------------------------------------------------------------===//
285// Finer scheduling model.
286
287def M3WriteNEONA   : SchedWriteRes<[M3UnitNSHF,
288                                    M3UnitFADD]>  { let Latency = 3;
289                                                    let NumMicroOps = 2; }
290def M3WriteNEONB   : SchedWriteRes<[M3UnitNALU,
291                                    M3UnitFST]>   { let Latency = 10;
292                                                    let NumMicroOps = 2; }
293def M3WriteNEOND   : SchedWriteRes<[M3UnitNSHF,
294                                    M3UnitFST]>   { let Latency = 6;
295                                                    let NumMicroOps = 2; }
296def M3WriteNEONH   : SchedWriteRes<[M3UnitNALU,
297                                    M3UnitS]>     { let Latency = 5;
298                                                    let NumMicroOps = 2; }
299def M3WriteNEONI   : SchedWriteRes<[M3UnitNSHF,
300                                    M3UnitS]>     { let Latency = 5;
301                                                    let NumMicroOps = 2; }
302def M3WriteNEONV   : SchedWriteRes<[M3UnitFDIV0,
303                                    M3UnitFDIV1]>  { let Latency = 7;
304                                                     let NumMicroOps = 2;
305                                                     let ResourceCycles = [8, 8]; }
306def M3WriteNEONW   : SchedWriteRes<[M3UnitFDIV0,
307                                    M3UnitFDIV1]>  { let Latency = 12;
308                                                     let NumMicroOps = 2;
309                                                     let ResourceCycles = [13, 13]; }
310def M3WriteNEONX   : SchedWriteRes<[M3UnitFSQR,
311                                    M3UnitFSQR]>  { let Latency = 18;
312                                                    let NumMicroOps = 2;
313                                                    let ResourceCycles = [19, 19]; }
314def M3WriteNEONY   : SchedWriteRes<[M3UnitFSQR,
315                                    M3UnitFSQR]>  { let Latency = 25;
316                                                    let NumMicroOps = 2;
317                                                    let ResourceCycles = [26, 26]; }
318def M3WriteNEONZ   : SchedWriteRes<[M3UnitNMSC,
319                                    M3UnitNMSC]>  { let Latency = 5;
320                                                    let NumMicroOps = 2; }
321def M3WriteFADD2   : SchedWriteRes<[M3UnitFADD]>  { let Latency = 2; }
322def M3WriteFCVT2   : SchedWriteRes<[M3UnitFCVT]>  { let Latency = 2; }
323def M3WriteFCVT3   : SchedWriteRes<[M3UnitFCVT]>  { let Latency = 3; }
324def M3WriteFCVT3A  : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 3; }
325def M3WriteFCVT4A  : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 4; }
326def M3WriteFCVT4   : SchedWriteRes<[M3UnitFCVT]>  { let Latency = 4; }
327def M3WriteFDIV10  : SchedWriteRes<[M3UnitFDIV]>  { let Latency = 7;
328                                                    let ResourceCycles = [8]; }
329def M3WriteFDIV12  : SchedWriteRes<[M3UnitFDIV]>  { let Latency = 12;
330                                                    let ResourceCycles = [13]; }
331def M3WriteFMAC3   : SchedWriteRes<[M3UnitFMAC]>  { let Latency = 3; }
332def M3WriteFMAC4   : SchedWriteRes<[M3UnitFMAC]>  { let Latency = 4; }
333def M3WriteFMAC5   : SchedWriteRes<[M3UnitFMAC]>  { let Latency = 5; }
334def M3WriteFSQR17  : SchedWriteRes<[M3UnitFSQR]>  { let Latency = 18;
335                                                    let ResourceCycles = [19]; }
336def M3WriteFSQR25  : SchedWriteRes<[M3UnitFSQR]>  { let Latency = 25;
337                                                    let ResourceCycles = [26]; }
338def M3WriteNALU1   : SchedWriteRes<[M3UnitNALU]>  { let Latency = 1; }
339def M3WriteNCRY1A  : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 1; }
340def M3WriteNCRY3A  : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 3; }
341def M3WriteNCRY5A  : SchedWriteRes<[M3UnitNCRY]>  { let Latency = 5; }
342def M3WriteNMSC1   : SchedWriteRes<[M3UnitNMSC]>  { let Latency = 1; }
343def M3WriteNMSC2   : SchedWriteRes<[M3UnitNMSC]>  { let Latency = 2; }
344def M3WriteNMSC3   : SchedWriteRes<[M3UnitNMSC]>  { let Latency = 3; }
345def M3WriteNMUL3   : SchedWriteRes<[M3UnitNMUL]>  { let Latency = 3; }
346def M3WriteNSHF1   : SchedWriteRes<[M3UnitNSHF]>  { let Latency = 1; }
347def M3WriteNSHF3   : SchedWriteRes<[M3UnitNSHF]>  { let Latency = 3; }
348def M3WriteNSHT1   : SchedWriteRes<[M3UnitNSHT]>  { let Latency = 1; }
349def M3WriteNSHT2   : SchedWriteRes<[M3UnitNSHT]>  { let Latency = 2; }
350def M3WriteNSHT3   : SchedWriteRes<[M3UnitNSHT]>  { let Latency = 3; }
351def M3WriteVLDA    : SchedWriteRes<[M3UnitL,
352                                    M3UnitL]>     { let Latency = 5;
353                                                    let NumMicroOps = 2; }
354def M3WriteVLDB    : SchedWriteRes<[M3UnitL,
355                                    M3UnitL,
356                                    M3UnitL]>     { let Latency = 6;
357                                                    let NumMicroOps = 3; }
358def M3WriteVLDC    : SchedWriteRes<[M3UnitL,
359                                    M3UnitL,
360                                    M3UnitL,
361                                    M3UnitL]>     { let Latency = 6;
362                                                    let NumMicroOps = 4; }
363def M3WriteVLDD    : SchedWriteRes<[M3UnitL,
364                                    M3UnitNALU]>  { let Latency = 7;
365                                                    let NumMicroOps = 2;
366                                                    let ResourceCycles = [2, 1]; }
367def M3WriteVLDE    : SchedWriteRes<[M3UnitL,
368                                    M3UnitNALU]>  { let Latency = 6;
369                                                    let NumMicroOps = 2;
370                                                    let ResourceCycles = [2, 1]; }
371def M3WriteVLDF    : SchedWriteRes<[M3UnitL,
372                                    M3UnitL]>     { let Latency = 10;
373                                                    let NumMicroOps = 2;
374                                                    let ResourceCycles = [5, 5]; }
375def M3WriteVLDG    : SchedWriteRes<[M3UnitL,
376                                    M3UnitNALU,
377                                    M3UnitNALU]>  { let Latency = 7;
378                                                    let NumMicroOps = 3;
379                                                    let ResourceCycles = [2, 1, 1]; }
380def M3WriteVLDH    : SchedWriteRes<[M3UnitL,
381                                    M3UnitNALU,
382                                    M3UnitNALU]>  { let Latency = 6;
383                                                    let NumMicroOps = 3;
384                                                    let ResourceCycles = [2, 1, 1]; }
385def M3WriteVLDI    : SchedWriteRes<[M3UnitL,
386                                    M3UnitL,
387                                    M3UnitL]>     { let Latency = 12;
388                                                    let NumMicroOps = 3;
389                                                    let ResourceCycles = [6, 6, 6]; }
390def M3WriteVLDJ    : SchedWriteRes<[M3UnitL,
391                                    M3UnitNALU,
392                                    M3UnitNALU,
393                                    M3UnitNALU]>  { let Latency = 7;
394                                                    let NumMicroOps = 4;
395                                                    let ResourceCycles = [2, 1, 1, 1]; }
396def M3WriteVLDK    : SchedWriteRes<[M3UnitL,
397                                    M3UnitNALU,
398                                    M3UnitNALU,
399                                    M3UnitNALU,
400                                    M3UnitNALU]>  { let Latency = 9;
401                                                    let NumMicroOps = 5;
402                                                    let ResourceCycles = [4, 1, 1, 1, 1]; }
403def M3WriteVLDL    : SchedWriteRes<[M3UnitL,
404                                    M3UnitNALU,
405                                    M3UnitNALU,
406                                    M3UnitL,
407                                    M3UnitNALU]>  { let Latency = 6;
408                                                    let NumMicroOps = 5;
409                                                    let ResourceCycles = [6, 1, 1, 6, 1]; }
410def M3WriteVLDM    : SchedWriteRes<[M3UnitL,
411                                    M3UnitNALU,
412                                    M3UnitNALU,
413                                    M3UnitL,
414                                    M3UnitNALU,
415                                    M3UnitNALU]>  { let Latency = 7;
416                                                    let NumMicroOps = 6;
417                                                    let ResourceCycles = [6, 1, 1, 6, 1, 1]; }
418def M3WriteVLDN    : SchedWriteRes<[M3UnitL,
419                                    M3UnitL,
420                                    M3UnitL,
421                                    M3UnitL]>     { let Latency = 14;
422                                                    let NumMicroOps = 4;
423                                                    let ResourceCycles = [6, 6, 6, 6]; }
424def M3WriteVSTA    : WriteSequence<[WriteVST], 2>;
425def M3WriteVSTB    : WriteSequence<[WriteVST], 3>;
426def M3WriteVSTC    : WriteSequence<[WriteVST], 4>;
427def M3WriteVSTD    : SchedWriteRes<[M3UnitS,
428                                    M3UnitFST,
429                                    M3UnitS,
430                                    M3UnitFST]>   { let Latency = 7;
431                                                    let NumMicroOps = 4;
432                                                    let ResourceCycles = [1, 3, 1, 3]; }
433def M3WriteVSTE    : SchedWriteRes<[M3UnitS,
434                                    M3UnitFST,
435                                    M3UnitS,
436                                    M3UnitFST,
437                                    M3UnitS,
438                                    M3UnitFST]>   { let Latency = 8;
439                                                    let NumMicroOps = 6;
440                                                    let ResourceCycles = [1, 3, 1, 3, 1, 3]; }
441def M3WriteVSTF    : SchedWriteRes<[M3UnitNALU,
442                                    M3UnitFST,
443                                    M3UnitFST,
444                                    M3UnitS,
445                                    M3UnitFST,
446                                    M3UnitS,
447                                    M3UnitFST]>   { let Latency = 15;
448                                                    let NumMicroOps = 7;
449                                                    let ResourceCycles = [1, 3, 3, 1, 3, 1, 3]; }
450def M3WriteVSTG    : SchedWriteRes<[M3UnitNALU,
451                                    M3UnitFST,
452                                    M3UnitFST,
453                                    M3UnitS,
454                                    M3UnitFST,
455                                    M3UnitS,
456                                    M3UnitFST,
457                                    M3UnitS,
458                                    M3UnitFST]>   { let Latency = 16;
459                                                    let NumMicroOps = 9;
460                                                    let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
461def M3WriteVSTH    : SchedWriteRes<[M3UnitNALU,
462                                    M3UnitFST,
463                                    M3UnitFST,
464                                    M3UnitS,
465                                    M3UnitFST]>   { let Latency = 14;
466                                                    let NumMicroOps = 5;
467                                                    let ResourceCycles = [1, 3, 3, 1, 3]; }
468def M3WriteVSTI    : SchedWriteRes<[M3UnitNALU,
469                                    M3UnitFST,
470                                    M3UnitFST,
471                                    M3UnitS,
472                                    M3UnitFST,
473                                    M3UnitS,
474                                    M3UnitFST,
475                                    M3UnitS,
476                                    M3UnitFST]>   { let Latency = 17;
477                                                    let NumMicroOps = 9;
478                                                    let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
479
480// Special cases.
481def M3WriteAES     : SchedWriteRes<[M3UnitNCRY]>  { let Latency = 1; }
482def M3WriteCOPY    : SchedWriteVariant<[SchedVar<ExynosFPPred, [M3WriteNALU1]>,
483                                        SchedVar<NoSchedPred,  [M3WriteZ0]>]>;
484def M3WriteMOVI    : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M3WriteZ0]>,
485                                        SchedVar<NoSchedPred,       [M3WriteNALU1]>]>;
486
487// Fast forwarding.
488def M3ReadAES      : SchedReadAdvance<1, [M3WriteAES]>;
489def M3ReadFMAC     : SchedReadAdvance<1, [M3WriteFMAC4,
490                                          M3WriteFMAC5]>;
491def M3ReadNMUL     : SchedReadAdvance<1, [M3WriteNMUL3]>;
492
493// Branch instructions
494def : InstRW<[M3WriteB1], (instrs Bcc)>;
495def : InstRW<[M3WriteA1], (instrs BL)>;
496def : InstRW<[M3WriteBX], (instrs BLR)>;
497def : InstRW<[M3WriteC1], (instregex "^CBN?Z[WX]")>;
498def : InstRW<[M3WriteAD], (instregex "^TBN?Z[WX]")>;
499
500// Arithmetic and logical integer instructions.
501def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>;
502def : InstRW<[M3WriteAU], (instrs ORRWrs, ORRXrs)>;
503def : InstRW<[M3WriteAX], (instregex "^(ADD|SUB)S?[WX]rx(64)?$")>;
504def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>;
505def : InstRW<[M3WriteAV], (instrs ADDWri, ADDXri)>;
506def : InstRW<[M3WriteAW], (instrs ORRWri, ORRXri)>;
507
508// Move instructions.
509def : InstRW<[M3WriteCOPY], (instrs COPY)>;
510def : InstRW<[M3WriteZ0],   (instrs ADR, ADRP)>;
511def : InstRW<[M3WriteZ0],   (instregex "^MOV[NZ][WX]i")>;
512
513// Divide and multiply instructions.
514
515// Miscellaneous instructions.
516
517// Load instructions.
518def : InstRW<[M3WriteLD,
519              WriteLDHi,
520              WriteAdr],    (instregex "^LDP(SW|W|X)(post|pre)")>;
521def : InstRW<[M3WriteLB,
522              ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
523def : InstRW<[M3WriteLX,
524              ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
525def : InstRW<[M3WriteLB,
526              ReadAdrBase], (instrs PRFMroW)>;
527def : InstRW<[M3WriteLX,
528              ReadAdrBase], (instrs PRFMroX)>;
529
530// Store instructions.
531def : InstRW<[M3WriteSB,
532              ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>;
533def : InstRW<[WriteST,
534              ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>;
535
536// FP data instructions.
537def : InstRW<[M3WriteNSHF1],  (instregex "^FABS[DS]r")>;
538def : InstRW<[M3WriteFADD2],  (instregex "^F(ADD|SUB)[DS]rr")>;
539def : InstRW<[M3WriteFDIV10], (instrs FDIVSrr)>;
540def : InstRW<[M3WriteFDIV12], (instrs FDIVDrr)>;
541def : InstRW<[M3WriteNMSC1],  (instregex "^F(MAX|MIN).+rr")>;
542def : InstRW<[M3WriteFMAC3],  (instregex "^FN?MUL[DS]rr")>;
543def : InstRW<[M3WriteFMAC4,
544              M3ReadFMAC],    (instregex "^FN?M(ADD|SUB)[DS]rrr")>;
545def : InstRW<[M3WriteNALU1],  (instregex "^FNEG[DS]r")>;
546def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT.+r")>;
547def : InstRW<[M3WriteNEONH],  (instregex "^FCSEL[DS]rrr")>;
548def : InstRW<[M3WriteFSQR17], (instrs FSQRTSr)>;
549def : InstRW<[M3WriteFSQR25], (instrs FSQRTDr)>;
550
551// FP miscellaneous instructions.
552def : InstRW<[M3WriteFCVT3],  (instregex "^FCVT[DHS][DHS]r")>;
553def : InstRW<[M3WriteFCVT4A], (instregex "^[SU]CVTF[SU][XW][DHS]ri")>;
554def : InstRW<[M3WriteFCVT3A], (instregex "^FCVT[AMNPZ][SU]U[XW][DHS]r")>;
555def : InstRW<[M3WriteFCVT3A], (instregex "^FCVTZ[SU][dhs]")>;
556def : InstRW<[M3WriteNALU1],  (instregex "^FMOV[DS][ir]")>;
557def : InstRW<[M3WriteFCVT4],  (instregex "^[FU](RECP|RSQRT)Ev1")>;
558def : InstRW<[M3WriteNMSC1],  (instregex "^FRECPXv1")>;
559def : InstRW<[M3WriteFMAC4,
560              M3ReadFMAC],    (instregex "^F(RECP|RSQRT)S(16|32|64)")>;
561def : InstRW<[M3WriteNALU1],  (instregex "^FMOV[WX][DS]r")>;
562def : InstRW<[M3WriteNALU1],  (instregex "^FMOV[DS][WX]r")>;
563def : InstRW<[M3WriteNEONI],  (instregex "^FMOV(DX|XD)Highr")>;
564
565// FP load instructions.
566def : InstRW<[WriteVLD],    (instregex "^LDR[DSQ]l")>;
567def : InstRW<[WriteVLD],    (instregex "^LDUR[BDHSQ]i")>;
568def : InstRW<[WriteVLD,
569              WriteAdr],    (instregex "^LDR[BDHSQ](post|pre)")>;
570def : InstRW<[WriteVLD],    (instregex "^LDR[BDHSQ]ui")>;
571def : InstRW<[M3WriteLE,
572              ReadAdrBase], (instregex "^LDR[BDHS]roW")>;
573def : InstRW<[WriteVLD,
574              ReadAdrBase], (instregex "^LDR[BDHS]roX")>;
575def : InstRW<[M3WriteLY,
576              ReadAdrBase], (instregex "^LDRQro[WX]")>;
577def : InstRW<[WriteVLD,
578              M3WriteLH],   (instregex "^LDN?P[DS]i")>;
579def : InstRW<[M3WriteLA,
580              M3WriteLH],   (instregex "^LDN?PQi")>;
581def : InstRW<[M3WriteLB,
582              M3WriteLH,
583              WriteAdr],    (instregex "^LDP[DS](post|pre)")>;
584def : InstRW<[M3WriteLC,
585              M3WriteLH,
586              WriteAdr],    (instregex "^LDPQ(post|pre)")>;
587
588// FP store instructions.
589def : InstRW<[WriteVST],    (instregex "^STUR[BDHSQ]i")>;
590def : InstRW<[WriteVST,
591              WriteAdr],    (instregex "^STR[BDHSQ](post|pre)")>;
592def : InstRW<[WriteVST],    (instregex "^STR[BDHSQ]ui")>;
593def : InstRW<[M3WriteSA,
594              ReadAdrBase], (instregex "^STR[BDHS]roW")>;
595def : InstRW<[M3WriteSA,
596              ReadAdrBase], (instregex "^STRQroW")>;
597def : InstRW<[WriteVST,
598              ReadAdrBase], (instregex "^STR[BDHS]roX")>;
599def : InstRW<[M3WriteSY,
600              ReadAdrBase], (instregex "^STRQroX")>;
601def : InstRW<[WriteVST],    (instregex "^STN?P[DSQ]i")>;
602def : InstRW<[WriteVST,
603              WriteAdr],    (instregex "^STP[DS](post|pre)")>;
604def : InstRW<[M3WriteSC,
605              WriteAdr],    (instregex "^STPQ(post|pre)")>;
606
607// ASIMD instructions.
608def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ABAL?v")>;
609def : InstRW<[M3WriteNMSC1], (instregex "^[SU]ABDL?v")>;
610def : InstRW<[M3WriteNMSC1], (instregex "^((SQ)?ABS|SQNEG)v")>;
611def : InstRW<[M3WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>;
612def : InstRW<[M3WriteNMSC3], (instregex "^[SU]?ADDL?Pv")>;
613def : InstRW<[M3WriteNMSC3], (instregex "^[SU]H(ADD|SUB)v")>;
614def : InstRW<[M3WriteNMSC3], (instregex "^[SU](ADD|SUB)[LW]V?v")>;
615def : InstRW<[M3WriteNMSC3], (instregex "^R?(ADD|SUB)HN2?v")>;
616def : InstRW<[M3WriteNMSC3], (instregex "^[SU]Q(ADD|SUB)v")>;
617def : InstRW<[M3WriteNMSC3], (instregex "^(SU|US)QADDv")>;
618def : InstRW<[M3WriteNMSC3], (instregex "^[SU]RHADDv")>;
619def : InstRW<[M3WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>;
620def : InstRW<[M3WriteNALU1], (instregex "^CMTSTv")>;
621def : InstRW<[M3WriteNALU1], (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>;
622def : InstRW<[M3WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>;
623def : InstRW<[M3WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>;
624def : InstRW<[M3WriteNMSC3], (instregex "^[SU](MIN|MAX)Vv")>;
625def : InstRW<[M3WriteNMUL3], (instregex "^(MUL|SQR?DMULH)v")>;
626def : InstRW<[M3WriteNMUL3,
627              M3ReadNMUL],   (instregex "^ML[AS]v")>;
628def : InstRW<[M3WriteNMUL3], (instregex "^[SU]ML[AS]Lv")>;
629def : InstRW<[M3WriteNMUL3], (instregex "^SQDML[AS]L")>;
630def : InstRW<[M3WriteNMUL3], (instregex "^(S|U|SQD)MULLv")>;
631def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ADALPv")>;
632def : InstRW<[M3WriteNSHT3], (instregex "^[SU]R?SRAv")>;
633def : InstRW<[M3WriteNSHT1], (instregex "^SHL[dv]")>;
634def : InstRW<[M3WriteNSHT1], (instregex "^[SU]SH[LR][dv]")>;
635def : InstRW<[M3WriteNSHT1], (instregex "^S[RS]I[dv]")>;
636def : InstRW<[M3WriteNSHT2], (instregex "^[SU]?SHLLv")>;
637def : InstRW<[M3WriteNSHT3], (instregex "^(([SU]Q)?R)?SHRU?N[bhsv]")>;
638def : InstRW<[M3WriteNSHT3], (instregex "^[SU]RSH[LR][dv]")>;
639def : InstRW<[M3WriteNSHT3], (instregex "^[SU]QR?SHLU?[bdhsv]")>;
640
641// ASIMD FP instructions.
642def : InstRW<[M3WriteNSHF1],  (instregex "^FABSv")>;
643def : InstRW<[M3WriteFADD2],  (instregex "^F(ABD|ADD|SUB)v")>;
644def : InstRW<[M3WriteNEONA],  (instregex "^FADDP")>;
645def : InstRW<[M3WriteNMSC1],  (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>;
646def : InstRW<[M3WriteFCVT3],  (instregex "^FCVT(L|N|XN)v")>;
647def : InstRW<[M3WriteFCVT2],  (instregex "^FCVT[AMNPZ][SU]v")>;
648def : InstRW<[M3WriteFCVT2],  (instregex "^[SU]CVTFv")>;
649def : InstRW<[M3WriteFDIV10], (instrs FDIVv2f32)>;
650def : InstRW<[M3WriteNEONV],  (instrs FDIVv4f32)>;
651def : InstRW<[M3WriteNEONW],  (instrs FDIVv2f64)>;
652def : InstRW<[M3WriteNMSC1],  (instregex "^F(MAX|MIN)(NM)?v")>;
653def : InstRW<[M3WriteNMSC2],  (instregex "^F(MAX|MIN)(NM)?Pv")>;
654def : InstRW<[M3WriteNEONZ],  (instregex "^F(MAX|MIN)(NM)?Vv")>;
655def : InstRW<[M3WriteFMAC3],  (instregex "^FMULX?v.[fi]")>;
656def : InstRW<[M3WriteFMAC4,
657              M3ReadFMAC],    (instregex "^FML[AS]v.f")>;
658def : InstRW<[M3WriteFMAC5,
659              M3ReadFMAC],    (instregex "^FML[AS]v.i")>;
660def : InstRW<[M3WriteNALU1],  (instregex "^FNEGv")>;
661def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
662def : InstRW<[M3WriteFSQR17], (instrs FSQRTv2f32)>;
663def : InstRW<[M3WriteNEONX],  (instrs FSQRTv4f32)>;
664def : InstRW<[M3WriteNEONY],  (instrs FSQRTv2f64)>;
665
666// ASIMD miscellaneous instructions.
667def : InstRW<[M3WriteNALU1], (instregex "^RBITv")>;
668def : InstRW<[M3WriteNALU1], (instregex "^(BIF|BIT|BSL|BSP)v")>;
669def : InstRW<[M3WriteNEONB], (instregex "^DUPv.+gpr")>;
670def : InstRW<[M3WriteNSHF1], (instregex "^DUPv.+lane")>;
671def : InstRW<[M3WriteNSHF1], (instregex "^EXTv")>;
672def : InstRW<[M3WriteNSHF1], (instregex "^[SU]?Q?XTU?Nv")>;
673def : InstRW<[M3WriteNSHF1], (instregex "^DUP(i8|i16|i32|i64)$")>;
674def : InstRW<[M3WriteNSHF1], (instregex "^INSv.+lane")>;
675def : InstRW<[M3WriteMOVI],  (instregex "^MOVI")>;
676def : InstRW<[M3WriteNALU1], (instregex "^FMOVv")>;
677def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev[248]")>;
678def : InstRW<[M3WriteFMAC4,
679              M3ReadFMAC],   (instregex "^F(RECP|RSQRT)Sv")>;
680def : InstRW<[M3WriteNSHF1], (instregex "^REV(16|32|64)v")>;
681def : InstRW<[M3WriteNSHF1], (instregex "^TB[LX]v")>;
682def : InstRW<[M3WriteNEOND], (instregex "^[SU]MOVv")>;
683def : InstRW<[M3WriteNSHF3], (instregex "^INSv.+gpr")>;
684def : InstRW<[M3WriteNSHF1], (instregex "^(TRN|UZP|ZIP)[12]v")>;
685
686// ASIMD load instructions.
687def : InstRW<[M3WriteL5],   (instregex "LD1Onev(8b|4h|2s|1d)$")>;
688def : InstRW<[M3WriteL5,
689              M3WriteA1],   (instregex "LD1Onev(8b|4h|2s|1d)_POST")>;
690def : InstRW<[M3WriteL5],   (instregex "LD1Onev(16b|8h|4s|2d)$")>;
691def : InstRW<[M3WriteL5,
692              M3WriteA1],   (instregex "LD1Onev(16b|8h|4s|2d)_POST")>;
693
694def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>;
695def : InstRW<[M3WriteVLDA,
696              M3WriteA1],   (instregex "LD1Twov(8b|4h|2s|1d)_POST")>;
697def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>;
698def : InstRW<[M3WriteVLDA,
699              M3WriteA1],   (instregex "LD1Twov(16b|8h|4s|2d)_POST")>;
700
701def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>;
702def : InstRW<[M3WriteVLDB,
703              M3WriteA1],   (instregex "LD1Threev(8b|4h|2s|1d)_POST")>;
704def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>;
705def : InstRW<[M3WriteVLDB,
706              M3WriteA1],   (instregex "LD1Threev(16b|8h|4s|2d)_POST")>;
707
708def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
709def : InstRW<[M3WriteVLDC,
710              M3WriteA1],   (instregex "LD1Fourv(8b|4h|2s|1d)_POST")>;
711def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
712def : InstRW<[M3WriteVLDC,
713              M3WriteA1],   (instregex "LD1Fourv(16b|8h|4s|2d)_POST")>;
714
715def : InstRW<[M3WriteVLDD], (instregex "LD1i(8|16|32)$")>;
716def : InstRW<[M3WriteVLDD,
717              M3WriteA1],   (instregex "LD1i(8|16|32)_POST")>;
718def : InstRW<[M3WriteVLDE], (instregex "LD1i(64)$")>;
719def : InstRW<[M3WriteVLDE,
720              M3WriteA1],   (instregex "LD1i(64)_POST")>;
721
722def : InstRW<[M3WriteL5],   (instregex "LD1Rv(8b|4h|2s|1d)$")>;
723def : InstRW<[M3WriteL5,
724              M3WriteA1],   (instregex "LD1Rv(8b|4h|2s|1d)_POST")>;
725def : InstRW<[M3WriteL5],   (instregex "LD1Rv(16b|8h|4s|2d)$")>;
726def : InstRW<[M3WriteL5,
727              M3WriteA1],   (instregex "LD1Rv(16b|8h|4s|2d)_POST")>;
728
729def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>;
730def : InstRW<[M3WriteVLDF,
731              M3WriteA1],   (instregex "LD2Twov(8b|4h|2s)_POST")>;
732def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
733def : InstRW<[M3WriteVLDF,
734              M3WriteA1],   (instregex "LD2Twov(16b|8h|4s|2d)_POST")>;
735
736def : InstRW<[M3WriteVLDG], (instregex "LD2i(8|16|32)$")>;
737def : InstRW<[M3WriteVLDG,
738              M3WriteA1],   (instregex "LD2i(8|16|32)_POST")>;
739def : InstRW<[M3WriteVLDH], (instregex "LD2i(64)$")>;
740def : InstRW<[M3WriteVLDH,
741              M3WriteA1],   (instregex "LD2i(64)_POST")>;
742
743def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(8b|4h|2s|1d)$")>;
744def : InstRW<[M3WriteVLDA,
745              M3WriteA1],   (instregex "LD2Rv(8b|4h|2s|1d)_POST")>;
746def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>;
747def : InstRW<[M3WriteVLDA,
748              M3WriteA1],   (instregex "LD2Rv(16b|8h|4s|2d)_POST")>;
749
750def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>;
751def : InstRW<[M3WriteVLDI,
752              M3WriteA1],   (instregex "LD3Threev(8b|4h|2s)_POST")>;
753def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(16b|8h|4s|2d)$")>;
754def : InstRW<[M3WriteVLDI,
755              M3WriteA1],   (instregex "LD3Threev(16b|8h|4s|2d)_POST")>;
756
757def : InstRW<[M3WriteVLDJ], (instregex "LD3i(8|16|32)$")>;
758def : InstRW<[M3WriteVLDJ,
759              M3WriteA1],   (instregex "LD3i(8|16|32)_POST")>;
760def : InstRW<[M3WriteVLDL], (instregex "LD3i(64)$")>;
761def : InstRW<[M3WriteVLDL,
762              M3WriteA1],   (instregex "LD3i(64)_POST")>;
763
764def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(8b|4h|2s|1d)$")>;
765def : InstRW<[M3WriteVLDB,
766              M3WriteA1],   (instregex "LD3Rv(8b|4h|2s|1d)_POST")>;
767def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(16b|8h|4s|2d)$")>;
768def : InstRW<[M3WriteVLDB,
769              M3WriteA1],   (instregex "LD3Rv(16b|8h|4s|2d)_POST")>;
770
771def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>;
772def : InstRW<[M3WriteVLDN,
773              M3WriteA1],   (instregex "LD4Fourv(8b|4h|2s)_POST")>;
774def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;
775def : InstRW<[M3WriteVLDN,
776              M3WriteA1],   (instregex "LD4Fourv(16b|8h|4s|2d)_POST")>;
777
778def : InstRW<[M3WriteVLDK], (instregex "LD4i(8|16|32)$")>;
779def : InstRW<[M3WriteVLDK,
780              M3WriteA1],   (instregex "LD4i(8|16|32)_POST")>;
781def : InstRW<[M3WriteVLDM], (instregex "LD4i(64)$")>;
782def : InstRW<[M3WriteVLDM,
783              M3WriteA1],   (instregex "LD4i(64)_POST")>;
784
785def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(8b|4h|2s|1d)$")>;
786def : InstRW<[M3WriteVLDC,
787              M3WriteA1],   (instregex "LD4Rv(8b|4h|2s|1d)_POST")>;
788def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(16b|8h|4s|2d)$")>;
789def : InstRW<[M3WriteVLDC,
790              M3WriteA1],   (instregex "LD4Rv(16b|8h|4s|2d)_POST")>;
791
792// ASIMD store instructions.
793def : InstRW<[WriteVST],    (instregex "ST1Onev(8b|4h|2s|1d)$")>;
794def : InstRW<[WriteVST,
795              WriteAdr],    (instregex "ST1Onev(8b|4h|2s|1d)_POST")>;
796def : InstRW<[WriteVST],    (instregex "ST1Onev(16b|8h|4s|2d)$")>;
797def : InstRW<[WriteVST,
798              WriteAdr],    (instregex "ST1Onev(16b|8h|4s|2d)_POST")>;
799
800def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>;
801def : InstRW<[M3WriteVSTA,
802              WriteAdr],    (instregex "ST1Twov(8b|4h|2s|1d)_POST")>;
803def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>;
804def : InstRW<[M3WriteVSTA,
805              WriteAdr],    (instregex "ST1Twov(16b|8h|4s|2d)_POST")>;
806
807def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>;
808def : InstRW<[M3WriteVSTB,
809              WriteAdr],    (instregex "ST1Threev(8b|4h|2s|1d)_POST")>;
810def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>;
811def : InstRW<[M3WriteVSTB,
812              WriteAdr],    (instregex "ST1Threev(16b|8h|4s|2d)_POST")>;
813
814def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
815def : InstRW<[M3WriteVSTC,
816              WriteAdr],    (instregex "ST1Fourv(8b|4h|2s|1d)_POST")>;
817def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
818def : InstRW<[M3WriteVSTC,
819              WriteAdr],    (instregex "ST1Fourv(16b|8h|4s|2d)_POST")>;
820
821def : InstRW<[M3WriteVSTD], (instregex "ST1i(8|16|32|64)$")>;
822def : InstRW<[M3WriteVSTD,
823              WriteAdr],    (instregex "ST1i(8|16|32|64)_POST")>;
824
825def : InstRW<[M3WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>;
826def : InstRW<[M3WriteVSTD,
827              WriteAdr],    (instregex "ST2Twov(8b|4h|2s)_POST")>;
828def : InstRW<[M3WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
829def : InstRW<[M3WriteVSTE,
830              WriteAdr],    (instregex "ST2Twov(16b|8h|4s|2d)_POST")>;
831
832def : InstRW<[M3WriteVSTD], (instregex "ST2i(8|16|32)$")>;
833def : InstRW<[M3WriteVSTD,
834              WriteAdr],    (instregex "ST2i(8|16|32)_POST")>;
835def : InstRW<[M3WriteVSTD], (instregex "ST2i(64)$")>;
836def : InstRW<[M3WriteVSTD,
837              WriteAdr],    (instregex "ST2i(64)_POST")>;
838
839def : InstRW<[M3WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>;
840def : InstRW<[M3WriteVSTF,
841              WriteAdr],    (instregex "ST3Threev(8b|4h|2s)_POST")>;
842def : InstRW<[M3WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>;
843def : InstRW<[M3WriteVSTG,
844              WriteAdr],    (instregex "ST3Threev(16b|8h|4s|2d)_POST")>;
845
846def : InstRW<[M3WriteVSTH], (instregex "ST3i(8|16|32)$")>;
847def : InstRW<[M3WriteVSTH,
848              WriteAdr],    (instregex "ST3i(8|16|32)_POST")>;
849def : InstRW<[M3WriteVSTF], (instregex "ST3i(64)$")>;
850def : InstRW<[M3WriteVSTF,
851              WriteAdr],    (instregex "ST3i(64)_POST")>;
852
853def : InstRW<[M3WriteVSTF], (instregex "ST4Fourv(8b|4h|2s)$")>;
854def : InstRW<[M3WriteVSTF,
855              WriteAdr],    (instregex "ST4Fourv(8b|4h|2s)_POST")>;
856def : InstRW<[M3WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>;
857def : InstRW<[M3WriteVSTI,
858              WriteAdr],    (instregex "ST4Fourv(16b|8h|4s|2d)_POST")>;
859
860def : InstRW<[M3WriteVSTF], (instregex "ST4i(8|16|32|64)$")>;
861def : InstRW<[M3WriteVSTF,
862              WriteAdr],    (instregex "ST4i(8|16|32|64)_POST")>;
863
864// Cryptography instructions.
865def : InstRW<[M3WriteAES],    (instregex "^AES[DE]")>;
866def : InstRW<[M3WriteAES,
867              M3ReadAES],     (instregex "^AESI?MC")>;
868
869def : InstRW<[M3WriteNCRY3A], (instregex "^PMULL?v")>;
870
871def : InstRW<[M3WriteNCRY1A], (instregex "^SHA1([CHMP]|SU[01])")>;
872def : InstRW<[M3WriteNCRY1A], (instregex "^SHA256SU0")>;
873def : InstRW<[M3WriteNCRY5A], (instregex "^SHA256(H2?|SU1)")>;
874
875// CRC instructions.
876def : InstRW<[M3WriteC2], (instregex "^CRC32")>;
877
878} // SchedModel = ExynosM3Model
879