1//=- AArch64SchedExynosM3.td - Samsung Exynos M3 Sched Defs --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for the Samsung Exynos M3 to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// The Exynos-M3 is an advanced superscalar microprocessor with a 6-wide 16// in-order stage for decode and dispatch and a wider issue stage. 17// The execution units and loads and stores are out-of-order. 18 19def ExynosM3Model : SchedMachineModel { 20 let IssueWidth = 6; // Up to 6 uops per cycle. 21 let MicroOpBufferSize = 228; // ROB size. 22 let LoopMicroOpBufferSize = 40; // Based on the instruction queue size. 23 let LoadLatency = 4; // Optimistic load cases. 24 let MispredictPenalty = 16; // Minimum branch misprediction penalty. 25 let CompleteModel = 1; // Use the default model otherwise. 26 27 list<Predicate> UnsupportedFeatures = SVEUnsupported.F; 28} 29 30//===----------------------------------------------------------------------===// 31// Define each kind of processor resource and number available on the Exynos-M3, 32// which has 12 pipelines, each with its own queue with out-of-order dispatch. 33 34let SchedModel = ExynosM3Model in { 35 36def M3UnitA : ProcResource<2>; // Simple integer 37def M3UnitC : ProcResource<2>; // Simple and complex integer 38def M3UnitD : ProcResource<1>; // Integer division (inside C0, serialized) 39def M3UnitB : ProcResource<2>; // Branch 40def M3UnitL : ProcResource<2>; // Load 41def M3UnitS : ProcResource<1>; // Store 42def M3PipeF0 : ProcResource<1>; // FP #0 43let Super = M3PipeF0 in { 44 def M3UnitFMAC0 : ProcResource<1>; // FP multiplication 45 def M3UnitFADD0 : ProcResource<1>; // Simple FP 46 def M3UnitFCVT0 : ProcResource<1>; // FP conversion 47 def M3UnitFSQR : ProcResource<2>; // FP square root (serialized) 48 def M3UnitNALU0 : ProcResource<1>; // Simple vector 49 def M3UnitNMSC : ProcResource<1>; // FP and vector miscellanea 50 def M3UnitNSHT0 : ProcResource<1>; // Vector shifting 51 def M3UnitNSHF0 : ProcResource<1>; // Vector shuffling 52} 53def M3PipeF1 : ProcResource<1>; // FP #1 54let Super = M3PipeF1 in { 55 def M3UnitFMAC1 : ProcResource<1>; // FP multiplication 56 def M3UnitFADD1 : ProcResource<1>; // Simple FP 57 def M3UnitFDIV0 : ProcResource<2>; // FP division (serialized) 58 def M3UnitFCVT1 : ProcResource<1>; // FP conversion 59 def M3UnitFST0 : ProcResource<1>; // FP store 60 def M3UnitNALU1 : ProcResource<1>; // Simple vector 61 def M3UnitNCRY0 : ProcResource<1>; // Cryptographic 62 def M3UnitNMUL : ProcResource<1>; // Vector multiplication 63 def M3UnitNSHT1 : ProcResource<1>; // Vector shifting 64 def M3UnitNSHF1 : ProcResource<1>; // Vector shuffling 65} 66def M3PipeF2 : ProcResource<1>; // FP #2 67let Super = M3PipeF2 in { 68 def M3UnitFMAC2 : ProcResource<1>; // FP multiplication 69 def M3UnitFADD2 : ProcResource<1>; // Simple FP 70 def M3UnitFDIV1 : ProcResource<2>; // FP division (serialized) 71 def M3UnitFST1 : ProcResource<1>; // FP store 72 def M3UnitNALU2 : ProcResource<1>; // Simple vector 73 def M3UnitNCRY1 : ProcResource<1>; // Cryptographic 74 def M3UnitNSHT2 : ProcResource<1>; // Vector shifting 75 def M3UnitNSHF2 : ProcResource<1>; // Vector shuffling 76} 77 78 79def M3UnitALU : ProcResGroup<[M3UnitA, 80 M3UnitC]>; 81def M3UnitFMAC : ProcResGroup<[M3UnitFMAC0, 82 M3UnitFMAC1, 83 M3UnitFMAC2]>; 84def M3UnitFADD : ProcResGroup<[M3UnitFADD0, 85 M3UnitFADD1, 86 M3UnitFADD2]>; 87def M3UnitFDIV : ProcResGroup<[M3UnitFDIV0, 88 M3UnitFDIV1]>; 89def M3UnitFCVT : ProcResGroup<[M3UnitFCVT0, 90 M3UnitFCVT1]>; 91def M3UnitFST : ProcResGroup<[M3UnitFST0, 92 M3UnitFST1]>; 93def M3UnitNALU : ProcResGroup<[M3UnitNALU0, 94 M3UnitNALU1, 95 M3UnitNALU2]>; 96def M3UnitNCRY : ProcResGroup<[M3UnitNCRY0, 97 M3UnitNCRY1]>; 98def M3UnitNSHT : ProcResGroup<[M3UnitNSHT0, 99 M3UnitNSHT1, 100 M3UnitNSHT2]>; 101def M3UnitNSHF : ProcResGroup<[M3UnitNSHF0, 102 M3UnitNSHF1, 103 M3UnitNSHF2]>; 104 105//===----------------------------------------------------------------------===// 106// Coarse scheduling model. 107 108def M3WriteZ0 : SchedWriteRes<[]> { let Latency = 0; 109 let NumMicroOps = 1; } 110def M3WriteZ1 : SchedWriteRes<[]> { let Latency = 1; 111 let NumMicroOps = 0; } 112 113def M3WriteA1 : SchedWriteRes<[M3UnitALU]> { let Latency = 1; } 114def M3WriteAA : SchedWriteRes<[M3UnitALU]> { let Latency = 2; 115 let ResourceCycles = [2]; } 116def M3WriteAB : SchedWriteRes<[M3UnitALU, 117 M3UnitC]> { let Latency = 1; 118 let NumMicroOps = 2; } 119def M3WriteAC : SchedWriteRes<[M3UnitALU, 120 M3UnitALU, 121 M3UnitC]> { let Latency = 2; 122 let NumMicroOps = 3; } 123def M3WriteAD : SchedWriteRes<[M3UnitALU, 124 M3UnitC]> { let Latency = 2; 125 let NumMicroOps = 2; } 126def M3WriteC1 : SchedWriteRes<[M3UnitC]> { let Latency = 1; } 127def M3WriteC2 : SchedWriteRes<[M3UnitC]> { let Latency = 2; } 128def M3WriteAU : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M3WriteZ0]>, 129 SchedVar<ExynosArithPred, [M3WriteA1]>, 130 SchedVar<ExynosLogicPred, [M3WriteA1]>, 131 SchedVar<NoSchedPred, [M3WriteAA]>]>; 132def M3WriteAV : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M3WriteZ0]>, 133 SchedVar<NoSchedPred, [M3WriteAA]>]>; 134def M3WriteAW : SchedWriteVariant<[SchedVar<IsZeroIdiomPred, [M3WriteZ0]>, 135 SchedVar<NoSchedPred, [M3WriteAA]>]>; 136def M3WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M3WriteA1]>, 137 SchedVar<ExynosLogicPred, [M3WriteA1]>, 138 SchedVar<NoSchedPred, [M3WriteAA]>]>; 139def M3WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M3WriteA1]>, 140 SchedVar<NoSchedPred, [M3WriteAA]>]>; 141 142def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; } 143def M3WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M3WriteAC]>, 144 SchedVar<NoSchedPred, [M3WriteAB]>]>; 145 146def M3WriteL4 : SchedWriteRes<[M3UnitL]> { let Latency = 4; } 147def M3WriteL5 : SchedWriteRes<[M3UnitL]> { let Latency = 5; } 148def M3WriteLA : SchedWriteRes<[M3UnitL, 149 M3UnitL]> { let Latency = 5; 150 let NumMicroOps = 1; } 151def M3WriteLB : SchedWriteRes<[M3UnitA, 152 M3UnitL]> { let Latency = 5; 153 let NumMicroOps = 2; } 154def M3WriteLC : SchedWriteRes<[M3UnitA, 155 M3UnitL, 156 M3UnitL]> { let Latency = 5; 157 let NumMicroOps = 2; } 158def M3WriteLD : SchedWriteRes<[M3UnitA, 159 M3UnitL]> { let Latency = 4; 160 let NumMicroOps = 2; } 161def M3WriteLE : SchedWriteRes<[M3UnitA, 162 M3UnitL]> { let Latency = 6; 163 let NumMicroOps = 2; } 164def M3WriteLH : SchedWriteRes<[]> { let Latency = 5; 165 let NumMicroOps = 0; } 166def M3WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteL5]>, 167 SchedVar<NoSchedPred, [M3WriteL4]>]>; 168 169def M3WriteS1 : SchedWriteRes<[M3UnitS]> { let Latency = 1; } 170def M3WriteSA : SchedWriteRes<[M3UnitA, 171 M3UnitS, 172 M3UnitFST]> { let Latency = 3; 173 let NumMicroOps = 2; } 174def M3WriteSB : SchedWriteRes<[M3UnitA, 175 M3UnitS]> { let Latency = 2; 176 let NumMicroOps = 2; } 177 178def M3ReadAdrBase : SchedReadVariant<[SchedVar<ExynosScaledIdxPred, [ReadDefault]>, 179 SchedVar<NoSchedPred, [ReadDefault]>]>; 180 181// Branch instructions. 182def : SchedAlias<WriteBr, M3WriteZ0>; 183def : SchedAlias<WriteBrReg, M3WriteC1>; 184 185// Arithmetic and logical integer instructions. 186def : SchedAlias<WriteI, M3WriteA1>; 187def : SchedAlias<WriteISReg, M3WriteA1>; 188def : SchedAlias<WriteIEReg, M3WriteA1>; 189def : SchedAlias<WriteIS, M3WriteA1>; 190 191// Move instructions. 192def : SchedAlias<WriteImm, M3WriteA1>; 193 194// Divide and multiply instructions. 195def : WriteRes<WriteID32, [M3UnitC, 196 M3UnitD]> { let Latency = 12; 197 let ResourceCycles = [1, 12]; } 198def : WriteRes<WriteID64, [M3UnitC, 199 M3UnitD]> { let Latency = 21; 200 let ResourceCycles = [1, 21]; } 201def : WriteRes<WriteIM32, [M3UnitC]> { let Latency = 3; } 202def : WriteRes<WriteIM64, [M3UnitC]> { let Latency = 4; 203 let ResourceCycles = [2]; } 204 205// Miscellaneous instructions. 206def : SchedAlias<WriteExtr, M3WriteAY>; 207 208// Addressing modes. 209def : SchedAlias<WriteAdr, M3WriteZ1>; 210def : SchedAlias<ReadAdrBase, M3ReadAdrBase>; 211 212// Load instructions. 213def : SchedAlias<WriteLD, M3WriteL4>; 214def : WriteRes<WriteLDHi, []> { let Latency = 4; 215 let NumMicroOps = 0; } 216def : SchedAlias<WriteLDIdx, M3WriteLB>; 217 218// Store instructions. 219def : SchedAlias<WriteST, M3WriteS1>; 220def : SchedAlias<WriteSTP, M3WriteS1>; 221def : SchedAlias<WriteSTX, M3WriteS1>; 222def : SchedAlias<WriteSTIdx, M3WriteSB>; 223 224// FP data instructions. 225def : WriteRes<WriteF, [M3UnitFADD]> { let Latency = 2; } 226def : WriteRes<WriteFCmp, [M3UnitNMSC]> { let Latency = 2; } 227def : WriteRes<WriteFDiv, [M3UnitFDIV]> { let Latency = 12; 228 let ResourceCycles = [12]; } 229def : WriteRes<WriteFMul, [M3UnitFMAC]> { let Latency = 4; } 230 231// FP miscellaneous instructions. 232def : WriteRes<WriteFCvt, [M3UnitFCVT]> { let Latency = 3; } 233def : WriteRes<WriteFImm, [M3UnitNALU]> { let Latency = 1; } 234def : WriteRes<WriteFCopy, [M3UnitNALU]> { let Latency = 1; } 235 236// FP load instructions. 237def : SchedAlias<WriteVLD, M3WriteL5>; 238 239// FP store instructions. 240def : WriteRes<WriteVST, [M3UnitS, 241 M3UnitFST]> { let Latency = 1; 242 let NumMicroOps = 1; } 243 244// ASIMD FP instructions. 245def : WriteRes<WriteV, [M3UnitNALU]> { let Latency = 3; } 246 247// Other miscellaneous instructions. 248def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 249def : WriteRes<WriteBarrier, []> { let Latency = 1; } 250def : WriteRes<WriteHint, []> { let Latency = 1; } 251def : WriteRes<WriteSys, []> { let Latency = 1; } 252 253//===----------------------------------------------------------------------===// 254// Generic fast forwarding. 255 256// TODO: Add FP register forwarding rules. 257 258def : ReadAdvance<ReadI, 0>; 259def : ReadAdvance<ReadISReg, 0>; 260def : ReadAdvance<ReadIEReg, 0>; 261def : ReadAdvance<ReadIM, 0>; 262// TODO: The forwarding for 32 bits actually saves 2 cycles. 263def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>; 264def : ReadAdvance<ReadID, 0>; 265def : ReadAdvance<ReadExtrHi, 0>; 266def : ReadAdvance<ReadAdrBase, 0>; 267def : ReadAdvance<ReadVLD, 0>; 268 269//===----------------------------------------------------------------------===// 270// Finer scheduling model. 271 272def M3WriteNEONA : SchedWriteRes<[M3UnitNSHF, 273 M3UnitFADD]> { let Latency = 3; 274 let NumMicroOps = 2; } 275def M3WriteNEONB : SchedWriteRes<[M3UnitNALU, 276 M3UnitFST]> { let Latency = 10; 277 let NumMicroOps = 2; } 278def M3WriteNEOND : SchedWriteRes<[M3UnitNSHF, 279 M3UnitFST]> { let Latency = 6; 280 let NumMicroOps = 2; } 281def M3WriteNEONH : SchedWriteRes<[M3UnitNALU, 282 M3UnitS]> { let Latency = 5; 283 let NumMicroOps = 2; } 284def M3WriteNEONI : SchedWriteRes<[M3UnitNSHF, 285 M3UnitS]> { let Latency = 5; 286 let NumMicroOps = 2; } 287def M3WriteNEONV : SchedWriteRes<[M3UnitFDIV0, 288 M3UnitFDIV1]> { let Latency = 7; 289 let NumMicroOps = 2; 290 let ResourceCycles = [8, 8]; } 291def M3WriteNEONW : SchedWriteRes<[M3UnitFDIV0, 292 M3UnitFDIV1]> { let Latency = 12; 293 let NumMicroOps = 2; 294 let ResourceCycles = [13, 13]; } 295def M3WriteNEONX : SchedWriteRes<[M3UnitFSQR, 296 M3UnitFSQR]> { let Latency = 18; 297 let NumMicroOps = 2; 298 let ResourceCycles = [19, 19]; } 299def M3WriteNEONY : SchedWriteRes<[M3UnitFSQR, 300 M3UnitFSQR]> { let Latency = 25; 301 let NumMicroOps = 2; 302 let ResourceCycles = [26, 26]; } 303def M3WriteNEONZ : SchedWriteRes<[M3UnitNMSC, 304 M3UnitNMSC]> { let Latency = 5; 305 let NumMicroOps = 2; } 306def M3WriteFADD2 : SchedWriteRes<[M3UnitFADD]> { let Latency = 2; } 307def M3WriteFCVT2 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 2; } 308def M3WriteFCVT3 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 3; } 309def M3WriteFCVT3A : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 3; } 310def M3WriteFCVT4A : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 4; } 311def M3WriteFCVT4 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 4; } 312def M3WriteFDIV10 : SchedWriteRes<[M3UnitFDIV]> { let Latency = 7; 313 let ResourceCycles = [8]; } 314def M3WriteFDIV12 : SchedWriteRes<[M3UnitFDIV]> { let Latency = 12; 315 let ResourceCycles = [13]; } 316def M3WriteFMAC3 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 3; } 317def M3WriteFMAC4 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 4; } 318def M3WriteFMAC5 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 5; } 319def M3WriteFSQR17 : SchedWriteRes<[M3UnitFSQR]> { let Latency = 18; 320 let ResourceCycles = [19]; } 321def M3WriteFSQR25 : SchedWriteRes<[M3UnitFSQR]> { let Latency = 25; 322 let ResourceCycles = [26]; } 323def M3WriteNALU1 : SchedWriteRes<[M3UnitNALU]> { let Latency = 1; } 324def M3WriteNCRY1A : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 1; } 325def M3WriteNCRY3A : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 3; } 326def M3WriteNCRY5A : SchedWriteRes<[M3UnitNCRY]> { let Latency = 5; } 327def M3WriteNMSC1 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 1; } 328def M3WriteNMSC2 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 2; } 329def M3WriteNMSC3 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 3; } 330def M3WriteNMUL3 : SchedWriteRes<[M3UnitNMUL]> { let Latency = 3; } 331def M3WriteNSHF1 : SchedWriteRes<[M3UnitNSHF]> { let Latency = 1; } 332def M3WriteNSHF3 : SchedWriteRes<[M3UnitNSHF]> { let Latency = 3; } 333def M3WriteNSHT1 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 1; } 334def M3WriteNSHT2 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 2; } 335def M3WriteNSHT3 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 3; } 336def M3WriteVLDA : SchedWriteRes<[M3UnitL, 337 M3UnitL]> { let Latency = 5; 338 let NumMicroOps = 2; } 339def M3WriteVLDB : SchedWriteRes<[M3UnitL, 340 M3UnitL, 341 M3UnitL]> { let Latency = 6; 342 let NumMicroOps = 3; } 343def M3WriteVLDC : SchedWriteRes<[M3UnitL, 344 M3UnitL, 345 M3UnitL, 346 M3UnitL]> { let Latency = 6; 347 let NumMicroOps = 4; } 348def M3WriteVLDD : SchedWriteRes<[M3UnitL, 349 M3UnitNALU]> { let Latency = 7; 350 let NumMicroOps = 2; 351 let ResourceCycles = [2, 1]; } 352def M3WriteVLDE : SchedWriteRes<[M3UnitL, 353 M3UnitNALU]> { let Latency = 6; 354 let NumMicroOps = 2; 355 let ResourceCycles = [2, 1]; } 356def M3WriteVLDF : SchedWriteRes<[M3UnitL, 357 M3UnitL]> { let Latency = 10; 358 let NumMicroOps = 2; 359 let ResourceCycles = [5, 5]; } 360def M3WriteVLDG : SchedWriteRes<[M3UnitL, 361 M3UnitNALU, 362 M3UnitNALU]> { let Latency = 7; 363 let NumMicroOps = 3; 364 let ResourceCycles = [2, 1, 1]; } 365def M3WriteVLDH : SchedWriteRes<[M3UnitL, 366 M3UnitNALU, 367 M3UnitNALU]> { let Latency = 6; 368 let NumMicroOps = 3; 369 let ResourceCycles = [2, 1, 1]; } 370def M3WriteVLDI : SchedWriteRes<[M3UnitL, 371 M3UnitL, 372 M3UnitL]> { let Latency = 12; 373 let NumMicroOps = 3; 374 let ResourceCycles = [6, 6, 6]; } 375def M3WriteVLDJ : SchedWriteRes<[M3UnitL, 376 M3UnitNALU, 377 M3UnitNALU, 378 M3UnitNALU]> { let Latency = 7; 379 let NumMicroOps = 4; 380 let ResourceCycles = [2, 1, 1, 1]; } 381def M3WriteVLDK : SchedWriteRes<[M3UnitL, 382 M3UnitNALU, 383 M3UnitNALU, 384 M3UnitNALU, 385 M3UnitNALU]> { let Latency = 9; 386 let NumMicroOps = 5; 387 let ResourceCycles = [4, 1, 1, 1, 1]; } 388def M3WriteVLDL : SchedWriteRes<[M3UnitL, 389 M3UnitNALU, 390 M3UnitNALU, 391 M3UnitL, 392 M3UnitNALU]> { let Latency = 6; 393 let NumMicroOps = 5; 394 let ResourceCycles = [6, 1, 1, 6, 1]; } 395def M3WriteVLDM : SchedWriteRes<[M3UnitL, 396 M3UnitNALU, 397 M3UnitNALU, 398 M3UnitL, 399 M3UnitNALU, 400 M3UnitNALU]> { let Latency = 7; 401 let NumMicroOps = 6; 402 let ResourceCycles = [6, 1, 1, 6, 1, 1]; } 403def M3WriteVLDN : SchedWriteRes<[M3UnitL, 404 M3UnitL, 405 M3UnitL, 406 M3UnitL]> { let Latency = 14; 407 let NumMicroOps = 4; 408 let ResourceCycles = [6, 6, 6, 6]; } 409def M3WriteVSTA : WriteSequence<[WriteVST], 2>; 410def M3WriteVSTB : WriteSequence<[WriteVST], 3>; 411def M3WriteVSTC : WriteSequence<[WriteVST], 4>; 412def M3WriteVSTD : SchedWriteRes<[M3UnitS, 413 M3UnitFST, 414 M3UnitS, 415 M3UnitFST]> { let Latency = 7; 416 let NumMicroOps = 4; 417 let ResourceCycles = [1, 3, 1, 3]; } 418def M3WriteVSTE : SchedWriteRes<[M3UnitS, 419 M3UnitFST, 420 M3UnitS, 421 M3UnitFST, 422 M3UnitS, 423 M3UnitFST]> { let Latency = 8; 424 let NumMicroOps = 6; 425 let ResourceCycles = [1, 3, 1, 3, 1, 3]; } 426def M3WriteVSTF : SchedWriteRes<[M3UnitNALU, 427 M3UnitFST, 428 M3UnitFST, 429 M3UnitS, 430 M3UnitFST, 431 M3UnitS, 432 M3UnitFST]> { let Latency = 15; 433 let NumMicroOps = 7; 434 let ResourceCycles = [1, 3, 3, 1, 3, 1, 3]; } 435def M3WriteVSTG : SchedWriteRes<[M3UnitNALU, 436 M3UnitFST, 437 M3UnitFST, 438 M3UnitS, 439 M3UnitFST, 440 M3UnitS, 441 M3UnitFST, 442 M3UnitS, 443 M3UnitFST]> { let Latency = 16; 444 let NumMicroOps = 9; 445 let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; } 446def M3WriteVSTH : SchedWriteRes<[M3UnitNALU, 447 M3UnitFST, 448 M3UnitFST, 449 M3UnitS, 450 M3UnitFST]> { let Latency = 14; 451 let NumMicroOps = 5; 452 let ResourceCycles = [1, 3, 3, 1, 3]; } 453def M3WriteVSTI : SchedWriteRes<[M3UnitNALU, 454 M3UnitFST, 455 M3UnitFST, 456 M3UnitS, 457 M3UnitFST, 458 M3UnitS, 459 M3UnitFST, 460 M3UnitS, 461 M3UnitFST]> { let Latency = 17; 462 let NumMicroOps = 9; 463 let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; } 464 465// Special cases. 466def M3WriteAES : SchedWriteRes<[M3UnitNCRY]> { let Latency = 1; } 467def M3WriteCOPY : SchedWriteVariant<[SchedVar<ExynosFPPred, [M3WriteNALU1]>, 468 SchedVar<NoSchedPred, [M3WriteZ0]>]>; 469def M3WriteMOVI : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M3WriteZ0]>, 470 SchedVar<NoSchedPred, [M3WriteNALU1]>]>; 471 472// Fast forwarding. 473def M3ReadAES : SchedReadAdvance<1, [M3WriteAES]>; 474def M3ReadFMAC : SchedReadAdvance<1, [M3WriteFMAC4, 475 M3WriteFMAC5]>; 476def M3ReadNMUL : SchedReadAdvance<1, [M3WriteNMUL3]>; 477 478// Branch instructions 479def : InstRW<[M3WriteB1], (instrs Bcc)>; 480def : InstRW<[M3WriteA1], (instrs BL)>; 481def : InstRW<[M3WriteBX], (instrs BLR)>; 482def : InstRW<[M3WriteC1], (instregex "^CBN?Z[WX]")>; 483def : InstRW<[M3WriteAD], (instregex "^TBN?Z[WX]")>; 484 485// Arithmetic and logical integer instructions. 486def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>; 487def : InstRW<[M3WriteAU], (instrs ORRWrs, ORRXrs)>; 488def : InstRW<[M3WriteAX], (instregex "^(ADD|SUB)S?[WX]rx(64)?$")>; 489def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>; 490def : InstRW<[M3WriteAV], (instrs ADDWri, ADDXri)>; 491def : InstRW<[M3WriteAW], (instrs ORRWri, ORRXri)>; 492 493// Move instructions. 494def : InstRW<[M3WriteCOPY], (instrs COPY)>; 495def : InstRW<[M3WriteZ0], (instrs ADR, ADRP)>; 496def : InstRW<[M3WriteZ0], (instregex "^MOV[NZ][WX]i")>; 497 498// Divide and multiply instructions. 499 500// Miscellaneous instructions. 501 502// Load instructions. 503def : InstRW<[M3WriteLD, 504 WriteLDHi, 505 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>; 506def : InstRW<[M3WriteLB, 507 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>; 508def : InstRW<[M3WriteLX, 509 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>; 510def : InstRW<[M3WriteLB, 511 ReadAdrBase], (instrs PRFMroW)>; 512def : InstRW<[M3WriteLX, 513 ReadAdrBase], (instrs PRFMroX)>; 514 515// Store instructions. 516def : InstRW<[M3WriteSB, 517 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>; 518def : InstRW<[WriteST, 519 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>; 520 521// FP data instructions. 522def : InstRW<[M3WriteNSHF1], (instregex "^FABS[DS]r")>; 523def : InstRW<[M3WriteFADD2], (instregex "^F(ADD|SUB)[DS]rr")>; 524def : InstRW<[M3WriteFDIV10], (instrs FDIVSrr)>; 525def : InstRW<[M3WriteFDIV12], (instrs FDIVDrr)>; 526def : InstRW<[M3WriteNMSC1], (instregex "^F(MAX|MIN).+rr")>; 527def : InstRW<[M3WriteFMAC3], (instregex "^FN?MUL[DS]rr")>; 528def : InstRW<[M3WriteFMAC4, 529 M3ReadFMAC], (instregex "^FN?M(ADD|SUB)[DS]rrr")>; 530def : InstRW<[M3WriteNALU1], (instregex "^FNEG[DS]r")>; 531def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT.+r")>; 532def : InstRW<[M3WriteNEONH], (instregex "^FCSEL[DS]rrr")>; 533def : InstRW<[M3WriteFSQR17], (instrs FSQRTSr)>; 534def : InstRW<[M3WriteFSQR25], (instrs FSQRTDr)>; 535 536// FP miscellaneous instructions. 537def : InstRW<[M3WriteFCVT3], (instregex "^FCVT[DHS][DHS]r")>; 538def : InstRW<[M3WriteFCVT4A], (instregex "^[SU]CVTF[SU][XW][DHS]ri")>; 539def : InstRW<[M3WriteFCVT3A], (instregex "^FCVT[AMNPZ][SU]U[XW][DHS]r")>; 540def : InstRW<[M3WriteFCVT3A], (instregex "^FCVTZ[SU][dhs]")>; 541def : InstRW<[M3WriteNALU1], (instregex "^FMOV[DS][ir]")>; 542def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev1")>; 543def : InstRW<[M3WriteNMSC1], (instregex "^FRECPXv1")>; 544def : InstRW<[M3WriteFMAC4, 545 M3ReadFMAC], (instregex "^F(RECP|RSQRT)S(16|32|64)")>; 546def : InstRW<[M3WriteNALU1], (instregex "^FMOV[WX][DS]r")>; 547def : InstRW<[M3WriteNALU1], (instregex "^FMOV[DS][WX]r")>; 548def : InstRW<[M3WriteNEONI], (instregex "^FMOV(DX|XD)Highr")>; 549 550// FP load instructions. 551def : InstRW<[WriteVLD], (instregex "^LDR[DSQ]l")>; 552def : InstRW<[WriteVLD], (instregex "^LDUR[BDHSQ]i")>; 553def : InstRW<[WriteVLD, 554 WriteAdr], (instregex "^LDR[BDHSQ](post|pre)")>; 555def : InstRW<[WriteVLD], (instregex "^LDR[BDHSQ]ui")>; 556def : InstRW<[M3WriteLE, 557 ReadAdrBase], (instregex "^LDR[BDHS]roW")>; 558def : InstRW<[WriteVLD, 559 ReadAdrBase], (instregex "^LDR[BDHS]roX")>; 560def : InstRW<[M3WriteLE, 561 ReadAdrBase], (instregex "^LDRQro[WX]")>; 562def : InstRW<[WriteVLD, 563 M3WriteLH], (instregex "^LDN?P[DS]i")>; 564def : InstRW<[M3WriteLA, 565 M3WriteLH], (instregex "^LDN?PQi")>; 566def : InstRW<[M3WriteLB, 567 M3WriteLH, 568 WriteAdr], (instregex "^LDP[DS](post|pre)")>; 569def : InstRW<[M3WriteLC, 570 M3WriteLH, 571 WriteAdr], (instregex "^LDPQ(post|pre)")>; 572 573// FP store instructions. 574def : InstRW<[WriteVST], (instregex "^STUR[BDHSQ]i")>; 575def : InstRW<[WriteVST, 576 WriteAdr], (instregex "^STR[BDHSQ](post|pre)")>; 577def : InstRW<[WriteVST], (instregex "^STR[BDHSQ]ui")>; 578def : InstRW<[M3WriteSA, 579 ReadAdrBase], (instregex "^STR[BDHS]roW")>; 580def : InstRW<[WriteVST, 581 ReadAdrBase], (instregex "^STR[BDHS]roX")>; 582def : InstRW<[M3WriteSA, 583 ReadAdrBase], (instregex "^STRQro[WX]")>; 584def : InstRW<[WriteVST], (instregex "^STN?P[DSQ]i")>; 585def : InstRW<[WriteVST, 586 WriteAdr], (instregex "^STP[DS](post|pre)")>; 587def : InstRW<[M3WriteSA, 588 WriteAdr], (instregex "^STPQ(post|pre)")>; 589 590// ASIMD instructions. 591def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ABAL?v")>; 592def : InstRW<[M3WriteNMSC1], (instregex "^[SU]ABDL?v")>; 593def : InstRW<[M3WriteNMSC1], (instregex "^((SQ)?ABS|SQNEG)v")>; 594def : InstRW<[M3WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>; 595def : InstRW<[M3WriteNMSC3], (instregex "^[SU]?ADDL?Pv")>; 596def : InstRW<[M3WriteNMSC3], (instregex "^[SU]H(ADD|SUB)v")>; 597def : InstRW<[M3WriteNMSC3], (instregex "^[SU](ADD|SUB)[LW]V?v")>; 598def : InstRW<[M3WriteNMSC3], (instregex "^R?(ADD|SUB)HN2?v")>; 599def : InstRW<[M3WriteNMSC3], (instregex "^[SU]Q(ADD|SUB)v")>; 600def : InstRW<[M3WriteNMSC3], (instregex "^(SU|US)QADDv")>; 601def : InstRW<[M3WriteNMSC3], (instregex "^[SU]RHADDv")>; 602def : InstRW<[M3WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>; 603def : InstRW<[M3WriteNALU1], (instregex "^CMTSTv")>; 604def : InstRW<[M3WriteNALU1], (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>; 605def : InstRW<[M3WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>; 606def : InstRW<[M3WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>; 607def : InstRW<[M3WriteNMSC3], (instregex "^[SU](MIN|MAX)Vv")>; 608def : InstRW<[M3WriteNMUL3], (instregex "^(MUL|SQR?DMULH)v")>; 609def : InstRW<[M3WriteNMUL3, 610 M3ReadNMUL], (instregex "^ML[AS]v")>; 611def : InstRW<[M3WriteNMUL3], (instregex "^[SU]ML[AS]Lv")>; 612def : InstRW<[M3WriteNMUL3], (instregex "^SQDML[AS]L")>; 613def : InstRW<[M3WriteNMUL3], (instregex "^(S|U|SQD)MULLv")>; 614def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ADALPv")>; 615def : InstRW<[M3WriteNSHT3], (instregex "^[SU]R?SRAv")>; 616def : InstRW<[M3WriteNSHT1], (instregex "^SHL[dv]")>; 617def : InstRW<[M3WriteNSHT1], (instregex "^[SU]SH[LR][dv]")>; 618def : InstRW<[M3WriteNSHT1], (instregex "^S[RS]I[dv]")>; 619def : InstRW<[M3WriteNSHT2], (instregex "^[SU]?SHLLv")>; 620def : InstRW<[M3WriteNSHT3], (instregex "^(([SU]Q)?R)?SHRU?N[bhsv]")>; 621def : InstRW<[M3WriteNSHT3], (instregex "^[SU]RSH[LR][dv]")>; 622def : InstRW<[M3WriteNSHT3], (instregex "^[SU]QR?SHLU?[bdhsv]")>; 623 624// ASIMD FP instructions. 625def : InstRW<[M3WriteNSHF1], (instregex "^FABSv")>; 626def : InstRW<[M3WriteFADD2], (instregex "^F(ABD|ADD|SUB)v")>; 627def : InstRW<[M3WriteNEONA], (instregex "^FADDP")>; 628def : InstRW<[M3WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>; 629def : InstRW<[M3WriteFCVT3], (instregex "^FCVT(L|N|XN)v")>; 630def : InstRW<[M3WriteFCVT2], (instregex "^FCVT[AMNPZ][SU]v")>; 631def : InstRW<[M3WriteFCVT2], (instregex "^[SU]CVTFv")>; 632def : InstRW<[M3WriteFDIV10], (instrs FDIVv2f32)>; 633def : InstRW<[M3WriteNEONV], (instrs FDIVv4f32)>; 634def : InstRW<[M3WriteNEONW], (instrs FDIVv2f64)>; 635def : InstRW<[M3WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?v")>; 636def : InstRW<[M3WriteNMSC2], (instregex "^F(MAX|MIN)(NM)?Pv")>; 637def : InstRW<[M3WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>; 638def : InstRW<[M3WriteFMAC3], (instregex "^FMULX?v.[fi]")>; 639def : InstRW<[M3WriteFMAC4, 640 M3ReadFMAC], (instregex "^FML[AS]v.f")>; 641def : InstRW<[M3WriteFMAC5, 642 M3ReadFMAC], (instregex "^FML[AS]v.i")>; 643def : InstRW<[M3WriteNALU1], (instregex "^FNEGv")>; 644def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>; 645def : InstRW<[M3WriteFSQR17], (instrs FSQRTv2f32)>; 646def : InstRW<[M3WriteNEONX], (instrs FSQRTv4f32)>; 647def : InstRW<[M3WriteNEONY], (instrs FSQRTv2f64)>; 648 649// ASIMD miscellaneous instructions. 650def : InstRW<[M3WriteNALU1], (instregex "^RBITv")>; 651def : InstRW<[M3WriteNALU1], (instregex "^(BIF|BIT|BSL)v")>; 652def : InstRW<[M3WriteNEONB], (instregex "^DUPv.+gpr")>; 653def : InstRW<[M3WriteNSHF1], (instregex "^DUPv.+lane")>; 654def : InstRW<[M3WriteNSHF1], (instregex "^EXTv")>; 655def : InstRW<[M3WriteNSHF1], (instregex "^[SU]?Q?XTU?Nv")>; 656def : InstRW<[M3WriteNSHF1], (instregex "^CPY")>; 657def : InstRW<[M3WriteNSHF1], (instregex "^INSv.+lane")>; 658def : InstRW<[M3WriteMOVI], (instregex "^MOVI")>; 659def : InstRW<[M3WriteNALU1], (instregex "^FMOVv")>; 660def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev[248]")>; 661def : InstRW<[M3WriteFMAC4, 662 M3ReadFMAC], (instregex "^F(RECP|RSQRT)Sv")>; 663def : InstRW<[M3WriteNSHF1], (instregex "^REV(16|32|64)v")>; 664def : InstRW<[M3WriteNSHF1], (instregex "^TB[LX]v")>; 665def : InstRW<[M3WriteNEOND], (instregex "^[SU]MOVv")>; 666def : InstRW<[M3WriteNSHF3], (instregex "^INSv.+gpr")>; 667def : InstRW<[M3WriteNSHF1], (instregex "^(TRN|UZP|ZIP)[12]v")>; 668 669// ASIMD load instructions. 670def : InstRW<[M3WriteL5], (instregex "LD1Onev(8b|4h|2s|1d)$")>; 671def : InstRW<[M3WriteL5, 672 M3WriteA1], (instregex "LD1Onev(8b|4h|2s|1d)_POST")>; 673def : InstRW<[M3WriteL5], (instregex "LD1Onev(16b|8h|4s|2d)$")>; 674def : InstRW<[M3WriteL5, 675 M3WriteA1], (instregex "LD1Onev(16b|8h|4s|2d)_POST")>; 676 677def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>; 678def : InstRW<[M3WriteVLDA, 679 M3WriteA1], (instregex "LD1Twov(8b|4h|2s|1d)_POST")>; 680def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>; 681def : InstRW<[M3WriteVLDA, 682 M3WriteA1], (instregex "LD1Twov(16b|8h|4s|2d)_POST")>; 683 684def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>; 685def : InstRW<[M3WriteVLDB, 686 M3WriteA1], (instregex "LD1Threev(8b|4h|2s|1d)_POST")>; 687def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>; 688def : InstRW<[M3WriteVLDB, 689 M3WriteA1], (instregex "LD1Threev(16b|8h|4s|2d)_POST")>; 690 691def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>; 692def : InstRW<[M3WriteVLDC, 693 M3WriteA1], (instregex "LD1Fourv(8b|4h|2s|1d)_POST")>; 694def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>; 695def : InstRW<[M3WriteVLDC, 696 M3WriteA1], (instregex "LD1Fourv(16b|8h|4s|2d)_POST")>; 697 698def : InstRW<[M3WriteVLDD], (instregex "LD1i(8|16|32)$")>; 699def : InstRW<[M3WriteVLDD, 700 M3WriteA1], (instregex "LD1i(8|16|32)_POST")>; 701def : InstRW<[M3WriteVLDE], (instregex "LD1i(64)$")>; 702def : InstRW<[M3WriteVLDE, 703 M3WriteA1], (instregex "LD1i(64)_POST")>; 704 705def : InstRW<[M3WriteL5], (instregex "LD1Rv(8b|4h|2s|1d)$")>; 706def : InstRW<[M3WriteL5, 707 M3WriteA1], (instregex "LD1Rv(8b|4h|2s|1d)_POST")>; 708def : InstRW<[M3WriteL5], (instregex "LD1Rv(16b|8h|4s|2d)$")>; 709def : InstRW<[M3WriteL5, 710 M3WriteA1], (instregex "LD1Rv(16b|8h|4s|2d)_POST")>; 711 712def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>; 713def : InstRW<[M3WriteVLDF, 714 M3WriteA1], (instregex "LD2Twov(8b|4h|2s)_POST")>; 715def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(16b|8h|4s|2d)$")>; 716def : InstRW<[M3WriteVLDF, 717 M3WriteA1], (instregex "LD2Twov(16b|8h|4s|2d)_POST")>; 718 719def : InstRW<[M3WriteVLDG], (instregex "LD2i(8|16|32)$")>; 720def : InstRW<[M3WriteVLDG, 721 M3WriteA1], (instregex "LD2i(8|16|32)_POST")>; 722def : InstRW<[M3WriteVLDH], (instregex "LD2i(64)$")>; 723def : InstRW<[M3WriteVLDH, 724 M3WriteA1], (instregex "LD2i(64)_POST")>; 725 726def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(8b|4h|2s|1d)$")>; 727def : InstRW<[M3WriteVLDA, 728 M3WriteA1], (instregex "LD2Rv(8b|4h|2s|1d)_POST")>; 729def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>; 730def : InstRW<[M3WriteVLDA, 731 M3WriteA1], (instregex "LD2Rv(16b|8h|4s|2d)_POST")>; 732 733def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>; 734def : InstRW<[M3WriteVLDI, 735 M3WriteA1], (instregex "LD3Threev(8b|4h|2s)_POST")>; 736def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(16b|8h|4s|2d)$")>; 737def : InstRW<[M3WriteVLDI, 738 M3WriteA1], (instregex "LD3Threev(16b|8h|4s|2d)_POST")>; 739 740def : InstRW<[M3WriteVLDJ], (instregex "LD3i(8|16|32)$")>; 741def : InstRW<[M3WriteVLDJ, 742 M3WriteA1], (instregex "LD3i(8|16|32)_POST")>; 743def : InstRW<[M3WriteVLDL], (instregex "LD3i(64)$")>; 744def : InstRW<[M3WriteVLDL, 745 M3WriteA1], (instregex "LD3i(64)_POST")>; 746 747def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(8b|4h|2s|1d)$")>; 748def : InstRW<[M3WriteVLDB, 749 M3WriteA1], (instregex "LD3Rv(8b|4h|2s|1d)_POST")>; 750def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(16b|8h|4s|2d)$")>; 751def : InstRW<[M3WriteVLDB, 752 M3WriteA1], (instregex "LD3Rv(16b|8h|4s|2d)_POST")>; 753 754def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>; 755def : InstRW<[M3WriteVLDN, 756 M3WriteA1], (instregex "LD4Fourv(8b|4h|2s)_POST")>; 757def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(16b|8h|4s|2d)$")>; 758def : InstRW<[M3WriteVLDN, 759 M3WriteA1], (instregex "LD4Fourv(16b|8h|4s|2d)_POST")>; 760 761def : InstRW<[M3WriteVLDK], (instregex "LD4i(8|16|32)$")>; 762def : InstRW<[M3WriteVLDK, 763 M3WriteA1], (instregex "LD4i(8|16|32)_POST")>; 764def : InstRW<[M3WriteVLDM], (instregex "LD4i(64)$")>; 765def : InstRW<[M3WriteVLDM, 766 M3WriteA1], (instregex "LD4i(64)_POST")>; 767 768def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(8b|4h|2s|1d)$")>; 769def : InstRW<[M3WriteVLDC, 770 M3WriteA1], (instregex "LD4Rv(8b|4h|2s|1d)_POST")>; 771def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(16b|8h|4s|2d)$")>; 772def : InstRW<[M3WriteVLDC, 773 M3WriteA1], (instregex "LD4Rv(16b|8h|4s|2d)_POST")>; 774 775// ASIMD store instructions. 776def : InstRW<[WriteVST], (instregex "ST1Onev(8b|4h|2s|1d)$")>; 777def : InstRW<[WriteVST, 778 WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST")>; 779def : InstRW<[WriteVST], (instregex "ST1Onev(16b|8h|4s|2d)$")>; 780def : InstRW<[WriteVST, 781 WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST")>; 782 783def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>; 784def : InstRW<[M3WriteVSTA, 785 WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST")>; 786def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>; 787def : InstRW<[M3WriteVSTA, 788 WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST")>; 789 790def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>; 791def : InstRW<[M3WriteVSTB, 792 WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST")>; 793def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>; 794def : InstRW<[M3WriteVSTB, 795 WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST")>; 796 797def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; 798def : InstRW<[M3WriteVSTC, 799 WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST")>; 800def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; 801def : InstRW<[M3WriteVSTC, 802 WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST")>; 803 804def : InstRW<[M3WriteVSTD], (instregex "ST1i(8|16|32|64)$")>; 805def : InstRW<[M3WriteVSTD, 806 WriteAdr], (instregex "ST1i(8|16|32|64)_POST")>; 807 808def : InstRW<[M3WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>; 809def : InstRW<[M3WriteVSTD, 810 WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST")>; 811def : InstRW<[M3WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>; 812def : InstRW<[M3WriteVSTE, 813 WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST")>; 814 815def : InstRW<[M3WriteVSTD], (instregex "ST2i(8|16|32)$")>; 816def : InstRW<[M3WriteVSTD, 817 WriteAdr], (instregex "ST2i(8|16|32)_POST")>; 818def : InstRW<[M3WriteVSTD], (instregex "ST2i(64)$")>; 819def : InstRW<[M3WriteVSTD, 820 WriteAdr], (instregex "ST2i(64)_POST")>; 821 822def : InstRW<[M3WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>; 823def : InstRW<[M3WriteVSTF, 824 WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST")>; 825def : InstRW<[M3WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>; 826def : InstRW<[M3WriteVSTG, 827 WriteAdr], (instregex "ST3Threev(16b|8h|4s|2d)_POST")>; 828 829def : InstRW<[M3WriteVSTH], (instregex "ST3i(8|16|32)$")>; 830def : InstRW<[M3WriteVSTH, 831 WriteAdr], (instregex "ST3i(8|16|32)_POST")>; 832def : InstRW<[M3WriteVSTF], (instregex "ST3i(64)$")>; 833def : InstRW<[M3WriteVSTF, 834 WriteAdr], (instregex "ST3i(64)_POST")>; 835 836def : InstRW<[M3WriteVSTF], (instregex "ST4Fourv(8b|4h|2s)$")>; 837def : InstRW<[M3WriteVSTF, 838 WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST")>; 839def : InstRW<[M3WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>; 840def : InstRW<[M3WriteVSTI, 841 WriteAdr], (instregex "ST4Fourv(16b|8h|4s|2d)_POST")>; 842 843def : InstRW<[M3WriteVSTF], (instregex "ST4i(8|16|32|64)$")>; 844def : InstRW<[M3WriteVSTF, 845 WriteAdr], (instregex "ST4i(8|16|32|64)_POST")>; 846 847// Cryptography instructions. 848def : InstRW<[M3WriteAES], (instregex "^AES[DE]")>; 849def : InstRW<[M3WriteAES, 850 M3ReadAES], (instregex "^AESI?MC")>; 851 852def : InstRW<[M3WriteNCRY3A], (instregex "^PMULL?v")>; 853 854def : InstRW<[M3WriteNCRY1A], (instregex "^SHA1([CHMP]|SU[01])")>; 855def : InstRW<[M3WriteNCRY1A], (instregex "^SHA256SU0")>; 856def : InstRW<[M3WriteNCRY5A], (instregex "^SHA256(H2?|SU1)")>; 857 858// CRC instructions. 859def : InstRW<[M3WriteC2], (instregex "^CRC32")>; 860 861} // SchedModel = ExynosM3Model 862