1//==- AArch64SchedA53.td - Cortex-A53 Scheduling Definitions -*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the itinerary class data for the ARM Cortex A53 processors. 10// 11//===----------------------------------------------------------------------===// 12 13// ===---------------------------------------------------------------------===// 14// The following definitions describe the simpler per-operand machine model. 15// This works with MachineScheduler. See MCSchedule.h for details. 16 17// Cortex-A53 machine model for scheduling and other instruction cost heuristics. 18def CortexA53Model : SchedMachineModel { 19 let MicroOpBufferSize = 0; // Explicitly set to zero since A53 is in-order. 20 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle. 21 let LoadLatency = 3; // Optimistic load latency assuming bypass. 22 // This is overriden by OperandCycles if the 23 // Itineraries are queried instead. 24 let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation 25 // Specification - Instruction Timings" 26 // v 1.0 Spreadsheet 27 let CompleteModel = 1; 28 29 list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F, 30 PAUnsupported.F, 31 SMEUnsupported.F, 32 [HasMTE]); 33} 34 35 36//===----------------------------------------------------------------------===// 37// Define each kind of processor resource and number available. 38 39// Modeling each pipeline as a ProcResource using the BufferSize = 0 since 40// Cortex-A53 is in-order. 41 42def A53UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU 43def A53UnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC 44def A53UnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division 45def A53UnitLdSt : ProcResource<1> { let BufferSize = 0; } // Load/Store 46def A53UnitB : ProcResource<1> { let BufferSize = 0; } // Branch 47def A53UnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU 48def A53UnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mult/Div/Sqrt 49 50 51//===----------------------------------------------------------------------===// 52// Subtarget-specific SchedWrite types which both map the ProcResources and 53// set the latency. 54 55let SchedModel = CortexA53Model in { 56 57// ALU - Despite having a full latency of 4, most of the ALU instructions can 58// forward a cycle earlier and then two cycles earlier in the case of a 59// shift-only instruction. These latencies will be incorrect when the 60// result cannot be forwarded, but modeling isn't rocket surgery. 61def : WriteRes<WriteImm, [A53UnitALU]> { let Latency = 3; } 62def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; } 63def : WriteRes<WriteISReg, [A53UnitALU]> { let Latency = 3; } 64def : WriteRes<WriteIEReg, [A53UnitALU]> { let Latency = 3; } 65def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 2; } 66def : WriteRes<WriteExtr, [A53UnitALU]> { let Latency = 3; } 67 68// MAC 69def : WriteRes<WriteIM32, [A53UnitMAC]> { let Latency = 4; } 70def : WriteRes<WriteIM64, [A53UnitMAC]> { let Latency = 4; } 71 72// Div 73def : WriteRes<WriteID32, [A53UnitDiv]> { let Latency = 4; } 74def : WriteRes<WriteID64, [A53UnitDiv]> { let Latency = 4; } 75 76// Load 77def : WriteRes<WriteLD, [A53UnitLdSt]> { let Latency = 4; } 78def : WriteRes<WriteLDIdx, [A53UnitLdSt]> { let Latency = 4; } 79def : WriteRes<WriteLDHi, [A53UnitLdSt]> { let Latency = 4; } 80 81// Vector Load - Vector loads take 1-5 cycles to issue. For the WriteVecLd 82// below, choosing the median of 3 which makes the latency 6. 83// May model this more carefully in the future. The remaining 84// A53WriteVLD# types represent the 1-5 cycle issues explicitly. 85def : WriteRes<WriteVLD, [A53UnitLdSt]> { let Latency = 6; 86 let ResourceCycles = [3]; } 87def A53WriteVLD1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; } 88def A53WriteVLD2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5; 89 let ResourceCycles = [2]; } 90def A53WriteVLD3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6; 91 let ResourceCycles = [3]; } 92def A53WriteVLD4 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 7; 93 let ResourceCycles = [4]; } 94def A53WriteVLD5 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 8; 95 let ResourceCycles = [5]; } 96 97// Pre/Post Indexing - Performed as part of address generation which is already 98// accounted for in the WriteST* latencies below 99def : WriteRes<WriteAdr, []> { let Latency = 0; } 100 101// Store 102def : WriteRes<WriteST, [A53UnitLdSt]> { let Latency = 4; } 103def : WriteRes<WriteSTP, [A53UnitLdSt]> { let Latency = 4; } 104def : WriteRes<WriteSTIdx, [A53UnitLdSt]> { let Latency = 4; } 105def : WriteRes<WriteSTX, [A53UnitLdSt]> { let Latency = 4; } 106 107// Vector Store - Similar to vector loads, can take 1-3 cycles to issue. 108def : WriteRes<WriteVST, [A53UnitLdSt]> { let Latency = 5; 109 let ResourceCycles = [2];} 110def A53WriteVST1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; } 111def A53WriteVST2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5; 112 let ResourceCycles = [2]; } 113def A53WriteVST3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6; 114 let ResourceCycles = [3]; } 115 116def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 117 118// Branch 119def : WriteRes<WriteBr, [A53UnitB]>; 120def : WriteRes<WriteBrReg, [A53UnitB]>; 121def : WriteRes<WriteSys, [A53UnitB]>; 122def : WriteRes<WriteBarrier, [A53UnitB]>; 123def : WriteRes<WriteHint, [A53UnitB]>; 124 125// FP ALU 126def : WriteRes<WriteF, [A53UnitFPALU]> { let Latency = 6; } 127def : WriteRes<WriteFCmp, [A53UnitFPALU]> { let Latency = 6; } 128def : WriteRes<WriteFCvt, [A53UnitFPALU]> { let Latency = 6; } 129def : WriteRes<WriteFCopy, [A53UnitFPALU]> { let Latency = 6; } 130def : WriteRes<WriteFImm, [A53UnitFPALU]> { let Latency = 6; } 131def : WriteRes<WriteVd, [A53UnitFPALU]> { let Latency = 6; } 132def : WriteRes<WriteVq, [A53UnitFPALU]> { let Latency = 6; } 133 134// FP Mul, Div, Sqrt 135def : WriteRes<WriteFMul, [A53UnitFPMDS]> { let Latency = 6; } 136def : WriteRes<WriteFDiv, [A53UnitFPMDS]> { let Latency = 33; 137 let ResourceCycles = [29]; } 138def A53WriteFMAC : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 10; } 139def A53WriteFDivSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 18; 140 let ResourceCycles = [14]; } 141def A53WriteFDivDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 33; 142 let ResourceCycles = [29]; } 143def A53WriteFSqrtSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 17; 144 let ResourceCycles = [13]; } 145def A53WriteFSqrtDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 32; 146 let ResourceCycles = [28]; } 147 148//===----------------------------------------------------------------------===// 149// Subtarget-specific SchedRead types. 150 151// No forwarding for these reads. 152def : ReadAdvance<ReadExtrHi, 0>; 153def : ReadAdvance<ReadAdrBase, 0>; 154def : ReadAdvance<ReadST, 0>; 155def : ReadAdvance<ReadVLD, 0>; 156 157// ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable 158// operands are needed one cycle later if and only if they are to be 159// shifted. Otherwise, they too are needed two cycles later. This same 160// ReadAdvance applies to Extended registers as well, even though there is 161// a separate SchedPredicate for them. 162def : ReadAdvance<ReadI, 2, [WriteImm,WriteI, 163 WriteISReg, WriteIEReg,WriteIS, 164 WriteID32,WriteID64, 165 WriteIM32,WriteIM64]>; 166def A53ReadShifted : SchedReadAdvance<1, [WriteImm,WriteI, 167 WriteISReg, WriteIEReg,WriteIS, 168 WriteID32,WriteID64, 169 WriteIM32,WriteIM64]>; 170def A53ReadNotShifted : SchedReadAdvance<2, [WriteImm,WriteI, 171 WriteISReg, WriteIEReg,WriteIS, 172 WriteID32,WriteID64, 173 WriteIM32,WriteIM64]>; 174def A53ReadISReg : SchedReadVariant<[ 175 SchedVar<RegShiftedPred, [A53ReadShifted]>, 176 SchedVar<NoSchedPred, [A53ReadNotShifted]>]>; 177def : SchedAlias<ReadISReg, A53ReadISReg>; 178 179def A53ReadIEReg : SchedReadVariant<[ 180 SchedVar<RegExtendedPred, [A53ReadShifted]>, 181 SchedVar<NoSchedPred, [A53ReadNotShifted]>]>; 182def : SchedAlias<ReadIEReg, A53ReadIEReg>; 183 184// MAC - Operands are generally needed one cycle later in the MAC pipe. 185// Accumulator operands are needed two cycles later. 186def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI, 187 WriteISReg, WriteIEReg,WriteIS, 188 WriteID32,WriteID64, 189 WriteIM32,WriteIM64]>; 190def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI, 191 WriteISReg, WriteIEReg,WriteIS, 192 WriteID32,WriteID64, 193 WriteIM32,WriteIM64]>; 194 195// Div 196def : ReadAdvance<ReadID, 1, [WriteImm,WriteI, 197 WriteISReg, WriteIEReg,WriteIS, 198 WriteID32,WriteID64, 199 WriteIM32,WriteIM64]>; 200 201//===----------------------------------------------------------------------===// 202// Subtarget-specific InstRWs. 203 204//--- 205// Miscellaneous 206//--- 207def : InstRW<[WriteI], (instrs COPY)>; 208 209//--- 210// Vector Loads 211//--- 212def : InstRW<[A53WriteVLD1], (instregex "LD1i(8|16|32|64)$")>; 213def : InstRW<[A53WriteVLD1], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 214def : InstRW<[A53WriteVLD1], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 215def : InstRW<[A53WriteVLD2], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 216def : InstRW<[A53WriteVLD3], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 217def : InstRW<[A53WriteVLD4], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 218def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>; 219def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 220def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 221def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 222def : InstRW<[A53WriteVLD3, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 223def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 224 225def : InstRW<[A53WriteVLD1], (instregex "LD2i(8|16|32|64)$")>; 226def : InstRW<[A53WriteVLD1], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 227def : InstRW<[A53WriteVLD2], (instregex "LD2Twov(8b|4h|2s)$")>; 228def : InstRW<[A53WriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)$")>; 229def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD2i(8|16|32|64)_POST$")>; 230def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 231def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST$")>; 232def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>; 233 234def : InstRW<[A53WriteVLD2], (instregex "LD3i(8|16|32|64)$")>; 235def : InstRW<[A53WriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 236def : InstRW<[A53WriteVLD4], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)$")>; 237def : InstRW<[A53WriteVLD3], (instregex "LD3Threev2d$")>; 238def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD3i(8|16|32|64)_POST$")>; 239def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 240def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>; 241def : InstRW<[A53WriteVLD3, WriteAdr], (instregex "LD3Threev2d_POST$")>; 242 243def : InstRW<[A53WriteVLD2], (instregex "LD4i(8|16|32|64)$")>; 244def : InstRW<[A53WriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 245def : InstRW<[A53WriteVLD5], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>; 246def : InstRW<[A53WriteVLD4], (instregex "LD4Fourv(2d)$")>; 247def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD4i(8|16|32|64)_POST$")>; 248def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 249def : InstRW<[A53WriteVLD5, WriteAdr], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>; 250def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>; 251 252//--- 253// Vector Stores 254//--- 255def : InstRW<[A53WriteVST1], (instregex "ST1i(8|16|32|64)$")>; 256def : InstRW<[A53WriteVST1], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 257def : InstRW<[A53WriteVST1], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 258def : InstRW<[A53WriteVST2], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 259def : InstRW<[A53WriteVST2], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 260def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1i(8|16|32|64)_POST$")>; 261def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 262def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 263def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 264def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 265 266def : InstRW<[A53WriteVST1], (instregex "ST2i(8|16|32|64)$")>; 267def : InstRW<[A53WriteVST1], (instregex "ST2Twov(8b|4h|2s)$")>; 268def : InstRW<[A53WriteVST2], (instregex "ST2Twov(16b|8h|4s|2d)$")>; 269def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST2i(8|16|32|64)_POST$")>; 270def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>; 271def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>; 272 273def : InstRW<[A53WriteVST2], (instregex "ST3i(8|16|32|64)$")>; 274def : InstRW<[A53WriteVST3], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)$")>; 275def : InstRW<[A53WriteVST2], (instregex "ST3Threev(2d)$")>; 276def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST3i(8|16|32|64)_POST$")>; 277def : InstRW<[A53WriteVST3, WriteAdr], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>; 278def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST3Threev(2d)_POST$")>; 279 280def : InstRW<[A53WriteVST2], (instregex "ST4i(8|16|32|64)$")>; 281def : InstRW<[A53WriteVST3], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>; 282def : InstRW<[A53WriteVST2], (instregex "ST4Fourv(2d)$")>; 283def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST4i(8|16|32|64)_POST$")>; 284def : InstRW<[A53WriteVST3, WriteAdr], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>; 285def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>; 286 287//--- 288// Floating Point MAC, DIV, SQRT 289//--- 290def : InstRW<[A53WriteFMAC], (instregex "^FN?M(ADD|SUB).*")>; 291def : InstRW<[A53WriteFMAC], (instregex "^FML(A|S).*")>; 292def : InstRW<[A53WriteFDivSP], (instrs FDIVSrr)>; 293def : InstRW<[A53WriteFDivDP], (instrs FDIVDrr)>; 294def : InstRW<[A53WriteFDivSP], (instregex "^FDIVv.*32$")>; 295def : InstRW<[A53WriteFDivDP], (instregex "^FDIVv.*64$")>; 296def : InstRW<[A53WriteFSqrtSP], (instregex "^.*SQRT.*32$")>; 297def : InstRW<[A53WriteFSqrtDP], (instregex "^.*SQRT.*64$")>; 298 299} 300