1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the AArch64 implementation of the TargetRegisterInfo 10 // class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "AArch64RegisterInfo.h" 15 #include "AArch64FrameLowering.h" 16 #include "AArch64InstrInfo.h" 17 #include "AArch64MachineFunctionInfo.h" 18 #include "AArch64StackOffset.h" 19 #include "AArch64Subtarget.h" 20 #include "MCTargetDesc/AArch64AddressingModes.h" 21 #include "llvm/ADT/BitVector.h" 22 #include "llvm/ADT/Triple.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/CodeGen/MachineInstrBuilder.h" 25 #include "llvm/CodeGen/MachineRegisterInfo.h" 26 #include "llvm/CodeGen/RegisterScavenging.h" 27 #include "llvm/CodeGen/TargetFrameLowering.h" 28 #include "llvm/IR/DiagnosticInfo.h" 29 #include "llvm/IR/Function.h" 30 #include "llvm/Support/raw_ostream.h" 31 #include "llvm/Target/TargetOptions.h" 32 33 using namespace llvm; 34 35 #define GET_REGINFO_TARGET_DESC 36 #include "AArch64GenRegisterInfo.inc" 37 38 AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT) 39 : AArch64GenRegisterInfo(AArch64::LR), TT(TT) { 40 AArch64_MC::initLLVMToCVRegMapping(this); 41 } 42 43 const MCPhysReg * 44 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 45 assert(MF && "Invalid MachineFunction pointer."); 46 if (MF->getSubtarget<AArch64Subtarget>().isTargetWindows()) 47 return CSR_Win_AArch64_AAPCS_SaveList; 48 if (MF->getFunction().getCallingConv() == CallingConv::GHC) 49 // GHC set of callee saved regs is empty as all those regs are 50 // used for passing STG regs around 51 return CSR_AArch64_NoRegs_SaveList; 52 if (MF->getFunction().getCallingConv() == CallingConv::AnyReg) 53 return CSR_AArch64_AllRegs_SaveList; 54 if (MF->getFunction().getCallingConv() == CallingConv::AArch64_VectorCall) 55 return CSR_AArch64_AAVPCS_SaveList; 56 if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS) 57 return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ? 58 CSR_AArch64_CXX_TLS_Darwin_PE_SaveList : 59 CSR_AArch64_CXX_TLS_Darwin_SaveList; 60 if (MF->getSubtarget<AArch64Subtarget>().getTargetLowering() 61 ->supportSwiftError() && 62 MF->getFunction().getAttributes().hasAttrSomewhere( 63 Attribute::SwiftError)) 64 return CSR_AArch64_AAPCS_SwiftError_SaveList; 65 if (MF->getFunction().getCallingConv() == CallingConv::PreserveMost) 66 return CSR_AArch64_RT_MostRegs_SaveList; 67 if (MF->getSubtarget<AArch64Subtarget>().isTargetDarwin()) 68 return CSR_Darwin_AArch64_AAPCS_SaveList; 69 return CSR_AArch64_AAPCS_SaveList; 70 } 71 72 const MCPhysReg *AArch64RegisterInfo::getCalleeSavedRegsViaCopy( 73 const MachineFunction *MF) const { 74 assert(MF && "Invalid MachineFunction pointer."); 75 if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && 76 MF->getInfo<AArch64FunctionInfo>()->isSplitCSR()) 77 return CSR_AArch64_CXX_TLS_Darwin_ViaCopy_SaveList; 78 return nullptr; 79 } 80 81 void AArch64RegisterInfo::UpdateCustomCalleeSavedRegs( 82 MachineFunction &MF) const { 83 const MCPhysReg *CSRs = getCalleeSavedRegs(&MF); 84 SmallVector<MCPhysReg, 32> UpdatedCSRs; 85 for (const MCPhysReg *I = CSRs; *I; ++I) 86 UpdatedCSRs.push_back(*I); 87 88 for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) { 89 if (MF.getSubtarget<AArch64Subtarget>().isXRegCustomCalleeSaved(i)) { 90 UpdatedCSRs.push_back(AArch64::GPR64commonRegClass.getRegister(i)); 91 } 92 } 93 // Register lists are zero-terminated. 94 UpdatedCSRs.push_back(0); 95 MF.getRegInfo().setCalleeSavedRegs(UpdatedCSRs); 96 } 97 98 const TargetRegisterClass * 99 AArch64RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, 100 unsigned Idx) const { 101 // edge case for GPR/FPR register classes 102 if (RC == &AArch64::GPR32allRegClass && Idx == AArch64::hsub) 103 return &AArch64::FPR32RegClass; 104 else if (RC == &AArch64::GPR64allRegClass && Idx == AArch64::hsub) 105 return &AArch64::FPR64RegClass; 106 107 // Forward to TableGen's default version. 108 return AArch64GenRegisterInfo::getSubClassWithSubReg(RC, Idx); 109 } 110 111 const uint32_t * 112 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF, 113 CallingConv::ID CC) const { 114 bool SCS = MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack); 115 if (CC == CallingConv::GHC) 116 // This is academic because all GHC calls are (supposed to be) tail calls 117 return SCS ? CSR_AArch64_NoRegs_SCS_RegMask : CSR_AArch64_NoRegs_RegMask; 118 if (CC == CallingConv::AnyReg) 119 return SCS ? CSR_AArch64_AllRegs_SCS_RegMask : CSR_AArch64_AllRegs_RegMask; 120 if (CC == CallingConv::CXX_FAST_TLS) 121 return SCS ? CSR_AArch64_CXX_TLS_Darwin_SCS_RegMask 122 : CSR_AArch64_CXX_TLS_Darwin_RegMask; 123 if (CC == CallingConv::AArch64_VectorCall) 124 return SCS ? CSR_AArch64_AAVPCS_SCS_RegMask : CSR_AArch64_AAVPCS_RegMask; 125 if (CC == CallingConv::AArch64_SVE_VectorCall) 126 return CSR_AArch64_SVE_AAPCS_RegMask; 127 if (MF.getSubtarget<AArch64Subtarget>().getTargetLowering() 128 ->supportSwiftError() && 129 MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError)) 130 return SCS ? CSR_AArch64_AAPCS_SwiftError_SCS_RegMask 131 : CSR_AArch64_AAPCS_SwiftError_RegMask; 132 if (CC == CallingConv::PreserveMost) 133 return SCS ? CSR_AArch64_RT_MostRegs_SCS_RegMask 134 : CSR_AArch64_RT_MostRegs_RegMask; 135 else 136 return SCS ? CSR_AArch64_AAPCS_SCS_RegMask : CSR_AArch64_AAPCS_RegMask; 137 } 138 139 const uint32_t *AArch64RegisterInfo::getTLSCallPreservedMask() const { 140 if (TT.isOSDarwin()) 141 return CSR_AArch64_TLS_Darwin_RegMask; 142 143 assert(TT.isOSBinFormatELF() && "Invalid target"); 144 return CSR_AArch64_TLS_ELF_RegMask; 145 } 146 147 void AArch64RegisterInfo::UpdateCustomCallPreservedMask(MachineFunction &MF, 148 const uint32_t **Mask) const { 149 uint32_t *UpdatedMask = MF.allocateRegMask(); 150 unsigned RegMaskSize = MachineOperand::getRegMaskSize(getNumRegs()); 151 memcpy(UpdatedMask, *Mask, sizeof(UpdatedMask[0]) * RegMaskSize); 152 153 for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) { 154 if (MF.getSubtarget<AArch64Subtarget>().isXRegCustomCalleeSaved(i)) { 155 for (MCSubRegIterator SubReg(AArch64::GPR64commonRegClass.getRegister(i), 156 this, true); 157 SubReg.isValid(); ++SubReg) { 158 // See TargetRegisterInfo::getCallPreservedMask for how to interpret the 159 // register mask. 160 UpdatedMask[*SubReg / 32] |= 1u << (*SubReg % 32); 161 } 162 } 163 } 164 *Mask = UpdatedMask; 165 } 166 167 const uint32_t *AArch64RegisterInfo::getNoPreservedMask() const { 168 return CSR_AArch64_NoRegs_RegMask; 169 } 170 171 const uint32_t * 172 AArch64RegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF, 173 CallingConv::ID CC) const { 174 // This should return a register mask that is the same as that returned by 175 // getCallPreservedMask but that additionally preserves the register used for 176 // the first i64 argument (which must also be the register used to return a 177 // single i64 return value) 178 // 179 // In case that the calling convention does not use the same register for 180 // both, the function should return NULL (does not currently apply) 181 assert(CC != CallingConv::GHC && "should not be GHC calling convention."); 182 return CSR_AArch64_AAPCS_ThisReturn_RegMask; 183 } 184 185 const uint32_t *AArch64RegisterInfo::getWindowsStackProbePreservedMask() const { 186 return CSR_AArch64_StackProbe_Windows_RegMask; 187 } 188 189 BitVector 190 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const { 191 const AArch64FrameLowering *TFI = getFrameLowering(MF); 192 193 // FIXME: avoid re-calculating this every time. 194 BitVector Reserved(getNumRegs()); 195 markSuperRegs(Reserved, AArch64::WSP); 196 markSuperRegs(Reserved, AArch64::WZR); 197 198 if (TFI->hasFP(MF) || TT.isOSDarwin()) 199 markSuperRegs(Reserved, AArch64::W29); 200 201 for (size_t i = 0; i < AArch64::GPR32commonRegClass.getNumRegs(); ++i) { 202 if (MF.getSubtarget<AArch64Subtarget>().isXRegisterReserved(i)) 203 markSuperRegs(Reserved, AArch64::GPR32commonRegClass.getRegister(i)); 204 } 205 206 if (hasBasePointer(MF)) 207 markSuperRegs(Reserved, AArch64::W19); 208 209 // SLH uses register W16/X16 as the taint register. 210 if (MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening)) 211 markSuperRegs(Reserved, AArch64::W16); 212 213 assert(checkAllSuperRegsMarked(Reserved)); 214 return Reserved; 215 } 216 217 bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF, 218 unsigned Reg) const { 219 return getReservedRegs(MF)[Reg]; 220 } 221 222 bool AArch64RegisterInfo::isAnyArgRegReserved(const MachineFunction &MF) const { 223 return std::any_of(std::begin(*AArch64::GPR64argRegClass.MC), 224 std::end(*AArch64::GPR64argRegClass.MC), 225 [this, &MF](MCPhysReg r){return isReservedReg(MF, r);}); 226 } 227 228 void AArch64RegisterInfo::emitReservedArgRegCallError( 229 const MachineFunction &MF) const { 230 const Function &F = MF.getFunction(); 231 F.getContext().diagnose(DiagnosticInfoUnsupported{F, "AArch64 doesn't support" 232 " function calls if any of the argument registers is reserved."}); 233 } 234 235 bool AArch64RegisterInfo::isAsmClobberable(const MachineFunction &MF, 236 unsigned PhysReg) const { 237 return !isReservedReg(MF, PhysReg); 238 } 239 240 bool AArch64RegisterInfo::isConstantPhysReg(unsigned PhysReg) const { 241 return PhysReg == AArch64::WZR || PhysReg == AArch64::XZR; 242 } 243 244 const TargetRegisterClass * 245 AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF, 246 unsigned Kind) const { 247 return &AArch64::GPR64spRegClass; 248 } 249 250 const TargetRegisterClass * 251 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 252 if (RC == &AArch64::CCRRegClass) 253 return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV. 254 return RC; 255 } 256 257 unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; } 258 259 bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const { 260 const MachineFrameInfo &MFI = MF.getFrameInfo(); 261 262 // In the presence of variable sized objects or funclets, if the fixed stack 263 // size is large enough that referencing from the FP won't result in things 264 // being in range relatively often, we can use a base pointer to allow access 265 // from the other direction like the SP normally works. 266 // 267 // Furthermore, if both variable sized objects are present, and the 268 // stack needs to be dynamically re-aligned, the base pointer is the only 269 // reliable way to reference the locals. 270 if (MFI.hasVarSizedObjects() || MF.hasEHFunclets()) { 271 if (needsStackRealignment(MF)) 272 return true; 273 // Conservatively estimate whether the negative offset from the frame 274 // pointer will be sufficient to reach. If a function has a smallish 275 // frame, it's less likely to have lots of spills and callee saved 276 // space, so it's all more likely to be within range of the frame pointer. 277 // If it's wrong, we'll materialize the constant and still get to the 278 // object; it's just suboptimal. Negative offsets use the unscaled 279 // load/store instructions, which have a 9-bit signed immediate. 280 return MFI.getLocalFrameSize() >= 256; 281 } 282 283 return false; 284 } 285 286 Register 287 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const { 288 const AArch64FrameLowering *TFI = getFrameLowering(MF); 289 return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP; 290 } 291 292 bool AArch64RegisterInfo::requiresRegisterScavenging( 293 const MachineFunction &MF) const { 294 return true; 295 } 296 297 bool AArch64RegisterInfo::requiresVirtualBaseRegisters( 298 const MachineFunction &MF) const { 299 return true; 300 } 301 302 bool 303 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const { 304 // This function indicates whether the emergency spillslot should be placed 305 // close to the beginning of the stackframe (closer to FP) or the end 306 // (closer to SP). 307 // 308 // The beginning works most reliably if we have a frame pointer. 309 const AArch64FrameLowering &TFI = *getFrameLowering(MF); 310 return TFI.hasFP(MF); 311 } 312 313 bool AArch64RegisterInfo::requiresFrameIndexScavenging( 314 const MachineFunction &MF) const { 315 return true; 316 } 317 318 bool 319 AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const { 320 const MachineFrameInfo &MFI = MF.getFrameInfo(); 321 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI.adjustsStack()) 322 return true; 323 return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken(); 324 } 325 326 /// needsFrameBaseReg - Returns true if the instruction's frame index 327 /// reference would be better served by a base register other than FP 328 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 329 /// references it should create new base registers for. 330 bool AArch64RegisterInfo::needsFrameBaseReg(MachineInstr *MI, 331 int64_t Offset) const { 332 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) 333 assert(i < MI->getNumOperands() && 334 "Instr doesn't have FrameIndex operand!"); 335 336 // It's the load/store FI references that cause issues, as it can be difficult 337 // to materialize the offset if it won't fit in the literal field. Estimate 338 // based on the size of the local frame and some conservative assumptions 339 // about the rest of the stack frame (note, this is pre-regalloc, so 340 // we don't know everything for certain yet) whether this offset is likely 341 // to be out of range of the immediate. Return true if so. 342 343 // We only generate virtual base registers for loads and stores, so 344 // return false for everything else. 345 if (!MI->mayLoad() && !MI->mayStore()) 346 return false; 347 348 // Without a virtual base register, if the function has variable sized 349 // objects, all fixed-size local references will be via the frame pointer, 350 // Approximate the offset and see if it's legal for the instruction. 351 // Note that the incoming offset is based on the SP value at function entry, 352 // so it'll be negative. 353 MachineFunction &MF = *MI->getParent()->getParent(); 354 const AArch64FrameLowering *TFI = getFrameLowering(MF); 355 MachineFrameInfo &MFI = MF.getFrameInfo(); 356 357 // Estimate an offset from the frame pointer. 358 // Conservatively assume all GPR callee-saved registers get pushed. 359 // FP, LR, X19-X28, D8-D15. 64-bits each. 360 int64_t FPOffset = Offset - 16 * 20; 361 // Estimate an offset from the stack pointer. 362 // The incoming offset is relating to the SP at the start of the function, 363 // but when we access the local it'll be relative to the SP after local 364 // allocation, so adjust our SP-relative offset by that allocation size. 365 Offset += MFI.getLocalFrameSize(); 366 // Assume that we'll have at least some spill slots allocated. 367 // FIXME: This is a total SWAG number. We should run some statistics 368 // and pick a real one. 369 Offset += 128; // 128 bytes of spill slots 370 371 // If there is a frame pointer, try using it. 372 // The FP is only available if there is no dynamic realignment. We 373 // don't know for sure yet whether we'll need that, so we guess based 374 // on whether there are any local variables that would trigger it. 375 if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset)) 376 return false; 377 378 // If we can reference via the stack pointer or base pointer, try that. 379 // FIXME: This (and the code that resolves the references) can be improved 380 // to only disallow SP relative references in the live range of 381 // the VLA(s). In practice, it's unclear how much difference that 382 // would make, but it may be worth doing. 383 if (isFrameOffsetLegal(MI, AArch64::SP, Offset)) 384 return false; 385 386 // The offset likely isn't legal; we want to allocate a virtual base register. 387 return true; 388 } 389 390 bool AArch64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 391 unsigned BaseReg, 392 int64_t Offset) const { 393 assert(Offset <= INT_MAX && "Offset too big to fit in int."); 394 assert(MI && "Unable to get the legal offset for nil instruction."); 395 StackOffset SaveOffset(Offset, MVT::i8); 396 return isAArch64FrameOffsetLegal(*MI, SaveOffset) & AArch64FrameOffsetIsLegal; 397 } 398 399 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx 400 /// at the beginning of the basic block. 401 void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, 402 unsigned BaseReg, 403 int FrameIdx, 404 int64_t Offset) const { 405 MachineBasicBlock::iterator Ins = MBB->begin(); 406 DebugLoc DL; // Defaults to "unknown" 407 if (Ins != MBB->end()) 408 DL = Ins->getDebugLoc(); 409 const MachineFunction &MF = *MBB->getParent(); 410 const AArch64InstrInfo *TII = 411 MF.getSubtarget<AArch64Subtarget>().getInstrInfo(); 412 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri); 413 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 414 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF)); 415 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0); 416 417 BuildMI(*MBB, Ins, DL, MCID, BaseReg) 418 .addFrameIndex(FrameIdx) 419 .addImm(Offset) 420 .addImm(Shifter); 421 } 422 423 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 424 int64_t Offset) const { 425 // ARM doesn't need the general 64-bit offsets 426 StackOffset Off(Offset, MVT::i8); 427 428 unsigned i = 0; 429 430 while (!MI.getOperand(i).isFI()) { 431 ++i; 432 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 433 } 434 const MachineFunction *MF = MI.getParent()->getParent(); 435 const AArch64InstrInfo *TII = 436 MF->getSubtarget<AArch64Subtarget>().getInstrInfo(); 437 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII); 438 assert(Done && "Unable to resolve frame index!"); 439 (void)Done; 440 } 441 442 void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 443 int SPAdj, unsigned FIOperandNum, 444 RegScavenger *RS) const { 445 assert(SPAdj == 0 && "Unexpected"); 446 447 MachineInstr &MI = *II; 448 MachineBasicBlock &MBB = *MI.getParent(); 449 MachineFunction &MF = *MBB.getParent(); 450 const MachineFrameInfo &MFI = MF.getFrameInfo(); 451 const AArch64InstrInfo *TII = 452 MF.getSubtarget<AArch64Subtarget>().getInstrInfo(); 453 const AArch64FrameLowering *TFI = getFrameLowering(MF); 454 455 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 456 bool Tagged = 457 MI.getOperand(FIOperandNum).getTargetFlags() & AArch64II::MO_TAGGED; 458 unsigned FrameReg; 459 460 // Special handling of dbg_value, stackmap and patchpoint instructions. 461 if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP || 462 MI.getOpcode() == TargetOpcode::PATCHPOINT) { 463 StackOffset Offset = 464 TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg, 465 /*PreferFP=*/true, 466 /*ForSimm=*/false); 467 Offset += StackOffset(MI.getOperand(FIOperandNum + 1).getImm(), MVT::i8); 468 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/); 469 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getBytes()); 470 return; 471 } 472 473 if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE) { 474 MachineOperand &FI = MI.getOperand(FIOperandNum); 475 int Offset = TFI->getNonLocalFrameIndexReference(MF, FrameIndex); 476 FI.ChangeToImmediate(Offset); 477 return; 478 } 479 480 StackOffset Offset; 481 if (MI.getOpcode() == AArch64::TAGPstack) { 482 // TAGPstack must use the virtual frame register in its 3rd operand. 483 const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>(); 484 FrameReg = MI.getOperand(3).getReg(); 485 Offset = {MFI.getObjectOffset(FrameIndex) + 486 AFI->getTaggedBasePointerOffset(), 487 MVT::i8}; 488 } else if (Tagged) { 489 StackOffset SPOffset = { 490 MFI.getObjectOffset(FrameIndex) + (int64_t)MFI.getStackSize(), MVT::i8}; 491 if (MFI.hasVarSizedObjects() || 492 isAArch64FrameOffsetLegal(MI, SPOffset, nullptr, nullptr, nullptr) != 493 (AArch64FrameOffsetCanUpdate | AArch64FrameOffsetIsLegal)) { 494 // Can't update to SP + offset in place. Precalculate the tagged pointer 495 // in a scratch register. 496 Offset = TFI->resolveFrameIndexReference( 497 MF, FrameIndex, FrameReg, /*PreferFP=*/false, /*ForSimm=*/true); 498 Register ScratchReg = 499 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); 500 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, 501 TII); 502 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(AArch64::LDG), ScratchReg) 503 .addReg(ScratchReg) 504 .addReg(ScratchReg) 505 .addImm(0); 506 MI.getOperand(FIOperandNum) 507 .ChangeToRegister(ScratchReg, false, false, true); 508 return; 509 } 510 FrameReg = AArch64::SP; 511 Offset = {MFI.getObjectOffset(FrameIndex) + (int64_t)MFI.getStackSize(), 512 MVT::i8}; 513 } else { 514 Offset = TFI->resolveFrameIndexReference( 515 MF, FrameIndex, FrameReg, /*PreferFP=*/false, /*ForSimm=*/true); 516 } 517 518 // Modify MI as necessary to handle as much of 'Offset' as possible 519 if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII)) 520 return; 521 522 assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) && 523 "Emergency spill slot is out of reach"); 524 525 // If we get here, the immediate doesn't fit into the instruction. We folded 526 // as much as possible above. Handle the rest, providing a register that is 527 // SP+LargeImm. 528 Register ScratchReg = 529 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); 530 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII); 531 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true); 532 } 533 534 unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 535 MachineFunction &MF) const { 536 const AArch64FrameLowering *TFI = getFrameLowering(MF); 537 538 switch (RC->getID()) { 539 default: 540 return 0; 541 case AArch64::GPR32RegClassID: 542 case AArch64::GPR32spRegClassID: 543 case AArch64::GPR32allRegClassID: 544 case AArch64::GPR64spRegClassID: 545 case AArch64::GPR64allRegClassID: 546 case AArch64::GPR64RegClassID: 547 case AArch64::GPR32commonRegClassID: 548 case AArch64::GPR64commonRegClassID: 549 return 32 - 1 // XZR/SP 550 - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP 551 - MF.getSubtarget<AArch64Subtarget>().getNumXRegisterReserved() 552 - hasBasePointer(MF); // X19 553 case AArch64::FPR8RegClassID: 554 case AArch64::FPR16RegClassID: 555 case AArch64::FPR32RegClassID: 556 case AArch64::FPR64RegClassID: 557 case AArch64::FPR128RegClassID: 558 return 32; 559 560 case AArch64::DDRegClassID: 561 case AArch64::DDDRegClassID: 562 case AArch64::DDDDRegClassID: 563 case AArch64::QQRegClassID: 564 case AArch64::QQQRegClassID: 565 case AArch64::QQQQRegClassID: 566 return 32; 567 568 case AArch64::FPR128_loRegClassID: 569 return 16; 570 } 571 } 572 573 unsigned AArch64RegisterInfo::getLocalAddressRegister( 574 const MachineFunction &MF) const { 575 const auto &MFI = MF.getFrameInfo(); 576 if (!MF.hasEHFunclets() && !MFI.hasVarSizedObjects()) 577 return AArch64::SP; 578 else if (needsStackRealignment(MF)) 579 return getBaseRegister(); 580 return getFrameRegister(MF); 581 } 582