1 //===- AArch64PostCoalescerPass.cpp - AArch64 Post Coalescer pass ---------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===// 9 10 #include "AArch64InstrInfo.h" 11 #include "AArch64MachineFunctionInfo.h" 12 #include "llvm/CodeGen/LiveIntervals.h" 13 #include "llvm/CodeGen/MachineRegisterInfo.h" 14 #include "llvm/InitializePasses.h" 15 16 using namespace llvm; 17 18 #define DEBUG_TYPE "aarch64-post-coalescer-pass" 19 20 namespace { 21 22 struct AArch64PostCoalescer : public MachineFunctionPass { 23 static char ID; 24 25 AArch64PostCoalescer() : MachineFunctionPass(ID) { 26 initializeAArch64PostCoalescerPass(*PassRegistry::getPassRegistry()); 27 } 28 29 LiveIntervals *LIS; 30 MachineRegisterInfo *MRI; 31 32 bool runOnMachineFunction(MachineFunction &MF) override; 33 34 StringRef getPassName() const override { 35 return "AArch64 Post Coalescer pass"; 36 } 37 38 void getAnalysisUsage(AnalysisUsage &AU) const override { 39 AU.setPreservesAll(); 40 AU.addRequired<LiveIntervalsWrapperPass>(); 41 MachineFunctionPass::getAnalysisUsage(AU); 42 } 43 }; 44 45 char AArch64PostCoalescer::ID = 0; 46 47 } // end anonymous namespace 48 49 INITIALIZE_PASS_BEGIN(AArch64PostCoalescer, "aarch64-post-coalescer-pass", 50 "AArch64 Post Coalescer Pass", false, false) 51 INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass) 52 INITIALIZE_PASS_END(AArch64PostCoalescer, "aarch64-post-coalescer-pass", 53 "AArch64 Post Coalescer Pass", false, false) 54 55 bool AArch64PostCoalescer::runOnMachineFunction(MachineFunction &MF) { 56 if (skipFunction(MF.getFunction())) 57 return false; 58 59 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>(); 60 if (!FuncInfo->hasStreamingModeChanges()) 61 return false; 62 63 MRI = &MF.getRegInfo(); 64 LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS(); 65 bool Changed = false; 66 67 for (MachineBasicBlock &MBB : MF) { 68 for (MachineInstr &MI : make_early_inc_range(MBB)) { 69 switch (MI.getOpcode()) { 70 default: 71 break; 72 case AArch64::COALESCER_BARRIER_FPR16: 73 case AArch64::COALESCER_BARRIER_FPR32: 74 case AArch64::COALESCER_BARRIER_FPR64: 75 case AArch64::COALESCER_BARRIER_FPR128: { 76 Register Src = MI.getOperand(1).getReg(); 77 Register Dst = MI.getOperand(0).getReg(); 78 if (Src != Dst) 79 MRI->replaceRegWith(Dst, Src); 80 81 // MI must be erased from the basic block before recalculating the live 82 // interval. 83 LIS->RemoveMachineInstrFromMaps(MI); 84 MI.eraseFromParent(); 85 86 LIS->removeInterval(Src); 87 LIS->createAndComputeVirtRegInterval(Src); 88 89 Changed = true; 90 break; 91 } 92 } 93 } 94 } 95 96 return Changed; 97 } 98 99 FunctionPass *llvm::createAArch64PostCoalescerPass() { 100 return new AArch64PostCoalescer(); 101 } 102